1 /* 2 * linux/include/asm-arm/proc-armv/ptrace.h 3 * 4 * Copyright (C) 1996-1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __ASM_PROC_PTRACE_H 11 #define __ASM_PROC_PTRACE_H 12 13 #ifdef CONFIG_ARM64 14 15 #define PCMASK 0 16 17 /* 18 * PSR bits 19 */ 20 #define PSR_MODE_EL0t 0x00000000 21 #define PSR_MODE_EL1t 0x00000004 22 #define PSR_MODE_EL1h 0x00000005 23 #define PSR_MODE_EL2t 0x00000008 24 #define PSR_MODE_EL2h 0x00000009 25 #define PSR_MODE_EL3t 0x0000000c 26 #define PSR_MODE_EL3h 0x0000000d 27 #define PSR_MODE_MASK 0x0000000f 28 29 /* AArch32 CPSR bits */ 30 #define PSR_MODE32_BIT 0x00000010 31 32 /* AArch64 SPSR bits */ 33 #define PSR_F_BIT 0x00000040 34 #define PSR_I_BIT 0x00000080 35 #define PSR_A_BIT 0x00000100 36 #define PSR_D_BIT 0x00000200 37 #define PSR_BTYPE_MASK 0x00000c00 38 #define PSR_SSBS_BIT 0x00001000 39 #define PSR_PAN_BIT 0x00400000 40 #define PSR_UAO_BIT 0x00800000 41 #define PSR_DIT_BIT 0x01000000 42 #define PSR_TCO_BIT 0x02000000 43 #define PSR_V_BIT 0x10000000 44 #define PSR_C_BIT 0x20000000 45 #define PSR_Z_BIT 0x40000000 46 #define PSR_N_BIT 0x80000000 47 48 #define PSR_BTYPE_SHIFT 10 49 50 /* 51 * Groups of PSR bits 52 */ 53 #define PSR_f 0xff000000 /* Flags */ 54 #define PSR_s 0x00ff0000 /* Status */ 55 #define PSR_x 0x0000ff00 /* Extension */ 56 #define PSR_c 0x000000ff /* Control */ 57 58 /* Convenience names for the values of PSTATE.BTYPE */ 59 #define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT) 60 #define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT) 61 #define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT) 62 #define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT) 63 64 /* SPSR_ELx bits for exceptions taken from AArch32 */ 65 #define PSR_AA32_MODE_MASK 0x0000001f 66 #define PSR_AA32_MODE_USR 0x00000010 67 #define PSR_AA32_MODE_FIQ 0x00000011 68 #define PSR_AA32_MODE_IRQ 0x00000012 69 #define PSR_AA32_MODE_SVC 0x00000013 70 #define PSR_AA32_MODE_ABT 0x00000017 71 #define PSR_AA32_MODE_HYP 0x0000001a 72 #define PSR_AA32_MODE_UND 0x0000001b 73 #define PSR_AA32_MODE_SYS 0x0000001f 74 #define PSR_AA32_T_BIT 0x00000020 75 #define PSR_AA32_F_BIT 0x00000040 76 #define PSR_AA32_I_BIT 0x00000080 77 #define PSR_AA32_A_BIT 0x00000100 78 #define PSR_AA32_E_BIT 0x00000200 79 #define PSR_AA32_PAN_BIT 0x00400000 80 #define PSR_AA32_SSBS_BIT 0x00800000 81 #define PSR_AA32_DIT_BIT 0x01000000 82 #define PSR_AA32_Q_BIT 0x08000000 83 #define PSR_AA32_V_BIT 0x10000000 84 #define PSR_AA32_C_BIT 0x20000000 85 #define PSR_AA32_Z_BIT 0x40000000 86 #define PSR_AA32_N_BIT 0x80000000 87 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 88 #define PSR_AA32_GE_MASK 0x000f0000 89 90 #ifndef __ASSEMBLY__ 91 92 /* 93 * This struct defines the way the registers are stored 94 * on the stack during an exception. 95 */ 96 struct pt_regs { 97 unsigned long spsr; 98 unsigned long elr; 99 unsigned long esr; 100 unsigned long regs[31]; 101 }; 102 103 #endif /* __ASSEMBLY__ */ 104 105 #else /* CONFIG_ARM64 */ 106 107 #define USR26_MODE 0x00 108 #define FIQ26_MODE 0x01 109 #define IRQ26_MODE 0x02 110 #define SVC26_MODE 0x03 111 #define USR_MODE 0x10 112 #define FIQ_MODE 0x11 113 #define IRQ_MODE 0x12 114 #define SVC_MODE 0x13 115 #define MON_MODE 0x16 116 #define ABT_MODE 0x17 117 #define HYP_MODE 0x1a 118 #define UND_MODE 0x1b 119 #define SYSTEM_MODE 0x1f 120 #define MODE_MASK 0x1f 121 #define T_BIT 0x20 122 #define F_BIT 0x40 123 #define I_BIT 0x80 124 #define A_BIT 0x100 125 #define CC_V_BIT (1 << 28) 126 #define CC_C_BIT (1 << 29) 127 #define CC_Z_BIT (1 << 30) 128 #define CC_N_BIT (1 << 31) 129 #define PCMASK 0 130 131 #ifndef __ASSEMBLY__ 132 133 /* this struct defines the way the registers are stored on the 134 stack during a system call. */ 135 136 struct pt_regs { 137 long uregs[18]; 138 }; 139 140 #define ARM_cpsr uregs[16] 141 #define ARM_pc uregs[15] 142 #define ARM_lr uregs[14] 143 #define ARM_sp uregs[13] 144 #define ARM_ip uregs[12] 145 #define ARM_fp uregs[11] 146 #define ARM_r10 uregs[10] 147 #define ARM_r9 uregs[9] 148 #define ARM_r8 uregs[8] 149 #define ARM_r7 uregs[7] 150 #define ARM_r6 uregs[6] 151 #define ARM_r5 uregs[5] 152 #define ARM_r4 uregs[4] 153 #define ARM_r3 uregs[3] 154 #define ARM_r2 uregs[2] 155 #define ARM_r1 uregs[1] 156 #define ARM_r0 uregs[0] 157 #define ARM_ORIG_r0 uregs[17] 158 159 #ifdef __KERNEL__ 160 161 #define user_mode(regs) \ 162 (((regs)->ARM_cpsr & 0xf) == 0) 163 164 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) 165 #define thumb_mode(regs) \ 166 (((regs)->ARM_cpsr & T_BIT)) 167 #else 168 #define thumb_mode(regs) (0) 169 #endif 170 171 #define processor_mode(regs) \ 172 ((regs)->ARM_cpsr & MODE_MASK) 173 174 #define interrupts_enabled(regs) \ 175 (!((regs)->ARM_cpsr & I_BIT)) 176 177 #define fast_interrupts_enabled(regs) \ 178 (!((regs)->ARM_cpsr & F_BIT)) 179 180 #define condition_codes(regs) \ 181 ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) 182 183 /* Are the current registers suitable for user mode? 184 * (used to maintain security in signal handlers) 185 */ valid_user_regs(struct pt_regs * regs)186static inline int valid_user_regs(struct pt_regs *regs) 187 { 188 if ((regs->ARM_cpsr & 0xf) == 0 && 189 (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) 190 return 1; 191 192 /* 193 * Force CPSR to something logical... 194 */ 195 regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); 196 197 return 0; 198 } 199 200 #endif /* __KERNEL__ */ 201 202 #endif /* __ASSEMBLY__ */ 203 204 #endif /* CONFIG_ARM64 */ 205 206 #endif 207