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Searched defs:ArchCPU (Results 1 – 20 of 20) sorted by relevance

/qemu/target/arm/
A Dcpu.h837 struct ArchCPU { struct
894 Object *idau;
909 bool has_el2;
911 bool has_el3;
913 bool has_pmu;
915 bool has_vfp;
921 bool has_dsp;
924 bool has_mpu;
926 bool kvm_mte;
1036 } isar;
[all …]
/qemu/target/hexagon/
A Dcpu.h123 struct ArchCPU { struct
124 CPUState parent_obj;
126 CPUHexagonState env;
128 bool lldb_compat;
129 target_ulong lldb_stack_adjust;
130 bool short_circuit;
156 typedef HexagonCPU ArchCPU; typedef
/qemu/target/i386/
A Dcpu.h2069 struct ArchCPU { struct
2072 CPUX86State env;
2102 bool expose_kvm;
2103 bool expose_tcg;
2104 bool migratable;
2118 struct {
2123 } mwait;
2133 bool enable_pmu;
2213 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2220 int32_t die_id;
[all …]
/qemu/target/avr/
A Dcpu.h142 struct ArchCPU { struct
143 CPUState parent_obj;
145 CPUAVRState env;
148 uint32_t init_sp;
/qemu/target/rx/
A Dcpu.h109 struct ArchCPU { struct
110 CPUState parent_obj;
112 CPURXState env;
/qemu/target/loongarch/
A Dcpu.h399 struct ArchCPU { struct
415 * LoongArchCPUClass: argument
/qemu/target/microblaze/
A Dcpu.h342 struct ArchCPU { struct
343 CPUState parent_obj;
345 CPUMBState env;
347 bool ns_axi_dp;
348 bool ns_axi_ip;
349 bool ns_axi_dc;
350 bool ns_axi_ic;
352 MicroBlazeCPUConfig cfg;
/qemu/target/riscv/
A Dcpu.h497 struct ArchCPU { struct
498 CPUState parent_obj;
500 CPURISCVState env;
502 GDBFeature dyn_csr_feature;
503 GDBFeature dyn_vreg_feature;
506 RISCVCPUConfig cfg;
508 QEMUTimer *pmu_timer;
510 uint32_t pmu_avail_ctrs;
512 GHashTable *pmu_event_ctr_map;
513 const GPtrArray *decoders;
/qemu/target/tricore/
A Dcpu.h65 struct ArchCPU { struct
66 CPUState parent_obj;
68 CPUTriCoreState env;
/qemu/target/hppa/
A Dcpu.h274 struct ArchCPU { struct
275 CPUState parent_obj;
277 CPUHPPAState env;
278 QEMUTimer *alarm_timer;
/qemu/target/alpha/
A Dcpu.h258 struct ArchCPU { struct
259 CPUState parent_obj;
261 CPUAlphaState env;
264 QEMUTimer *alarm_timer;
/qemu/target/openrisc/
A Dcpu.h294 struct ArchCPU { struct
295 CPUState parent_obj;
297 CPUOpenRISCState env;
/qemu/target/sh4/
A Dcpu.h216 struct ArchCPU { struct
217 CPUState parent_obj;
219 CPUSH4State env;
/qemu/target/s390x/
A Dcpu.h170 struct ArchCPU { struct
171 CPUState parent_obj;
173 CPUS390XState env;
174 S390CPUModel *model;
176 void *irqstate;
177 uint32_t irqstate_saved_size;
/qemu/include/qemu/
A Dtypedefs.h29 typedef struct ArchCPU ArchCPU; typedef
/qemu/target/m68k/
A Dcpu.h166 struct ArchCPU { struct
167 CPUState parent_obj;
169 CPUM68KState env;
/qemu/target/xtensa/
A Dcpu.h558 struct ArchCPU { struct
559 CPUState parent_obj;
561 CPUXtensaState env;
562 Clock *clock;
/qemu/target/mips/
A Dcpu.h1204 struct ArchCPU { struct
1205 CPUState parent_obj;
1207 CPUMIPSState env;
1209 Clock *clock;
1210 Clock *count_div; /* Divider for CP0_Count clock */
1213 bool is_big_endian;
/qemu/target/ppc/
A Dcpu.h1448 struct ArchCPU { struct
1449 CPUState parent_obj;
1451 CPUPPCState env;
1453 int vcpu_id;
1454 uint32_t compat_pvr;
1455 PPCVirtualHypervisor *vhyp;
1456 PPCVirtualHypervisorClass *vhyp_class;
1457 void *machine_data;
1458 int32_t node_id; /* NUMA node this CPU belongs to */
1459 PPCHash64Options *hash64_opts;
[all …]
/qemu/target/sparc/
A Dcpu.h559 struct ArchCPU { struct
560 CPUState parent_obj;
562 CPUSPARCState env;

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