1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <linux/stringify.h> 11 12 /* 13 * T104x RDB board configuration file 14 */ 15 #include <asm/config_mpc85xx.h> 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define RESET_VECTOR_OFFSET 0x27FFC 19 #define BOOT_PAGE_OFFSET 0x27000 20 21 #ifdef CONFIG_MTD_RAW_NAND 22 #ifdef CONFIG_NXP_ESBC 23 #define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10)) 24 #else 25 #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) 26 #endif 27 #define CFG_SYS_NAND_U_BOOT_DST 0x30000000 28 #define CFG_SYS_NAND_U_BOOT_START 0x30000000 29 #endif 30 31 #ifdef CONFIG_SPIFLASH 32 #define CFG_RESET_VECTOR_ADDRESS 0x30000FFC 33 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 34 #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 35 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 36 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 37 #endif 38 39 #ifdef CONFIG_SDCARD 40 #define CFG_RESET_VECTOR_ADDRESS 0x30000FFC 41 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) 42 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) 43 #define CFG_SYS_MMC_U_BOOT_START (0x30000000) 44 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) 45 #endif 46 47 #endif 48 49 /* High Level Configuration Options */ 50 51 #ifndef CFG_RESET_VECTOR_ADDRESS 52 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E 61 62 /* 63 * Config the L3 Cache as L3 SRAM 64 */ 65 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 66 /* 67 * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence 68 * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address 69 * (CFG_SYS_INIT_L3_VADDR) will be different. 70 */ 71 #define CFG_SYS_INIT_L3_VADDR 0xFFFC0000 72 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 73 74 #define CFG_SYS_DCSRBAR 0xf0000000 75 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull 76 77 /* 78 * DDR Setup 79 */ 80 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 81 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 82 83 #define SPD_EEPROM_ADDRESS 0x51 84 85 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 86 87 /* 88 * IFC Definitions 89 */ 90 #define CFG_SYS_FLASH_BASE 0xe8000000 91 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) 92 93 #define CFG_SYS_NOR_CSPR_EXT (0xf) 94 #define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ 95 CSPR_PORT_SIZE_16 | \ 96 CSPR_MSEL_NOR | \ 97 CSPR_V) 98 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 99 100 /* 101 * TDM Definition 102 */ 103 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 104 105 /* NOR Flash Timing Params */ 106 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 107 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 108 FTIM0_NOR_TEADC(0x5) | \ 109 FTIM0_NOR_TEAHC(0x5)) 110 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 111 FTIM1_NOR_TRAD_NOR(0x1A) |\ 112 FTIM1_NOR_TSEQRAD_NOR(0x13)) 113 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 114 FTIM2_NOR_TCH(0x4) | \ 115 FTIM2_NOR_TWPH(0x0E) | \ 116 FTIM2_NOR_TWP(0x1c)) 117 #define CFG_SYS_NOR_FTIM3 0x0 118 119 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} 120 121 /* CPLD on IFC */ 122 #define CPLD_LBMAP_MASK 0x3F 123 #define CPLD_BANK_SEL_MASK 0x07 124 #define CPLD_BANK_OVERRIDE 0x40 125 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 126 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 127 #define CPLD_LBMAP_RESET 0xFF 128 #define CPLD_LBMAP_SHIFT 0x03 129 130 #if defined(CONFIG_TARGET_T1042D4RDB) 131 #define CPLD_DIU_SEL_DFP 0xc0 132 #endif 133 134 #define CFG_SYS_CPLD_BASE 0xffdf0000 135 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) 136 #define CFG_SYS_CSPR2_EXT (0xf) 137 #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ 138 | CSPR_PORT_SIZE_8 \ 139 | CSPR_MSEL_GPCM \ 140 | CSPR_V) 141 #define CFG_SYS_AMASK2 IFC_AMASK(64*1024) 142 #define CFG_SYS_CSOR2 0x0 143 /* CPLD Timing parameters for IFC CS2 */ 144 #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 145 FTIM0_GPCM_TEADC(0x0e) | \ 146 FTIM0_GPCM_TEAHC(0x0e)) 147 #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 148 FTIM1_GPCM_TRAD(0x1f)) 149 #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 150 FTIM2_GPCM_TCH(0x8) | \ 151 FTIM2_GPCM_TWP(0x1f)) 152 #define CFG_SYS_CS2_FTIM3 0x0 153 154 /* NAND Flash on IFC */ 155 #define CFG_SYS_NAND_BASE 0xff800000 156 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) 157 158 #define CFG_SYS_NAND_CSPR_EXT (0xf) 159 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 160 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 161 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 162 | CSPR_V) 163 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 164 165 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 166 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 167 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 168 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 169 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 170 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 171 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 172 173 /* ONFI NAND Flash mode0 Timing Params */ 174 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 175 FTIM0_NAND_TWP(0x18) | \ 176 FTIM0_NAND_TWCHT(0x07) | \ 177 FTIM0_NAND_TWH(0x0a)) 178 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 179 FTIM1_NAND_TWBE(0x39) | \ 180 FTIM1_NAND_TRR(0x0e) | \ 181 FTIM1_NAND_TRP(0x18)) 182 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 183 FTIM2_NAND_TREH(0x0a) | \ 184 FTIM2_NAND_TWHRE(0x1e)) 185 #define CFG_SYS_NAND_FTIM3 0x0 186 187 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 188 189 #if defined(CONFIG_MTD_RAW_NAND) 190 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 191 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 192 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 193 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 194 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 195 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 196 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 197 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 198 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT 199 #define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR 200 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 201 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 202 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 203 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 204 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 205 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 206 #else 207 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT 208 #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR 209 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 210 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 211 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 212 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 213 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 214 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 215 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 216 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 217 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 218 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 219 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 220 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 221 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 222 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 223 #endif 224 225 /* define to use L1 as initial stack */ 226 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 227 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 228 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 229 /* The assembler doesn't like typecast */ 230 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 231 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 232 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 233 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 234 235 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 236 237 /* Serial Port - controlled on board with jumper J8 238 * open - index 2 239 * shorted - index 1 240 */ 241 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) 242 243 #define CFG_SYS_BAUDRATE_TABLE \ 244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 245 246 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) 247 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) 248 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) 249 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) 250 251 /* I2C bus multiplexer */ 252 #define I2C_MUX_PCA_ADDR 0x70 253 #define I2C_MUX_CH_DEFAULT 0x8 254 255 #if defined(CONFIG_TARGET_T1042D4RDB) 256 /* 257 * RTC configuration 258 */ 259 #define CFG_SYS_I2C_RTC_ADDR 0x68 260 261 #endif 262 263 /* 264 * eSPI - Enhanced SPI 265 */ 266 267 /* 268 * General PCI 269 * Memory space is mapped 1-1, but I/O space must start from 0. 270 */ 271 272 #ifdef CONFIG_PCI 273 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 274 #ifdef CONFIG_PCIE1 275 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 276 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 277 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 278 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull 279 #endif 280 281 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 282 #ifdef CONFIG_PCIE2 283 #define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 284 #define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 285 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 286 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull 287 #endif 288 289 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 290 #ifdef CONFIG_PCIE3 291 #define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 292 #define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 293 #endif 294 295 /* controller 4, Base address 203000 */ 296 #ifdef CONFIG_PCIE4 297 #define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000 298 #define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 299 #endif 300 #endif /* CONFIG_PCI */ 301 302 /* 303 * USB 304 */ 305 306 #ifdef CONFIG_MMC 307 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 308 #endif 309 310 /* Qman/Bman */ 311 #ifndef CONFIG_NOBQFMAN 312 #define CFG_SYS_BMAN_NUM_PORTALS 10 313 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 314 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull 315 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 316 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 317 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 318 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 319 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 320 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 321 CFG_SYS_BMAN_CENA_SIZE) 322 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 323 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 324 #define CFG_SYS_QMAN_NUM_PORTALS 10 325 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 326 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull 327 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 328 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 329 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 330 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 331 CFG_SYS_QMAN_CENA_SIZE) 332 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 333 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 334 #endif /* CONFIG_NOBQFMAN */ 335 336 #ifdef CONFIG_FMAN_ENET 337 #if defined(CONFIG_TARGET_T1042D4RDB) 338 #define CFG_SYS_SGMII1_PHY_ADDR 0x02 339 #define CFG_SYS_SGMII2_PHY_ADDR 0x03 340 #define CFG_SYS_SGMII3_PHY_ADDR 0x01 341 #endif 342 343 #define CFG_SYS_RGMII1_PHY_ADDR 0x01 344 #define CFG_SYS_RGMII2_PHY_ADDR 0x02 345 #endif 346 347 /* 348 * Miscellaneous configurable options 349 */ 350 351 /* 352 * For booting Linux, the board info and command line data 353 * have to be in the first 64 MB of memory, since this is 354 * the maximum mapped by the Linux kernel during initialization. 355 */ 356 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 357 358 /* 359 * Dynamic MTD Partition support with mtdparts 360 */ 361 362 /* 363 * Environment Configuration 364 */ 365 366 #define __USB_PHY_TYPE utmi 367 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 368 369 #if defined(CONFIG_TARGET_T1042D4RDB) 370 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 371 #endif 372 373 #define CFG_EXTRA_ENV_SETTINGS \ 374 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 375 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 376 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 377 "netdev=eth0\0" \ 378 "uboot=" CONFIG_UBOOTPATH "\0" \ 379 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ 380 "tftpflash=tftpboot $loadaddr $uboot && " \ 381 "protect off $ubootaddr +$filesize && " \ 382 "erase $ubootaddr +$filesize && " \ 383 "cp.b $loadaddr $ubootaddr $filesize && " \ 384 "protect on $ubootaddr +$filesize && " \ 385 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 386 "consoledev=ttyS0\0" \ 387 "ramdiskaddr=2000000\0" \ 388 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 389 "fdtaddr=1e00000\0" \ 390 "fdtfile=" __stringify(FDTFILE) "\0" \ 391 "bdev=sda3\0" 392 393 #include <asm/fsl_secure_boot.h> 394 395 #endif /* __CONFIG_H */ 396