1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config PPC_SPINTABLE_COMPATIBLE 5 depends on MP 6 def_bool y 7 help 8 To comply with ePAPR 1.1, the spin table has been moved to 9 cache-enabled memory. Old OS may not work with this change. A patch 10 is waiting to be accepted for Linux kernel. Other OS needs similar 11 fix to spin table. For OSes with old spin table code, we can enable 12 this temporary fix by setting environmental variable 13 "spin_table_compat". For new OSes, set "spin_table_compat=no". After 14 Linux is fixed, we can remove this macro and related code. For now, 15 it is enabled by default. 16 17config SYS_CPU 18 default "mpc85xx" 19 20config CMD_ERRATA 21 bool "Enable the 'errata' command" 22 depends on MPC85xx 23 default y 24 help 25 This enables the 'errata' command which displays a list of errata 26 work-arounds which are enabled for the current board. 27 28config FSL_PREPBL_ESDHC_BOOT_SECTOR 29 bool "Generate QorIQ pre-PBL eSDHC boot sector" 30 depends on MPC85xx 31 depends on SDCARD 32 help 33 With this option final image would have prepended QorIQ pre-PBL eSDHC 34 boot sector suitable for SD card images. This boot sector instruct 35 BootROM to configure L2 SRAM and eSDHC then load image from SD card 36 into L2 SRAM and finally jump to image entry point. 37 38 This is alternative to Freescale boot_format tool, but works only for 39 SD card images and only for L2 SRAM booting. U-Boot images generated 40 with this option should not passed to boot_format tool. 41 42 For other configuration like booting from eSPI or configuring SDRAM 43 please use Freescale boot_format tool without this option. See file 44 doc/README.mpc85xx-sd-spi-boot 45 46config FSL_PREPBL_ESDHC_BOOT_SECTOR_START 47 int "QorIQ pre-PBL eSDHC boot sector start offset" 48 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR 49 range 0 23 50 default 0 51 help 52 QorIQ pre-PBL eSDHC boot sector may be located on one of the first 53 24 SD card sectors. Select SD card sector on which final U-Boot 54 image (with this boot sector) would be installed. 55 56 By default first SD card sector (0) is used. But this may be changed 57 to allow installing U-Boot image on some partition (with fixed start 58 sector). 59 60 Please note that any sector on SD card prior this boot sector must 61 not contain ASCII "BOOT" bytes at sector offset 0x40. 62 63config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA 64 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector" 65 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR 66 default 1 67 range 1 8388607 68 help 69 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot 70 sector on which would be stored raw U-Boot image. 71 72 By default is it second sector (1) which is the first available free 73 sector (on the first sector is stored boot sector). It can be any 74 sector number which offset in bytes can be expressed by 32-bit number. 75 76 In case this final U-Boot image (with this boot sector) is put on 77 the FAT32 partition into reserved boot area, this data sector needs 78 to be at least 2 (third sector) because FAT32 use second sector for 79 its data. 80 81choice 82 prompt "Target select" 83 optional 84 85config TARGET_SOCRATES 86 bool "Support socrates" 87 select ARCH_MPC8544 88 select BINMAN 89 90config TARGET_P3041DS 91 bool "Support P3041DS" 92 select PHYS_64BIT 93 select ARCH_P3041 94 select BOARD_LATE_INIT if CHAIN_OF_TRUST 95 select FSL_NGPIXIS 96 imply CMD_SATA 97 imply PANIC_HANG 98 99config TARGET_P4080DS 100 bool "Support P4080DS" 101 select PHYS_64BIT 102 select ARCH_P4080 103 select BOARD_LATE_INIT if CHAIN_OF_TRUST 104 select FSL_NGPIXIS 105 imply CMD_SATA 106 imply PANIC_HANG 107 108config TARGET_P5040DS 109 bool "Support P5040DS" 110 select PHYS_64BIT 111 select ARCH_P5040 112 select BOARD_LATE_INIT if CHAIN_OF_TRUST 113 select FSL_NGPIXIS 114 select SYS_FSL_RAID_ENGINE 115 imply CMD_SATA 116 imply PANIC_HANG 117 118config TARGET_MPC8548CDS 119 bool "Support MPC8548CDS" 120 select ARCH_MPC8548 121 select FSL_VIA 122 select SYS_CACHE_SHIFT_5 123 124config TARGET_P1010RDB_PA 125 bool "Support P1010RDB_PA" 126 select ARCH_P1010 127 select BOARD_LATE_INIT if CHAIN_OF_TRUST 128 select SUPPORT_SPL 129 select SUPPORT_TPL 130 select SYS_L2_SIZE_256KB 131 imply CMD_EEPROM 132 imply CMD_SATA 133 imply PANIC_HANG 134 135config TARGET_P1010RDB_PB 136 bool "Support P1010RDB_PB" 137 select ARCH_P1010 138 select BOARD_LATE_INIT if CHAIN_OF_TRUST 139 select SUPPORT_SPL 140 select SUPPORT_TPL 141 select SYS_L2_SIZE_256KB 142 imply CMD_EEPROM 143 imply CMD_SATA 144 imply PANIC_HANG 145 146config TARGET_P1020RDB_PC 147 bool "Support P1020RDB-PC" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 select SYS_L2_SIZE_256KB 152 imply CMD_EEPROM 153 imply CMD_SATA 154 imply PANIC_HANG 155 156config TARGET_P1020RDB_PD 157 bool "Support P1020RDB-PD" 158 select SUPPORT_SPL 159 select SUPPORT_TPL 160 select ARCH_P1020 161 select SYS_L2_SIZE_256KB 162 imply CMD_EEPROM 163 imply CMD_SATA 164 imply PANIC_HANG 165 166config TARGET_P2020RDB 167 bool "Support P2020RDB-PC" 168 select SUPPORT_SPL 169 select SUPPORT_TPL 170 select ARCH_P2020 171 select SYS_L2_SIZE_512KB 172 imply CMD_EEPROM 173 imply CMD_SATA 174 imply SATA_SIL 175 176config TARGET_P2041RDB 177 bool "Support P2041RDB" 178 select ARCH_P2041 179 select BOARD_LATE_INIT if CHAIN_OF_TRUST 180 select FSL_CORENET 181 select PHYS_64BIT 182 select SYS_L3_SIZE_1024KB 183 imply CMD_SATA 184 imply FSL_SATA 185 186config TARGET_QEMU_PPCE500 187 bool "Support qemu-ppce500" 188 select ARCH_QEMU_E500 189 select PHYS_64BIT 190 select SYS_RAMBOOT 191 imply OF_HAS_PRIOR_STAGE 192 193config TARGET_T1024RDB 194 bool "Support T1024RDB" 195 select ARCH_T1024 196 select BOARD_LATE_INIT if CHAIN_OF_TRUST 197 select SUPPORT_SPL 198 select PHYS_64BIT 199 select FSL_DDR_INTERACTIVE 200 select SYS_L3_SIZE_256KB 201 imply CMD_EEPROM 202 imply PANIC_HANG 203 204config TARGET_T1042D4RDB 205 bool "Support T1042D4RDB" 206 select ARCH_T1042 207 select BOARD_LATE_INIT if CHAIN_OF_TRUST 208 select SUPPORT_SPL 209 select PHYS_64BIT 210 select SYS_L3_SIZE_256KB 211 imply PANIC_HANG 212 213config TARGET_T2080QDS 214 bool "Support T2080QDS" 215 select ARCH_T2080 216 select BOARD_LATE_INIT if CHAIN_OF_TRUST 217 select SUPPORT_SPL 218 select PHYS_64BIT 219 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 220 select FSL_DDR_INTERACTIVE 221 select SYS_L3_SIZE_512KB 222 imply CMD_SATA 223 224config TARGET_T2080RDB 225 bool "Support T2080RDB" 226 select ARCH_T2080 227 select BOARD_LATE_INIT if CHAIN_OF_TRUST 228 select SUPPORT_SPL 229 select PHYS_64BIT 230 select SYS_L3_SIZE_512KB 231 imply CMD_SATA 232 imply PANIC_HANG 233 234config TARGET_T4240RDB 235 bool "Support T4240RDB" 236 select ARCH_T4240 237 select SUPPORT_SPL 238 select PHYS_64BIT 239 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 240 select SYS_L3_SIZE_512KB 241 imply CMD_SATA 242 imply PANIC_HANG 243 244config TARGET_KMP204X 245 bool "Support kmp204x" 246 select VENDOR_KM 247 248config TARGET_KMCENT2 249 bool "Support kmcent2" 250 select VENDOR_KM 251 select EVENT 252 select FSL_CORENET 253 select SYS_DPAA_FMAN 254 select SYS_DPAA_PME 255 select SYS_L3_SIZE_256KB 256 257endchoice 258 259config ARCH_B4420 260 bool 261 select E500MC 262 select E6500 263 select FSL_CORENET 264 select FSL_LAW 265 select HETROGENOUS_CLUSTERS 266 select SYS_FSL_DDR_VER_47 267 select SYS_FSL_ERRATUM_A004477 268 select SYS_FSL_ERRATUM_A005871 269 select SYS_FSL_ERRATUM_A006379 270 select SYS_FSL_ERRATUM_A006384 271 select SYS_FSL_ERRATUM_A006475 272 select SYS_FSL_ERRATUM_A006593 273 select SYS_FSL_ERRATUM_A007075 274 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 275 select SYS_FSL_ERRATUM_A007212 276 select SYS_FSL_ERRATUM_A009942 277 select SYS_FSL_HAS_DDR3 278 select SYS_FSL_HAS_SEC 279 select SYS_FSL_QORIQ_CHASSIS2 280 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 281 select SYS_FSL_SEC_BE 282 select SYS_FSL_SEC_COMPAT_4 283 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 284 select SYS_FSL_USB1_PHY_ENABLE 285 select SYS_PPC64 286 select FSL_IFC 287 imply CMD_EEPROM 288 imply CMD_NAND 289 imply CMD_REGINFO 290 291config ARCH_B4860 292 bool 293 select E500MC 294 select E6500 295 select FSL_CORENET 296 select FSL_LAW 297 select HETROGENOUS_CLUSTERS 298 select SYS_FSL_DDR_VER_47 299 select SYS_FSL_ERRATUM_A004477 300 select SYS_FSL_ERRATUM_A005871 301 select SYS_FSL_ERRATUM_A006379 302 select SYS_FSL_ERRATUM_A006384 303 select SYS_FSL_ERRATUM_A006475 304 select SYS_FSL_ERRATUM_A006593 305 select SYS_FSL_ERRATUM_A007075 306 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 307 select SYS_FSL_ERRATUM_A007212 308 select SYS_FSL_ERRATUM_A007907 309 select SYS_FSL_ERRATUM_A009942 310 select SYS_FSL_HAS_DDR3 311 select SYS_FSL_HAS_SEC 312 select SYS_FSL_QORIQ_CHASSIS2 313 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 314 select SYS_FSL_SEC_BE 315 select SYS_FSL_SEC_COMPAT_4 316 select SYS_FSL_SRDS_1 317 select SYS_FSL_SRDS_2 318 select SYS_FSL_SRIO_LIODN 319 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 320 select SYS_FSL_USB1_PHY_ENABLE 321 select SYS_PPC64 322 select FSL_IFC 323 imply CMD_EEPROM 324 imply CMD_NAND 325 imply CMD_REGINFO 326 327config ARCH_BSC9131 328 bool 329 select FSL_LAW 330 select SYS_FSL_DDR_VER_44 331 select SYS_FSL_ERRATUM_A004477 332 select SYS_FSL_ERRATUM_A005125 333 select SYS_FSL_ERRATUM_ESDHC111 334 select SYS_FSL_HAS_DDR3 335 select SYS_FSL_HAS_SEC 336 select SYS_FSL_SEC_BE 337 select SYS_FSL_SEC_COMPAT_4 338 select FSL_IFC 339 imply CMD_EEPROM 340 imply CMD_NAND 341 imply CMD_REGINFO 342 343config ARCH_BSC9132 344 bool 345 select FSL_LAW 346 select SYS_FSL_DDR_VER_46 347 select SYS_FSL_ERRATUM_A004477 348 select SYS_FSL_ERRATUM_A005125 349 select SYS_FSL_ERRATUM_A005434 350 select SYS_FSL_ERRATUM_ESDHC111 351 select SYS_FSL_ERRATUM_I2C_A004447 352 select SYS_FSL_ERRATUM_IFC_A002769 353 select FSL_PCIE_RESET 354 select SYS_FSL_HAS_DDR3 355 select SYS_FSL_HAS_SEC 356 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 357 select SYS_FSL_SEC_BE 358 select SYS_FSL_SEC_COMPAT_4 359 select SYS_PPC_E500_USE_DEBUG_TLB 360 select FSL_IFC 361 imply CMD_EEPROM 362 imply CMD_MTDPARTS 363 imply CMD_NAND 364 imply CMD_PCI 365 imply CMD_REGINFO 366 367config ARCH_C29X 368 bool 369 select FSL_LAW 370 select SYS_FSL_DDR_VER_46 371 select SYS_FSL_ERRATUM_A005125 372 select SYS_FSL_ERRATUM_ESDHC111 373 select FSL_PCIE_RESET 374 select SYS_FSL_HAS_DDR3 375 select SYS_FSL_HAS_SEC 376 select SYS_FSL_SEC_BE 377 select SYS_FSL_SEC_COMPAT_6 378 select SYS_PPC_E500_USE_DEBUG_TLB 379 select FSL_IFC 380 imply CMD_NAND 381 imply CMD_PCI 382 imply CMD_REGINFO 383 384config ARCH_MPC8536 385 bool 386 select FSL_LAW 387 select SYS_FSL_ERRATUM_A004508 388 select SYS_FSL_ERRATUM_A005125 389 select FSL_PCIE_RESET 390 select SYS_FSL_HAS_DDR2 391 select SYS_FSL_HAS_DDR3 392 select SYS_FSL_HAS_SEC 393 select SYS_FSL_SEC_BE 394 select SYS_FSL_SEC_COMPAT_2 395 select SYS_PPC_E500_USE_DEBUG_TLB 396 select FSL_ELBC 397 imply CMD_NAND 398 imply CMD_SATA 399 imply CMD_REGINFO 400 401config ARCH_MPC8540 402 bool 403 select FSL_LAW 404 select SYS_FSL_HAS_DDR1 405 406config ARCH_MPC8544 407 bool 408 select BTB 409 select FSL_LAW 410 select SYS_CACHE_SHIFT_5 411 select SYS_FSL_ERRATUM_A005125 412 select FSL_PCIE_RESET 413 select SYS_FSL_HAS_DDR2 414 select SYS_FSL_HAS_SEC 415 select SYS_FSL_SEC_BE 416 select SYS_FSL_SEC_COMPAT_2 417 select SYS_PPC_E500_USE_DEBUG_TLB 418 select FSL_ELBC 419 420config ARCH_MPC8548 421 bool 422 select BTB 423 select FSL_LAW 424 select SYS_FSL_ERRATUM_A005125 425 select SYS_FSL_ERRATUM_NMG_DDR120 426 select SYS_FSL_ERRATUM_NMG_LBC103 427 select SYS_FSL_ERRATUM_NMG_ETSEC129 428 select SYS_FSL_ERRATUM_I2C_A004447 429 select FSL_PCIE_RESET 430 select SYS_FSL_HAS_DDR2 431 select SYS_FSL_HAS_DDR1 432 select SYS_FSL_HAS_SEC 433 select SYS_FSL_RMU 434 select SYS_FSL_SEC_BE 435 select SYS_FSL_SEC_COMPAT_2 436 select SYS_PPC_E500_USE_DEBUG_TLB 437 imply CMD_REGINFO 438 439config ARCH_MPC8560 440 bool 441 select FSL_LAW 442 select SYS_FSL_HAS_DDR1 443 444config ARCH_P1010 445 bool 446 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL 447 select BTB 448 select FSL_LAW 449 select SYS_CACHE_SHIFT_5 450 select SYS_HAS_SERDES 451 select SYS_FSL_ERRATUM_A004477 452 select SYS_FSL_ERRATUM_A004508 453 select SYS_FSL_ERRATUM_A005125 454 select SYS_FSL_ERRATUM_A005275 455 select SYS_FSL_ERRATUM_A006261 456 select SYS_FSL_ERRATUM_A007075 457 select SYS_FSL_ERRATUM_ESDHC111 458 select SYS_FSL_ERRATUM_I2C_A004447 459 select SYS_FSL_ERRATUM_IFC_A002769 460 select SYS_FSL_ERRATUM_P1010_A003549 461 select SYS_FSL_ERRATUM_SEC_A003571 462 select SYS_FSL_ERRATUM_IFC_A003399 463 select FSL_PCIE_RESET 464 select SYS_FSL_HAS_DDR3 465 select SYS_FSL_HAS_SEC 466 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 467 select SYS_FSL_SEC_BE 468 select SYS_FSL_SEC_COMPAT_4 469 select SYS_FSL_USB1_PHY_ENABLE 470 select SYS_PPC_E500_USE_DEBUG_TLB 471 select FSL_IFC 472 imply CMD_EEPROM 473 imply CMD_MTDPARTS 474 imply CMD_NAND 475 imply CMD_SATA 476 imply CMD_PCI 477 imply CMD_REGINFO 478 imply FSL_SATA 479 imply TIMESTAMP 480 481config ARCH_P1011 482 bool 483 select FSL_LAW 484 select SYS_FSL_ERRATUM_A004508 485 select SYS_FSL_ERRATUM_A005125 486 select SYS_FSL_ERRATUM_ELBC_A001 487 select SYS_FSL_ERRATUM_ESDHC111 488 select FSL_PCIE_DISABLE_ASPM 489 select SYS_FSL_HAS_DDR3 490 select SYS_FSL_HAS_SEC 491 select SYS_FSL_SEC_BE 492 select SYS_FSL_SEC_COMPAT_2 493 select SYS_PPC_E500_USE_DEBUG_TLB 494 select FSL_ELBC 495 496config ARCH_P1020 497 bool 498 select BTB 499 select FSL_LAW 500 select SYS_CACHE_SHIFT_5 501 select SYS_FSL_ERRATUM_A004508 502 select SYS_FSL_ERRATUM_A005125 503 select SYS_FSL_ERRATUM_ELBC_A001 504 select SYS_FSL_ERRATUM_ESDHC111 505 select FSL_PCIE_DISABLE_ASPM 506 select FSL_PCIE_RESET 507 select SYS_FSL_HAS_DDR3 508 select SYS_FSL_HAS_SEC 509 select SYS_FSL_SEC_BE 510 select SYS_FSL_SEC_COMPAT_2 511 select SYS_PPC_E500_USE_DEBUG_TLB 512 select FSL_ELBC 513 imply CMD_NAND 514 imply CMD_SATA 515 imply CMD_PCI 516 imply CMD_REGINFO 517 imply SATA_SIL 518 519config ARCH_P1021 520 bool 521 select FSL_LAW 522 select SYS_FSL_ERRATUM_A004508 523 select SYS_FSL_ERRATUM_A005125 524 select SYS_FSL_ERRATUM_ELBC_A001 525 select SYS_FSL_ERRATUM_ESDHC111 526 select FSL_PCIE_DISABLE_ASPM 527 select FSL_PCIE_RESET 528 select SYS_FSL_HAS_DDR3 529 select SYS_FSL_HAS_SEC 530 select SYS_FSL_SEC_BE 531 select SYS_FSL_SEC_COMPAT_2 532 select SYS_PPC_E500_USE_DEBUG_TLB 533 select FSL_ELBC 534 imply CMD_REGINFO 535 imply CMD_NAND 536 imply CMD_SATA 537 imply CMD_REGINFO 538 imply SATA_SIL 539 540config ARCH_P1023 541 bool 542 select FSL_LAW 543 select SYS_FSL_ERRATUM_A004508 544 select SYS_FSL_ERRATUM_A005125 545 select SYS_FSL_ERRATUM_I2C_A004447 546 select FSL_PCIE_RESET 547 select SYS_FSL_HAS_DDR3 548 select SYS_FSL_HAS_SEC 549 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 550 select SYS_FSL_SEC_BE 551 select SYS_FSL_SEC_COMPAT_4 552 select FSL_ELBC 553 554config ARCH_P1024 555 bool 556 select FSL_LAW 557 select SYS_FSL_ERRATUM_A004508 558 select SYS_FSL_ERRATUM_A005125 559 select SYS_FSL_ERRATUM_ELBC_A001 560 select SYS_FSL_ERRATUM_ESDHC111 561 select FSL_PCIE_DISABLE_ASPM 562 select FSL_PCIE_RESET 563 select SYS_FSL_HAS_DDR3 564 select SYS_FSL_HAS_SEC 565 select SYS_FSL_RMU 566 select SYS_FSL_SEC_BE 567 select SYS_FSL_SEC_COMPAT_2 568 select SYS_PPC_E500_USE_DEBUG_TLB 569 select FSL_ELBC 570 imply CMD_EEPROM 571 imply CMD_NAND 572 imply CMD_SATA 573 imply CMD_PCI 574 imply CMD_REGINFO 575 imply SATA_SIL 576 577config ARCH_P1025 578 bool 579 select FSL_LAW 580 select SYS_FSL_ERRATUM_A004508 581 select SYS_FSL_ERRATUM_A005125 582 select SYS_FSL_ERRATUM_ELBC_A001 583 select SYS_FSL_ERRATUM_ESDHC111 584 select FSL_PCIE_DISABLE_ASPM 585 select FSL_PCIE_RESET 586 select SYS_FSL_HAS_DDR3 587 select SYS_FSL_HAS_SEC 588 select SYS_FSL_SEC_BE 589 select SYS_FSL_SEC_COMPAT_2 590 select SYS_PPC_E500_USE_DEBUG_TLB 591 select FSL_ELBC 592 imply CMD_SATA 593 imply CMD_REGINFO 594 595config ARCH_P2020 596 bool 597 select BTB 598 select FSL_LAW 599 select SYS_CACHE_SHIFT_5 600 select SYS_FSL_ERRATUM_A004477 601 select SYS_FSL_ERRATUM_A004508 602 select SYS_FSL_ERRATUM_A005125 603 select SYS_FSL_ERRATUM_ESDHC111 604 select SYS_FSL_ERRATUM_ESDHC_A001 605 select FSL_PCIE_RESET 606 select SYS_FSL_HAS_DDR3 607 select SYS_FSL_HAS_SEC 608 select SYS_FSL_SEC_BE 609 select SYS_FSL_SEC_COMPAT_2 610 select SYS_PPC_E500_USE_DEBUG_TLB 611 select FSL_ELBC 612 imply CMD_EEPROM 613 imply CMD_NAND 614 imply CMD_REGINFO 615 imply TIMESTAMP 616 617config ARCH_P2041 618 bool 619 select BACKSIDE_L2_CACHE 620 select E500MC 621 select FSL_LAW 622 select SYS_CACHE_SHIFT_6 623 select SYS_DPAA_FMAN 624 select SYS_DPAA_PME 625 select SYS_DPAA_RMAN 626 select SYS_FSL_ERRATUM_A004510 627 select SYS_FSL_ERRATUM_A004849 628 select SYS_FSL_ERRATUM_A005275 629 select SYS_FSL_ERRATUM_A006261 630 select SYS_FSL_ERRATUM_CPU_A003999 631 select SYS_FSL_ERRATUM_DDR_A003 632 select SYS_FSL_ERRATUM_DDR_A003474 633 select SYS_FSL_ERRATUM_ESDHC111 634 select SYS_FSL_ERRATUM_I2C_A004447 635 select SYS_FSL_ERRATUM_NMG_CPU_A011 636 select SYS_FSL_ERRATUM_SRIO_A004034 637 select SYS_FSL_ERRATUM_USB14 638 select SYS_FSL_HAS_DDR3 639 select SYS_FSL_HAS_SEC 640 select SYS_FSL_QORIQ_CHASSIS1 641 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 642 select SYS_FSL_SEC_BE 643 select SYS_FSL_SEC_COMPAT_4 644 select SYS_FSL_USB1_PHY_ENABLE 645 select SYS_FSL_USB2_PHY_ENABLE 646 select FSL_ELBC 647 imply CMD_NAND 648 649config ARCH_P3041 650 bool 651 select BACKSIDE_L2_CACHE 652 select E500MC 653 select FSL_CORENET 654 select FSL_LAW 655 select SYS_CACHE_SHIFT_6 656 select SYS_FSL_DDR_VER_44 657 select SYS_FSL_ERRATUM_A004510 658 select SYS_FSL_ERRATUM_A004849 659 select SYS_FSL_ERRATUM_A005275 660 select SYS_FSL_ERRATUM_A005812 661 select SYS_FSL_ERRATUM_A006261 662 select SYS_FSL_ERRATUM_CPU_A003999 663 select SYS_FSL_ERRATUM_DDR_A003 664 select SYS_FSL_ERRATUM_DDR_A003474 665 select SYS_FSL_ERRATUM_ESDHC111 666 select SYS_FSL_ERRATUM_I2C_A004447 667 select SYS_FSL_ERRATUM_NMG_CPU_A011 668 select SYS_FSL_ERRATUM_SRIO_A004034 669 select SYS_FSL_ERRATUM_USB14 670 select SYS_FSL_HAS_DDR3 671 select SYS_FSL_HAS_SEC 672 select SYS_FSL_QORIQ_CHASSIS1 673 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 674 select SYS_FSL_SEC_BE 675 select SYS_FSL_SEC_COMPAT_4 676 select SYS_FSL_USB1_PHY_ENABLE 677 select SYS_FSL_USB2_PHY_ENABLE 678 select FSL_ELBC 679 imply CMD_NAND 680 imply CMD_SATA 681 imply CMD_REGINFO 682 imply FSL_SATA 683 684config ARCH_P4080 685 bool 686 select BACKSIDE_L2_CACHE 687 select E500MC 688 select FSL_CORENET 689 select FSL_LAW 690 select SYS_CACHE_SHIFT_6 691 select SYS_FSL_DDR_VER_44 692 select SYS_FSL_ERRATUM_A004510 693 select SYS_FSL_ERRATUM_A004580 694 select SYS_FSL_ERRATUM_A004849 695 select SYS_FSL_ERRATUM_A005812 696 select SYS_FSL_ERRATUM_A007075 697 select SYS_FSL_ERRATUM_CPC_A002 698 select SYS_FSL_ERRATUM_CPC_A003 699 select SYS_FSL_ERRATUM_CPU_A003999 700 select SYS_FSL_ERRATUM_DDR_A003 701 select SYS_FSL_ERRATUM_DDR_A003474 702 select SYS_FSL_ERRATUM_ELBC_A001 703 select SYS_FSL_ERRATUM_ESDHC111 704 select SYS_FSL_ERRATUM_ESDHC13 705 select SYS_FSL_ERRATUM_ESDHC135 706 select SYS_FSL_ERRATUM_I2C_A004447 707 select SYS_FSL_ERRATUM_NMG_CPU_A011 708 select SYS_FSL_ERRATUM_SRIO_A004034 709 select SYS_FSL_PCIE_COMPAT_P4080_PCIE 710 select SYS_P4080_ERRATUM_CPU22 711 select SYS_P4080_ERRATUM_PCIE_A003 712 select SYS_P4080_ERRATUM_SERDES8 713 select SYS_P4080_ERRATUM_SERDES9 714 select SYS_P4080_ERRATUM_SERDES_A001 715 select SYS_P4080_ERRATUM_SERDES_A005 716 select SYS_FSL_HAS_DDR3 717 select SYS_FSL_HAS_SEC 718 select SYS_FSL_QORIQ_CHASSIS1 719 select SYS_FSL_RMU 720 select SYS_FSL_SEC_BE 721 select SYS_FSL_SEC_COMPAT_4 722 select FSL_ELBC 723 imply CMD_SATA 724 imply CMD_REGINFO 725 imply SATA_SIL 726 727config ARCH_P5040 728 bool 729 select BACKSIDE_L2_CACHE 730 select E500MC 731 select FSL_CORENET 732 select FSL_LAW 733 select SYS_CACHE_SHIFT_6 734 select SYS_FSL_DDR_VER_44 735 select SYS_FSL_ERRATUM_A004510 736 select SYS_FSL_ERRATUM_A004699 737 select SYS_FSL_ERRATUM_A005275 738 select SYS_FSL_ERRATUM_A005812 739 select SYS_FSL_ERRATUM_A006261 740 select SYS_FSL_ERRATUM_DDR_A003 741 select SYS_FSL_ERRATUM_DDR_A003474 742 select SYS_FSL_ERRATUM_ESDHC111 743 select SYS_FSL_ERRATUM_USB14 744 select SYS_FSL_HAS_DDR3 745 select SYS_FSL_HAS_SEC 746 select SYS_FSL_QORIQ_CHASSIS1 747 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 748 select SYS_FSL_SEC_BE 749 select SYS_FSL_SEC_COMPAT_4 750 select SYS_FSL_USB1_PHY_ENABLE 751 select SYS_FSL_USB2_PHY_ENABLE 752 select SYS_PPC64 753 select FSL_ELBC 754 imply CMD_SATA 755 imply CMD_REGINFO 756 imply FSL_SATA 757 758config ARCH_QEMU_E500 759 bool 760 select SYS_CACHE_SHIFT_5 761 762config ARCH_T1024 763 bool 764 select BACKSIDE_L2_CACHE 765 select E500MC 766 select E5500 767 select FSL_CORENET 768 select FSL_LAW 769 select SYS_CACHE_SHIFT_6 770 select SYS_DPAA_FMAN 771 select SYS_FSL_DDR_VER_50 772 select SYS_FSL_ERRATUM_A008378 773 select SYS_FSL_ERRATUM_A008109 774 select SYS_FSL_ERRATUM_A009663 775 select SYS_FSL_ERRATUM_A009942 776 select SYS_FSL_ERRATUM_ESDHC111 777 select SYS_FSL_HAS_DDR3 778 select SYS_FSL_HAS_DDR4 779 select SYS_FSL_HAS_SEC 780 select SYS_FSL_QORIQ_CHASSIS2 781 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 782 select SYS_FSL_SEC_BE 783 select SYS_FSL_SEC_COMPAT_5 784 select SYS_FSL_SINGLE_SOURCE_CLK 785 select SYS_FSL_SRDS_1 786 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 787 select SYS_FSL_USB_DUAL_PHY_ENABLE 788 select FSL_IFC 789 imply CMD_EEPROM 790 imply CMD_NAND 791 imply CMD_MTDPARTS 792 imply CMD_REGINFO 793 794config ARCH_T1040 795 bool 796 select BACKSIDE_L2_CACHE 797 select E500MC 798 select E5500 799 select FSL_CORENET 800 select FSL_LAW 801 select SYS_CACHE_SHIFT_6 802 select SYS_DPAA_FMAN 803 select SYS_DPAA_PME 804 select SYS_FSL_DDR_VER_50 805 select SYS_FSL_ERRATUM_A008044 806 select SYS_FSL_ERRATUM_A008378 807 select SYS_FSL_ERRATUM_A008109 808 select SYS_FSL_ERRATUM_A009663 809 select SYS_FSL_ERRATUM_A009942 810 select SYS_FSL_ERRATUM_ESDHC111 811 select SYS_FSL_HAS_DDR3 812 select SYS_FSL_HAS_DDR4 813 select SYS_FSL_HAS_SEC 814 select SYS_FSL_QORIQ_CHASSIS2 815 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 816 select SYS_FSL_SEC_BE 817 select SYS_FSL_SEC_COMPAT_5 818 select SYS_FSL_SINGLE_SOURCE_CLK 819 select SYS_FSL_SRDS_1 820 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 821 select SYS_FSL_USB_DUAL_PHY_ENABLE 822 select FSL_IFC 823 imply CMD_MTDPARTS 824 imply CMD_NAND 825 imply CMD_REGINFO 826 827config ARCH_T1042 828 bool 829 select BACKSIDE_L2_CACHE 830 select E500MC 831 select E5500 832 select FSL_CORENET 833 select FSL_LAW 834 select SYS_CACHE_SHIFT_6 835 select SYS_DPAA_FMAN 836 select SYS_DPAA_PME 837 select SYS_FSL_DDR_VER_50 838 select SYS_FSL_ERRATUM_A008044 839 select SYS_FSL_ERRATUM_A008378 840 select SYS_FSL_ERRATUM_A008109 841 select SYS_FSL_ERRATUM_A009663 842 select SYS_FSL_ERRATUM_A009942 843 select SYS_FSL_ERRATUM_ESDHC111 844 select SYS_FSL_HAS_DDR3 845 select SYS_FSL_HAS_DDR4 846 select SYS_FSL_HAS_SEC 847 select SYS_FSL_QORIQ_CHASSIS2 848 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 849 select SYS_FSL_SEC_BE 850 select SYS_FSL_SEC_COMPAT_5 851 select SYS_FSL_SINGLE_SOURCE_CLK 852 select SYS_FSL_SRDS_1 853 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 854 select SYS_FSL_USB_DUAL_PHY_ENABLE 855 select FSL_IFC 856 imply CMD_MTDPARTS 857 imply CMD_NAND 858 imply CMD_REGINFO 859 860config ARCH_T2080 861 bool 862 select E500MC 863 select E6500 864 select FSL_CORENET 865 select FSL_LAW 866 select SYS_CACHE_SHIFT_6 867 select SYS_DPAA_DCE if !NOBQFMAN 868 select SYS_DPAA_FMAN if !NOBQFMAN 869 select SYS_DPAA_PME if !NOBQFMAN 870 select SYS_DPAA_RMAN if !NOBQFMAN 871 select SYS_FSL_DDR_VER_47 872 select SYS_FSL_ERRATUM_A006379 873 select SYS_FSL_ERRATUM_A006593 874 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 875 select SYS_FSL_ERRATUM_A007212 876 select SYS_FSL_ERRATUM_A007815 877 select SYS_FSL_ERRATUM_A007907 878 select SYS_FSL_ERRATUM_A008109 879 select SYS_FSL_ERRATUM_A009942 880 select SYS_FSL_ERRATUM_ESDHC111 881 select FSL_PCIE_RESET 882 select SYS_FSL_HAS_DDR3 883 select SYS_FSL_HAS_SEC 884 select SYS_FSL_QORIQ_CHASSIS2 885 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 886 select SYS_FSL_SEC_BE 887 select SYS_FSL_SEC_COMPAT_4 888 select SYS_FSL_SRDS_1 889 select SYS_FSL_SRDS_2 890 select SYS_FSL_SRIO_LIODN 891 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 892 select SYS_FSL_USB_DUAL_PHY_ENABLE 893 select SYS_PMAN if !NOBQFMAN 894 select SYS_PPC64 895 select FSL_IFC 896 imply CMD_SATA 897 imply CMD_NAND 898 imply CMD_REGINFO 899 imply FSL_SATA 900 imply ID_EEPROM 901 902config ARCH_T4240 903 bool 904 select E500MC 905 select E6500 906 select FSL_CORENET 907 select FSL_LAW 908 select SYS_CACHE_SHIFT_6 909 select SYS_DPAA_DCE if !NOBQFMAN 910 select SYS_DPAA_FMAN if !NOBQFMAN 911 select SYS_DPAA_PME if !NOBQFMAN 912 select SYS_DPAA_RMAN if !NOBQFMAN 913 select SYS_FSL_DDR_VER_47 914 select SYS_FSL_ERRATUM_A004468 915 select SYS_FSL_ERRATUM_A005871 916 select SYS_FSL_ERRATUM_A006261 917 select SYS_FSL_ERRATUM_A006379 918 select SYS_FSL_ERRATUM_A006593 919 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 920 select SYS_FSL_ERRATUM_A007798 921 select SYS_FSL_ERRATUM_A007815 922 select SYS_FSL_ERRATUM_A007907 923 select SYS_FSL_ERRATUM_A008109 924 select SYS_FSL_ERRATUM_A009942 925 select SYS_FSL_HAS_DDR3 926 select SYS_FSL_HAS_SEC 927 select SYS_FSL_QORIQ_CHASSIS2 928 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 929 select SYS_FSL_SEC_BE 930 select SYS_FSL_SEC_COMPAT_4 931 select SYS_FSL_SRDS_1 932 select SYS_FSL_SRDS_2 933 select SYS_FSL_SRIO_LIODN 934 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 935 select SYS_FSL_USB_DUAL_PHY_ENABLE 936 select SYS_PMAN if !NOBQFMAN 937 select SYS_PPC64 938 select FSL_IFC 939 imply CMD_SATA 940 imply CMD_NAND 941 imply CMD_REGINFO 942 imply FSL_SATA 943 944config MPC85XX_HAVE_RESET_VECTOR 945 bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" 946 depends on MPC85xx 947 948config BTB 949 bool "toggle branch predition" 950 951config BOOKE 952 bool 953 default y 954 955config E500 956 bool 957 default y 958 help 959 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 960 961config E500MC 962 bool 963 select BTB 964 imply CMD_PCI 965 help 966 Enble PowerPC E500MC core 967 968config E5500 969 bool 970 971config E6500 972 bool 973 select BTB 974 help 975 Enable PowerPC E6500 core 976 977config NOBQFMAN 978 bool 979 980config FSL_LAW 981 bool 982 help 983 Use Freescale common code for Local Access Window 984 985config HETROGENOUS_CLUSTERS 986 bool 987 988config MAX_CPUS 989 int "Maximum number of CPUs permitted for MPC85xx" 990 default 12 if ARCH_T4240 991 default 8 if ARCH_P4080 992 default 4 if ARCH_B4860 || \ 993 ARCH_P2041 || \ 994 ARCH_P3041 || \ 995 ARCH_P5040 || \ 996 ARCH_T1040 || \ 997 ARCH_T1042 || \ 998 ARCH_T2080 999 default 2 if ARCH_B4420 || \ 1000 ARCH_BSC9132 || \ 1001 ARCH_P1020 || \ 1002 ARCH_P1021 || \ 1003 ARCH_P1023 || \ 1004 ARCH_P1024 || \ 1005 ARCH_P1025 || \ 1006 ARCH_P2020 || \ 1007 ARCH_T1024 1008 default 1 1009 help 1010 Set this number to the maximum number of possible CPUs in the SoC. 1011 SoCs may have multiple clusters with each cluster may have multiple 1012 ports. If some ports are reserved but higher ports are used for 1013 cores, count the reserved ports. This will allocate enough memory 1014 in spin table to properly handle all cores. 1015 1016config SYS_CCSRBAR_DEFAULT 1017 hex "Default CCSRBAR address" 1018 default 0xff700000 if ARCH_BSC9131 || \ 1019 ARCH_BSC9132 || \ 1020 ARCH_C29X || \ 1021 ARCH_MPC8536 || \ 1022 ARCH_MPC8540 || \ 1023 ARCH_MPC8544 || \ 1024 ARCH_MPC8548 || \ 1025 ARCH_MPC8560 || \ 1026 ARCH_P1010 || \ 1027 ARCH_P1011 || \ 1028 ARCH_P1020 || \ 1029 ARCH_P1021 || \ 1030 ARCH_P1024 || \ 1031 ARCH_P1025 || \ 1032 ARCH_P2020 1033 default 0xff600000 if ARCH_P1023 1034 default 0xfe000000 if ARCH_B4420 || \ 1035 ARCH_B4860 || \ 1036 ARCH_P2041 || \ 1037 ARCH_P3041 || \ 1038 ARCH_P4080 || \ 1039 ARCH_P5040 || \ 1040 ARCH_T1024 || \ 1041 ARCH_T1040 || \ 1042 ARCH_T1042 || \ 1043 ARCH_T2080 || \ 1044 ARCH_T4240 1045 default 0xe0000000 if ARCH_QEMU_E500 1046 help 1047 Default value of CCSRBAR comes from power-on-reset. It 1048 is fixed on each SoC. Some SoCs can have different value 1049 if changed by pre-boot regime. The value here must match 1050 the current value in SoC. If not sure, do not change. 1051 1052config SYS_DPAA_PME 1053 bool 1054 1055config SYS_DPAA_DCE 1056 bool 1057 1058config SYS_DPAA_RMAN 1059 bool 1060 1061config A003399_NOR_WORKAROUND 1062 bool 1063 help 1064 Enables a workaround for IFC erratum A003399. It is only required 1065 during NOR boot. 1066 1067config A008044_WORKAROUND 1068 bool 1069 help 1070 Enables a workaround for T1040/T1042 erratum A008044. It is only 1071 required during NAND boot and valid for Rev 1.0 SoC revision 1072 1073config SYS_FSL_ERRATUM_A004468 1074 bool 1075 1076config SYS_FSL_ERRATUM_A004477 1077 bool 1078 1079config SYS_FSL_ERRATUM_A004508 1080 bool 1081 1082config SYS_FSL_ERRATUM_A004580 1083 bool 1084 1085config SYS_FSL_ERRATUM_A004699 1086 bool 1087 1088config SYS_FSL_ERRATUM_A004849 1089 bool 1090 1091config SYS_FSL_ERRATUM_A004510 1092 bool 1093 1094config SYS_FSL_ERRATUM_A004510_SVR_REV 1095 hex 1096 depends on SYS_FSL_ERRATUM_A004510 1097 default 0x20 if ARCH_P4080 1098 default 0x10 1099 1100config SYS_FSL_ERRATUM_A004510_SVR_REV2 1101 hex 1102 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1103 default 0x11 1104 1105config SYS_FSL_ERRATUM_A005125 1106 bool 1107 1108config SYS_FSL_ERRATUM_A005434 1109 bool 1110 1111config SYS_FSL_ERRATUM_A005812 1112 bool 1113 1114config SYS_FSL_ERRATUM_A005871 1115 bool 1116 1117config SYS_FSL_ERRATUM_A005275 1118 bool 1119 1120config SYS_FSL_ERRATUM_A006261 1121 bool 1122 1123config SYS_FSL_ERRATUM_A006379 1124 bool 1125 1126config SYS_FSL_ERRATUM_A006384 1127 bool 1128 1129config SYS_FSL_ERRATUM_A006475 1130 bool 1131 1132config SYS_FSL_ERRATUM_A006593 1133 bool 1134 1135config SYS_FSL_ERRATUM_A007075 1136 bool 1137 1138config SYS_FSL_ERRATUM_A007186 1139 bool 1140 1141config SYS_FSL_ERRATUM_A007212 1142 bool 1143 1144config SYS_FSL_ERRATUM_A007815 1145 bool 1146 1147config SYS_FSL_ERRATUM_A007798 1148 bool 1149 1150config SYS_FSL_ERRATUM_A007907 1151 bool 1152 1153config SYS_FSL_ERRATUM_A008044 1154 bool 1155 select A008044_WORKAROUND if MTD_RAW_NAND 1156 1157config SYS_FSL_ERRATUM_CPC_A002 1158 bool 1159 1160config SYS_FSL_ERRATUM_CPC_A003 1161 bool 1162 1163config SYS_FSL_ERRATUM_CPU_A003999 1164 bool 1165 1166config SYS_FSL_ERRATUM_ELBC_A001 1167 bool 1168 1169config SYS_FSL_ERRATUM_I2C_A004447 1170 bool 1171 1172config SYS_FSL_A004447_SVR_REV 1173 hex 1174 depends on SYS_FSL_ERRATUM_I2C_A004447 1175 default 0x00 if ARCH_MPC8548 1176 default 0x10 if ARCH_P1010 1177 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1178 default 0x20 if ARCH_P3041 || ARCH_P4080 1179 1180config SYS_FSL_ERRATUM_IFC_A002769 1181 bool 1182 1183config SYS_FSL_ERRATUM_IFC_A003399 1184 bool 1185 1186config SYS_FSL_ERRATUM_NMG_CPU_A011 1187 bool 1188 1189config SYS_FSL_ERRATUM_NMG_ETSEC129 1190 bool 1191 1192config SYS_FSL_ERRATUM_NMG_LBC103 1193 bool 1194 1195config SYS_FSL_ERRATUM_P1010_A003549 1196 bool 1197 1198config SYS_FSL_ERRATUM_SATA_A001 1199 bool 1200 1201config SYS_FSL_ERRATUM_SEC_A003571 1202 bool 1203 1204config SYS_FSL_ERRATUM_SRIO_A004034 1205 bool 1206 1207config SYS_FSL_ERRATUM_USB14 1208 bool 1209 1210config SYS_P4080_ERRATUM_CPU22 1211 bool 1212 1213config SYS_P4080_ERRATUM_PCIE_A003 1214 bool 1215 1216config SYS_P4080_ERRATUM_SERDES8 1217 bool 1218 1219config SYS_P4080_ERRATUM_SERDES9 1220 bool 1221 1222config SYS_P4080_ERRATUM_SERDES_A001 1223 bool 1224 1225config SYS_P4080_ERRATUM_SERDES_A005 1226 bool 1227 1228config FSL_PCIE_DISABLE_ASPM 1229 bool 1230 1231config FSL_PCIE_RESET 1232 bool 1233 1234config SYS_PMAN 1235 bool 1236 1237config SYS_FSL_RAID_ENGINE 1238 bool 1239 1240config SYS_FSL_RMU 1241 bool 1242 1243config SYS_FSL_QORIQ_CHASSIS1 1244 bool 1245 1246config SYS_FSL_QORIQ_CHASSIS2 1247 bool 1248 1249config SYS_FSL_NUM_LAWS 1250 int "Number of local access windows" 1251 depends on FSL_LAW 1252 default 32 if ARCH_B4420 || \ 1253 ARCH_B4860 || \ 1254 ARCH_P2041 || \ 1255 ARCH_P3041 || \ 1256 ARCH_P4080 || \ 1257 ARCH_P5040 || \ 1258 ARCH_T2080 || \ 1259 ARCH_T4240 1260 default 16 if ARCH_T1024 || \ 1261 ARCH_T1040 || \ 1262 ARCH_T1042 1263 default 12 if ARCH_BSC9131 || \ 1264 ARCH_BSC9132 || \ 1265 ARCH_C29X || \ 1266 ARCH_MPC8536 || \ 1267 ARCH_P1010 || \ 1268 ARCH_P1011 || \ 1269 ARCH_P1020 || \ 1270 ARCH_P1021 || \ 1271 ARCH_P1023 || \ 1272 ARCH_P1024 || \ 1273 ARCH_P1025 || \ 1274 ARCH_P2020 1275 default 10 if ARCH_MPC8544 || \ 1276 ARCH_MPC8548 1277 default 8 if ARCH_MPC8540 || \ 1278 ARCH_MPC8560 1279 help 1280 Number of local access windows. This is fixed per SoC. 1281 If not sure, do not change. 1282 1283config SYS_FSL_CORES_PER_CLUSTER 1284 int 1285 depends on SYS_FSL_QORIQ_CHASSIS2 1286 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240 1287 default 2 if ARCH_B4420 1288 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 1289 1290config SYS_FSL_THREADS_PER_CORE 1291 int 1292 depends on SYS_FSL_QORIQ_CHASSIS2 1293 default 2 if E6500 1294 default 1 1295 1296config SYS_NUM_TLBCAMS 1297 int "Number of TLB CAM entries" 1298 default 64 if E500MC 1299 default 16 1300 help 1301 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1302 16 for other E500 SoCs. 1303 1304config L2_CACHE 1305 bool "Enable L2 cache support" 1306 1307if HETROGENOUS_CLUSTERS 1308 1309config SYS_MAPLE 1310 def_bool y 1311 1312config SYS_CPRI 1313 def_bool y 1314 1315config PPC_CLUSTER_START 1316 int 1317 default 0 1318 1319config DSP_CLUSTER_START 1320 int 1321 default 1 1322 1323config SYS_CPRI_CLK 1324 int 1325 default 3 1326 1327config SYS_ULB_CLK 1328 int 1329 default 4 1330 1331config SYS_ETVPE_CLK 1332 int 1333 default 1 1334 1335config MAX_DSP_CPUS 1336 int 1337 default 12 if ARCH_B4860 1338 default 2 if ARCH_B4420 1339endif 1340 1341config SYS_L2_SIZE_256KB 1342 bool 1343 1344config SYS_L2_SIZE_512KB 1345 bool 1346 1347config SYS_L2_SIZE 1348 int 1349 default 262144 if SYS_L2_SIZE_256KB 1350 default 524288 if SYS_L2_SIZE_512KB 1351 1352config BACKSIDE_L2_CACHE 1353 bool 1354 1355config SYS_L3_SIZE_256KB 1356 bool 1357 1358config SYS_L3_SIZE_512KB 1359 bool 1360 1361config SYS_L3_SIZE_1024KB 1362 bool 1363 1364config SYS_L3_SIZE 1365 int 1366 default 262144 if SYS_L3_SIZE_256KB 1367 default 524288 if SYS_L3_SIZE_512KB 1368 default 1048576 if SYS_L3_SIZE_512KB 1369 1370config SYS_PPC64 1371 bool 1372 1373config SYS_PPC_E500_USE_DEBUG_TLB 1374 bool 1375 1376config FSL_ELBC 1377 bool 1378 1379config SYS_PPC_E500_DEBUG_TLB 1380 int "Temporary TLB entry for external debugger" 1381 depends on SYS_PPC_E500_USE_DEBUG_TLB 1382 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1383 default 1 if ARCH_MPC8536 1384 default 2 if ARCH_P1011 || \ 1385 ARCH_P1020 || \ 1386 ARCH_P1021 || \ 1387 ARCH_P1024 || \ 1388 ARCH_P1025 || \ 1389 ARCH_P2020 1390 default 3 if ARCH_P1010 || \ 1391 ARCH_BSC9132 || \ 1392 ARCH_C29X 1393 help 1394 Select a temporary TLB entry to be used during boot to work 1395 around limitations in e500v1 and e500v2 external debugger 1396 support. This reduces the portions of the boot code where 1397 breakpoints and single stepping do not work. The value of this 1398 symbol should be set to the TLB1 entry to be used for this 1399 purpose. If unsure, do not change. 1400 1401config SYS_FSL_IFC_CLK_DIV 1402 int "Divider of platform clock" 1403 depends on FSL_IFC 1404 default 2 if ARCH_B4420 || \ 1405 ARCH_B4860 || \ 1406 ARCH_T1024 || \ 1407 ARCH_T1040 || \ 1408 ARCH_T1042 || \ 1409 ARCH_T4240 1410 default 1 1411 help 1412 Defines divider of platform clock(clock input to 1413 IFC controller). 1414 1415config SYS_FSL_LBC_CLK_DIV 1416 int "Divider of platform clock" 1417 depends on FSL_ELBC || ARCH_MPC8540 || \ 1418 ARCH_MPC8548 || \ 1419 ARCH_MPC8560 1420 1421 default 2 if ARCH_P2041 || \ 1422 ARCH_P3041 || \ 1423 ARCH_P4080 || \ 1424 ARCH_P5040 1425 default 1 1426 1427 help 1428 Defines divider of platform clock(clock input to 1429 eLBC controller). 1430 1431config ENABLE_36BIT_PHYS 1432 bool "Enable 36bit physical address space support" 1433 1434config SYS_BOOK3E_HV 1435 bool "Category E.HV is supported" 1436 depends on BOOKE 1437 1438config FSL_CORENET 1439 bool 1440 select SYS_FSL_CPC 1441 1442config FSL_NGPIXIS 1443 bool 1444 1445config SYS_CPC_REINIT_F 1446 bool 1447 help 1448 The CPC is configured as SRAM at the time of U-Boot entry and is 1449 required to be re-initialized. 1450 1451config SYS_FSL_CPC 1452 bool 1453 1454config SYS_CACHE_STASHING 1455 bool "Enable cache stashing" 1456 1457config SYS_FSL_PCIE_COMPAT_P4080_PCIE 1458 bool 1459 1460config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 1461 bool 1462 1463config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 1464 bool 1465 1466config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 1467 bool 1468 1469config SYS_FSL_PCIE_COMPAT 1470 string 1471 depends on FSL_CORENET 1472 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE 1473 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 1474 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 1475 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 1476 help 1477 Defines the string to utilize when trying to match PCIe device tree 1478 nodes for the given platform. 1479 1480config SYS_FSL_SINGLE_SOURCE_CLK 1481 bool 1482 1483config SYS_FSL_SRIO_LIODN 1484 bool 1485 1486config SYS_FSL_TBCLK_DIV 1487 int 1488 default 32 if ARCH_P2041 || ARCH_P3041 1489 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \ 1490 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \ 1491 ARCH_T1024 || ARCH_T2080 1492 default 8 1493 help 1494 Defines the core time base clock divider ratio compared to the system 1495 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can 1496 be 16 or 32. The ratio varies from SoC to Soc. 1497 1498config SYS_FSL_USB1_PHY_ENABLE 1499 bool 1500 1501config SYS_FSL_USB2_PHY_ENABLE 1502 bool 1503 1504config SYS_FSL_USB_DUAL_PHY_ENABLE 1505 bool 1506 1507config SYS_MPC85XX_NO_RESETVEC 1508 bool "Discard resetvec section and move bootpg section up" 1509 depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR 1510 help 1511 If this variable is specified, the section .resetvec is not kept and 1512 the section .bootpg is placed in the previous 4k of the .text section. 1513 1514config SPL_SYS_MPC85XX_NO_RESETVEC 1515 bool "Discard resetvec section and move bootpg section up, in SPL" 1516 depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR 1517 help 1518 If this variable is specified, the section .resetvec is not kept and 1519 the section .bootpg is placed in the previous 4k of the .text section, 1520 of the SPL portion of the binary. 1521 1522config TPL_SYS_MPC85XX_NO_RESETVEC 1523 bool "Discard resetvec section and move bootpg section up, in TPL" 1524 depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR 1525 help 1526 If this variable is specified, the section .resetvec is not kept and 1527 the section .bootpg is placed in the previous 4k of the .text section, 1528 of the SPL portion of the binary. 1529 1530config FSL_VIA 1531 bool 1532 1533source "board/emulation/qemu-ppce500/Kconfig" 1534source "board/freescale/mpc8548cds/Kconfig" 1535source "board/freescale/p1010rdb/Kconfig" 1536source "board/freescale/p1_p2_rdb_pc/Kconfig" 1537source "board/freescale/p2041rdb/Kconfig" 1538source "board/freescale/t102xrdb/Kconfig" 1539source "board/freescale/t104xrdb/Kconfig" 1540source "board/freescale/t208xqds/Kconfig" 1541source "board/freescale/t208xrdb/Kconfig" 1542source "board/freescale/t4rdb/Kconfig" 1543source "board/socrates/Kconfig" 1544 1545endmenu 1546