1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select GICV2 8 select SKIP_LOWLEVEL_INIT 9 select SYS_FSL_SRDS_1 10 select SYS_HAS_SERDES 11 select SYS_FSL_DDR_BE 12 select SYS_FSL_MMDC 13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE 14 select SYS_FSL_ERRATUM_A009798 15 select SYS_FSL_ERRATUM_A008997 16 select SYS_FSL_ERRATUM_A009007 17 select SYS_FSL_ERRATUM_A009008 18 select ARCH_EARLY_INIT_R 19 select BOARD_EARLY_INIT_F 20 select SYS_I2C_MXC 21 select SYS_I2C_MXC_I2C1 if !DM_I2C 22 select SYS_I2C_MXC_I2C2 if !DM_I2C 23 imply PANIC_HANG 24 imply TIMESTAMP 25 26config ARCH_LS1028A 27 bool 28 select ARMV8_SET_SMPEN 29 select ESBC_HDR_LS if CHAIN_OF_TRUST 30 select FSL_LAYERSCAPE 31 select FSL_LSCH3 32 select FSL_TZASC_400 33 select GICV3 34 select NXP_LSCH3_2 35 select SYS_FSL_HAS_CCI400 36 select SYS_FSL_SRDS_1 37 select SYS_HAS_SERDES 38 select SYS_FSL_DDR 39 select SYS_FSL_DDR_LE 40 select SYS_FSL_DDR_VER_50 41 select SYS_FSL_HAS_DDR3 42 select SYS_FSL_HAS_DDR4 43 select SYS_FSL_HAS_SEC 44 select SYS_FSL_SEC_COMPAT_5 45 select SYS_FSL_SEC_LE 46 select FSL_TZASC_1 47 select FSL_TZPC_BP147 48 select ARCH_EARLY_INIT_R 49 select BOARD_EARLY_INIT_F 50 select SYS_I2C_MXC 51 select SYS_FSL_ERRATUM_A008997 52 select SYS_FSL_ERRATUM_A009007 53 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 54 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 55 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 56 select SYS_FSL_ERRATUM_A050382 57 select SYS_FSL_ERRATUM_A011334 58 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 59 select RESV_RAM if GIC_V3_ITS 60 select SYS_HAS_ARMV8_SECURE_BASE 61 imply PANIC_HANG 62 63config ARCH_LS1043A 64 bool 65 select ARMV8_SET_SMPEN 66 select ARM_ERRATA_855873 if !TFABOOT 67 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) 68 select FSL_LAYERSCAPE 69 select FSL_LSCH2 70 select GICV2 71 select HAS_FSL_XHCI_USB if USB_HOST 72 select SKIP_LOWLEVEL_INIT 73 select SYS_DPAA_FMAN 74 select SYS_FSL_SRDS_1 75 select SYS_HAS_SERDES 76 select SYS_FSL_DDR 77 select SYS_FSL_DDR_BE 78 select SYS_FSL_DDR_VER_50 79 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 80 select SYS_FSL_ERRATUM_A008997 81 select SYS_FSL_ERRATUM_A009008 82 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 83 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 84 select SYS_FSL_ERRATUM_A009798 85 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 86 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE 87 select SYS_FSL_ERRATUM_A010539 88 select SYS_FSL_HAS_DDR3 89 select SYS_FSL_HAS_DDR4 90 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 91 select ARCH_EARLY_INIT_R 92 select BOARD_EARLY_INIT_F 93 select SYS_I2C_MXC 94 select SYS_I2C_MXC_I2C1 if !DM_I2C 95 select SYS_I2C_MXC_I2C2 if !DM_I2C 96 select SYS_I2C_MXC_I2C3 if !DM_I2C 97 select SYS_I2C_MXC_I2C4 if !DM_I2C 98 select SYS_HAS_ARMV8_SECURE_BASE 99 imply CMD_PCI 100 imply ID_EEPROM 101 102config ARCH_LS1046A 103 bool 104 select ARMV8_SET_SMPEN 105 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) 106 select FSL_LAYERSCAPE 107 select FSL_LSCH2 108 select GICV2 109 select HAS_FSL_XHCI_USB if USB_HOST 110 select SKIP_LOWLEVEL_INIT 111 select SYS_DPAA_FMAN 112 select SYS_FSL_SRDS_1 113 select SYS_HAS_SERDES 114 select SYS_FSL_DDR 115 select SYS_FSL_DDR_BE 116 select SYS_FSL_DDR_VER_50 117 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 118 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 119 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 120 select SYS_FSL_ERRATUM_A008997 121 select SYS_FSL_ERRATUM_A009008 122 select SYS_FSL_ERRATUM_A009798 123 select SYS_FSL_ERRATUM_A009801 124 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 125 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 126 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 127 select SYS_FSL_ERRATUM_A010539 128 select SYS_FSL_HAS_DDR4 129 select SYS_FSL_SRDS_2 130 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 131 select ARCH_EARLY_INIT_R 132 select BOARD_EARLY_INIT_F 133 select SYS_I2C_MXC 134 select SYS_I2C_MXC_I2C1 if !DM_I2C 135 select SYS_I2C_MXC_I2C2 if !DM_I2C 136 select SYS_I2C_MXC_I2C3 if !DM_I2C 137 select SYS_I2C_MXC_I2C4 if !DM_I2C 138 imply ID_EEPROM 139 imply SCSI 140 imply SCSI_AHCI 141 imply SPL_SYS_I2C_LEGACY 142 143config ARCH_LS1088A 144 bool 145 select ARMV8_SET_SMPEN 146 select ARM_ERRATA_855873 if !TFABOOT 147 select ESBC_HDR_LS if CHAIN_OF_TRUST 148 select FSL_IFC 149 select FSL_LAYERSCAPE 150 select FSL_LSCH3 151 select GICV3 152 select SKIP_LOWLEVEL_INIT 153 select SYS_FSL_SRDS_1 154 select SYS_HAS_SERDES 155 select SYS_FSL_DDR 156 select SYS_FSL_DDR_LE 157 select SYS_FSL_DDR_VER_50 158 select SYS_FSL_EC1 159 select SYS_FSL_EC2 160 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 161 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 162 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 163 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 164 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 165 select SYS_FSL_ERRATUM_A009007 166 select SYS_FSL_HAS_CCI400 167 select SYS_FSL_HAS_DDR4 168 select SYS_FSL_HAS_RGMII 169 select SYS_FSL_HAS_SEC 170 select SYS_FSL_SEC_COMPAT_5 171 select SYS_FSL_SEC_LE 172 select SYS_FSL_SRDS_1 173 select SYS_FSL_SRDS_2 174 select FSL_TZASC_1 175 select FSL_TZASC_400 176 select FSL_TZPC_BP147 177 select ARCH_EARLY_INIT_R 178 select BOARD_EARLY_INIT_F 179 select SYS_I2C_MXC 180 select SYS_I2C_MXC_I2C1 if !TFABOOT 181 select SYS_I2C_MXC_I2C2 if !TFABOOT 182 select SYS_I2C_MXC_I2C3 if !TFABOOT 183 select SYS_I2C_MXC_I2C4 if !TFABOOT 184 select RESV_RAM if GIC_V3_ITS 185 imply ID_EEPROM 186 imply SCSI 187 imply SPL_SYS_I2C_LEGACY 188 imply PANIC_HANG 189 190config ARCH_LS2080A 191 bool 192 select ARMV8_SET_SMPEN 193 select ARM_ERRATA_826974 194 select ARM_ERRATA_828024 195 select ARM_ERRATA_829520 196 select ARM_ERRATA_833471 197 select ESBC_HDR_LS if CHAIN_OF_TRUST 198 select FSL_IFC 199 select FSL_LAYERSCAPE 200 select FSL_LSCH3 201 select SYS_FSL_OTHER_DDR_NUM_CTRLS 202 select GICV3 203 select SKIP_LOWLEVEL_INIT 204 select SYS_FSL_SRDS_1 205 select SYS_HAS_SERDES 206 select SYS_FSL_DDR 207 select SYS_FSL_DDR_LE 208 select SYS_FSL_DDR_VER_50 209 select SYS_FSL_HAS_CCN504 210 select SYS_FSL_HAS_DP_DDR 211 select SYS_FSL_HAS_SEC 212 select SYS_FSL_HAS_DDR4 213 select SYS_FSL_SEC_COMPAT_5 214 select SYS_FSL_SEC_LE 215 select SYS_FSL_SRDS_2 216 select FSL_TZASC_1 217 select FSL_TZASC_2 218 select FSL_TZASC_400 219 select FSL_TZPC_BP147 220 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 221 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 222 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 223 select SYS_FSL_ERRATUM_A008585 224 select SYS_FSL_ERRATUM_A008997 225 select SYS_FSL_ERRATUM_A009007 226 select SYS_FSL_ERRATUM_A009008 227 select SYS_FSL_ERRATUM_A009635 228 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 229 select SYS_FSL_ERRATUM_A009798 230 select SYS_FSL_ERRATUM_A009801 231 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 232 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 233 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 234 select SYS_FSL_ERRATUM_A009203 235 select ARCH_EARLY_INIT_R 236 select BOARD_EARLY_INIT_F 237 select SYS_I2C_MXC 238 select SYS_I2C_MXC_I2C1 if !TFABOOT 239 select SYS_I2C_MXC_I2C2 if !TFABOOT 240 select SYS_I2C_MXC_I2C3 if !TFABOOT 241 select SYS_I2C_MXC_I2C4 if !TFABOOT 242 select RESV_RAM if GIC_V3_ITS 243 imply DISTRO_DEFAULTS 244 imply ID_EEPROM 245 imply PANIC_HANG 246 imply SPL_SYS_I2C_LEGACY 247 248config ARCH_LX2162A 249 bool 250 select ARMV8_SET_SMPEN 251 select ESBC_HDR_LS if CHAIN_OF_TRUST 252 select FSL_DDR_BIST 253 select FSL_DDR_INTERACTIVE 254 select FSL_LAYERSCAPE 255 select FSL_LSCH3 256 select FSL_TZPC_BP147 257 select GICV3 258 select NXP_LSCH3_2 259 select SYS_HAS_SERDES 260 select SYS_FSL_SRDS_1 261 select SYS_FSL_SRDS_2 262 select SYS_FSL_DDR 263 select SYS_FSL_DDR_LE 264 select SYS_FSL_DDR_VER_50 265 select SYS_FSL_EC1 266 select SYS_FSL_EC2 267 select SYS_FSL_ERRATUM_A050204 268 select SYS_FSL_ERRATUM_A011334 269 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 270 select SYS_FSL_HAS_RGMII 271 select SYS_FSL_HAS_SEC 272 select SYS_FSL_HAS_CCN508 273 select SYS_FSL_HAS_DDR4 274 select SYS_FSL_SEC_COMPAT_5 275 select SYS_FSL_SEC_LE 276 select SYS_PCI_64BIT if PCI 277 select ARCH_EARLY_INIT_R 278 select BOARD_EARLY_INIT_F 279 select SYS_I2C_MXC 280 select RESV_RAM if GIC_V3_ITS 281 imply DISTRO_DEFAULTS 282 imply PANIC_HANG 283 imply SCSI 284 imply SCSI_AHCI 285 imply SPL_SYS_I2C_LEGACY 286 287config ARCH_LX2160A 288 bool 289 select ARMV8_SET_SMPEN 290 select ESBC_HDR_LS if CHAIN_OF_TRUST 291 select FSL_DDR_BIST 292 select FSL_DDR_INTERACTIVE 293 select FSL_LAYERSCAPE 294 select FSL_LSCH3 295 select FSL_TZPC_BP147 296 select GICV3 297 select HAS_FSL_XHCI_USB if USB_HOST 298 select NXP_LSCH3_2 299 select SYS_HAS_SERDES 300 select SYS_FSL_SRDS_1 301 select SYS_FSL_SRDS_2 302 select SYS_NXP_SRDS_3 303 select SYS_FSL_DDR 304 select SYS_FSL_DDR_LE 305 select SYS_FSL_DDR_VER_50 306 select SYS_FSL_EC1 307 select SYS_FSL_EC2 308 select SYS_FSL_ERRATUM_A050204 309 select SYS_FSL_ERRATUM_A011334 310 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 311 select SYS_FSL_HAS_RGMII 312 select SYS_FSL_HAS_SEC 313 select SYS_FSL_HAS_CCN508 314 select SYS_FSL_HAS_DDR4 315 select SYS_FSL_SEC_COMPAT_5 316 select SYS_FSL_SEC_LE 317 select SYS_PCI_64BIT if PCI 318 select ARCH_EARLY_INIT_R 319 select BOARD_EARLY_INIT_F 320 select SYS_I2C_MXC 321 select RESV_RAM if GIC_V3_ITS 322 imply DISTRO_DEFAULTS 323 imply ID_EEPROM 324 imply PANIC_HANG 325 imply SCSI 326 imply SCSI_AHCI 327 imply SPL_SYS_I2C_LEGACY 328 329config FSL_LSCH2 330 bool 331 select SKIP_LOWLEVEL_INIT 332 select SYS_FSL_CCSR_GUR_BE 333 select SYS_FSL_CCSR_SCFG_BE 334 select SYS_FSL_ESDHC_BE 335 select SYS_FSL_IFC_BE 336 select SYS_FSL_PEX_LUT_BE 337 select SYS_FSL_HAS_CCI400 338 select SYS_FSL_HAS_SEC 339 select SYS_FSL_SEC_COMPAT_5 340 select SYS_FSL_SEC_BE 341 342config FSL_LSCH3 343 select ARCH_MISC_INIT 344 select SYS_FSL_CCSR_GUR_LE 345 select SYS_FSL_CCSR_SCFG_LE 346 select SYS_FSL_ESDHC_LE 347 select SYS_FSL_IFC_LE 348 select SYS_FSL_PEX_LUT_LE 349 bool 350 351config NXP_LSCH3_2 352 bool 353 354config SYS_FSL_CCSR_GUR_BE 355 bool 356 357config SYS_FSL_CCSR_SCFG_BE 358 bool 359 360config SYS_FSL_PEX_LUT_BE 361 bool 362 363config SYS_FSL_CCSR_GUR_LE 364 bool 365 366config SYS_FSL_CCSR_SCFG_LE 367 bool 368 369config SYS_FSL_ESDHC_LE 370 bool 371 372config SYS_FSL_IFC_LE 373 bool 374 375config SYS_FSL_PEX_LUT_LE 376 bool 377 378menu "Layerscape architecture" 379 depends on FSL_LSCH2 || FSL_LSCH3 380 381config FSL_LAYERSCAPE 382 bool 383 select ARM_SMCCC 384 385config HAS_FEATURE_GIC64K_ALIGN 386 bool 387 default y if ARCH_LS1043A 388 389config HAS_FEATURE_ENHANCED_MSI 390 bool 391 default y if ARCH_LS1043A 392 393menu "Layerscape PPA" 394config FSL_LS_PPA 395 bool "FSL Layerscape PPA firmware support" 396 depends on !ARMV8_PSCI 397 select ARMV8_SEC_FIRMWARE_SUPPORT 398 select SEC_FIRMWARE_ARMV8_PSCI 399 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 400 help 401 The FSL Primary Protected Application (PPA) is a software component 402 which is loaded during boot stage, and then remains resident in RAM 403 and runs in the TrustZone after boot. 404 Say y to enable it. 405 406config SPL_FSL_LS_PPA 407 bool "FSL Layerscape PPA firmware support for SPL build" 408 depends on !ARMV8_PSCI 409 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 410 select SEC_FIRMWARE_ARMV8_PSCI 411 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 412 help 413 The FSL Primary Protected Application (PPA) is a software component 414 which is loaded during boot stage, and then remains resident in RAM 415 and runs in the TrustZone after boot. This is to load PPA during SPL 416 stage instead of the RAM version of U-Boot. Once PPA is initialized, 417 the rest of U-Boot (including RAM version) runs at EL2. 418choice 419 prompt "FSL Layerscape PPA firmware loading-media select" 420 depends on FSL_LS_PPA 421 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 422 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 423 default SYS_LS_PPA_FW_IN_XIP 424 425config SYS_LS_PPA_FW_IN_XIP 426 bool "XIP" 427 help 428 Say Y here if the PPA firmware locate at XIP flash, such 429 as NOR or QSPI flash. 430 431config SYS_LS_PPA_FW_IN_MMC 432 bool "eMMC or SD Card" 433 help 434 Say Y here if the PPA firmware locate at eMMC/SD card. 435 436config SYS_LS_PPA_FW_IN_NAND 437 bool "NAND" 438 help 439 Say Y here if the PPA firmware locate at NAND flash. 440 441endchoice 442 443config LS_PPA_ESBC_HDR_SIZE 444 hex "Length of PPA ESBC header" 445 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 446 default 0x2000 447 help 448 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 449 NAND to memory to validate PPA image. 450 451endmenu 452 453config SYS_FSL_ERRATUM_A008997 454 bool "Workaround for USB PHY erratum A008997" 455 456config SYS_FSL_ERRATUM_A009007 457 bool 458 help 459 Workaround for USB PHY erratum A009007 460 461config SYS_FSL_ERRATUM_A009008 462 bool "Workaround for USB PHY erratum A009008" 463 464config SYS_FSL_ERRATUM_A009798 465 bool "Workaround for USB PHY erratum A009798" 466 467config SYS_FSL_ERRATUM_A050204 468 bool "Workaround for USB PHY erratum A050204" 469 help 470 USB3.0 Receiver needs to enable fixed equalization 471 for each of PHY instances in an SOC. This is similar 472 to erratum A-009007, but this one is for LX2160A and LX2162A, 473 and the register value is different. 474 475config SYS_FSL_ERRATUM_A010315 476 bool "Workaround for PCIe erratum A010315" 477 478config SYS_FSL_ERRATUM_A010539 479 bool "Workaround for PIN MUX erratum A010539" 480 481config MAX_CPUS 482 int "Maximum number of CPUs permitted for Layerscape" 483 default 2 if ARCH_LS1028A 484 default 4 if ARCH_LS1043A 485 default 4 if ARCH_LS1046A 486 default 16 if ARCH_LS2080A 487 default 8 if ARCH_LS1088A 488 default 16 if ARCH_LX2160A 489 default 16 if ARCH_LX2162A 490 default 1 491 help 492 Set this number to the maximum number of possible CPUs in the SoC. 493 SoCs may have multiple clusters with each cluster may have multiple 494 ports. If some ports are reserved but higher ports are used for 495 cores, count the reserved ports. This will allocate enough memory 496 in spin table to properly handle all cores. 497 498config EMC2305 499 bool "Fan controller" 500 help 501 Enable the EMC2305 fan controller for configuration of fan 502 speed. 503 504config QSPI_AHB_INIT 505 bool "Init the QSPI AHB bus" 506 help 507 The default setting for QSPI AHB bus just support 3bytes addressing. 508 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 509 bus for those flashes to support the full QSPI flash size. 510 511config FSPI_AHB_EN_4BYTE 512 bool "Enable 4-byte Fast Read command for AHB mode" 513 help 514 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 515 But some FlexSPI flash sizes are up to 64MBytes. 516 This flag enables fast read command for AHB mode and modifies required 517 LUT to support full FlexSPI flash. 518 519config SYS_CCI400_OFFSET 520 hex "Offset for CCI400 base" 521 depends on SYS_FSL_HAS_CCI400 522 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 523 default 0x180000 if FSL_LSCH2 524 help 525 Offset for CCI400 base 526 CCI400 base addr = CCSRBAR + CCI400_OFFSET 527 528config SYS_FSL_HAS_CCI400 529 bool 530 531config SYS_FSL_HAS_CCN504 532 bool 533 534config SYS_FSL_HAS_CCN508 535 bool 536 537config SYS_FSL_HAS_DP_DDR 538 bool 539 help 540 Defines the SoC has DP-DDR used for DPAA. 541 542config DP_DDR_CTRL 543 int 544 depends on SYS_FSL_HAS_DP_DDR 545 default 2 if ARCH_LS2080A 546 547config DP_DDR_DIMM_SLOTS_PER_CTLR 548 int 549 depends on SYS_FSL_HAS_DP_DDR 550 default 1 if ARCH_LS2080A 551 552config DP_DDR_NUM_CTRLS 553 int 554 depends on SYS_FSL_HAS_DP_DDR 555 default 1 if ARCH_LS2080A 556 557config SYS_DP_DDR_BASE 558 hex 559 depends on SYS_FSL_HAS_DP_DDR 560 default 0x6000000000 if ARCH_LS2080A 561 562config SYS_DP_DDR_BASE_PHY 563 int 564 depends on SYS_FSL_HAS_DP_DDR 565 default 0 if ARCH_LS2080A 566 help 567 DDR controller uses this value as the base address for binding. 568 It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 569 570config SYS_NXP_SRDS_3 571 bool 572 573config FSL_TZASC_1 574 bool 575 576config FSL_TZASC_2 577 bool 578 579config FSL_TZASC_400 580 bool 581 582config FSL_TZPC_BP147 583 bool 584endmenu 585 586menu "Layerscape clock tree configuration" 587 depends on FSL_LSCH2 || FSL_LSCH3 588 589config CLUSTER_CLK_FREQ 590 int "Reference clock of core cluster" 591 depends on ARCH_LS1012A 592 default 100000000 593 help 594 This number is the reference clock frequency of core PLL. 595 For most platforms, the core PLL and Platform PLL have the same 596 reference clock, but for some platforms, LS1012A for instance, 597 they are provided sepatately. 598 599config SYS_FSL_PCLK_DIV 600 int "Platform clock divider" 601 default 1 if ARCH_LS1028A 602 default 1 if ARCH_LS1043A 603 default 1 if ARCH_LS1046A 604 default 1 if ARCH_LS1088A 605 default 2 606 help 607 This is the divider that is used to derive Platform clock from 608 Platform PLL, in another word: 609 Platform_clk = Platform_PLL_freq / this_divider 610 611config SYS_FSL_DSPI_CLK_DIV 612 int "DSPI clock divider" 613 default 1 if ARCH_LS1043A 614 default 2 615 help 616 This is the divider that is used to derive DSPI clock from Platform 617 clock, in another word DSPI_clk = Platform_clk / this_divider. 618 619config SYS_FSL_DUART_CLK_DIV 620 int "DUART clock divider" 621 default 1 if ARCH_LS1043A 622 default 4 if ARCH_LX2160A 623 default 4 if ARCH_LX2162A 624 default 2 625 help 626 This is the divider that is used to derive DUART clock from Platform 627 clock, in another word DUART_clk = Platform_clk / this_divider. 628 629config SYS_FSL_I2C_CLK_DIV 630 int "I2C clock divider" 631 default 1 if ARCH_LS1043A 632 default 4 if ARCH_LS1012A 633 default 4 if ARCH_LS1028A 634 default 8 if ARCH_LX2160A 635 default 8 if ARCH_LX2162A 636 default 8 if ARCH_LS1088A 637 default 2 638 help 639 This is the divider that is used to derive I2C clock from Platform 640 clock, in another word I2C_clk = Platform_clk / this_divider. 641 642config SYS_FSL_IFC_CLK_DIV 643 int "IFC clock divider" 644 default 1 if ARCH_LS1043A 645 default 4 if ARCH_LS1012A 646 default 4 if ARCH_LS1028A 647 default 8 if ARCH_LX2160A 648 default 8 if ARCH_LX2162A 649 default 8 if ARCH_LS1088A 650 default 2 651 help 652 This is the divider that is used to derive IFC clock from Platform 653 clock, in another word IFC_clk = Platform_clk / this_divider. 654 655config SYS_FSL_LPUART_CLK_DIV 656 int "LPUART clock divider" 657 default 1 if ARCH_LS1043A 658 default 2 659 help 660 This is the divider that is used to derive LPUART clock from Platform 661 clock, in another word LPUART_clk = Platform_clk / this_divider. 662 663config SYS_FSL_SDHC_CLK_DIV 664 int "SDHC clock divider" 665 default 1 if ARCH_LS1043A 666 default 1 if ARCH_LS1012A 667 default 2 668 help 669 This is the divider that is used to derive SDHC clock from Platform 670 clock, in another word SDHC_clk = Platform_clk / this_divider. 671 672config SYS_FSL_QMAN_CLK_DIV 673 int "QMAN clock divider" 674 default 1 if ARCH_LS1043A 675 default 2 676 help 677 This is the divider that is used to derive QMAN clock from Platform 678 clock, in another word QMAN_clk = Platform_clk / this_divider. 679endmenu 680 681config RESV_RAM 682 bool 683 help 684 Reserve memory from the top, tracked by gd->arch.resv_ram. This 685 reserved RAM can be used by special driver that resides in memory 686 after U-Boot exits. It's up to implementation to allocate and allow 687 access to this reserved memory. For example, the reserved RAM can 688 be at the high end of physical memory. The reserve RAM may be 689 excluded from memory bank(s) passed to OS, or marked as reserved. 690 691config SYS_FSL_EC1 692 bool 693 help 694 Ethernet controller 1, this is connected to 695 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 696 Provides DPAA2 capabilities 697 698config SYS_FSL_EC2 699 bool 700 help 701 Ethernet controller 2, this is connected to 702 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 703 Provides DPAA2 capabilities 704 705config SYS_FSL_ERRATUM_A008336 706 bool 707 708config SYS_FSL_ERRATUM_A008514 709 bool 710 711config SYS_FSL_ERRATUM_A008585 712 bool 713 714config SYS_FSL_ERRATUM_A008850 715 bool 716 717config SYS_FSL_ERRATUM_A009203 718 bool 719 720config SYS_FSL_ERRATUM_A009635 721 bool 722 723config SYS_FSL_ERRATUM_A009660 724 bool 725 726config SYS_FSL_ERRATUM_A050382 727 bool 728 729config SYS_FSL_HAS_RGMII 730 bool 731 depends on SYS_FSL_EC1 || SYS_FSL_EC2 732 733config HAS_FSL_XHCI_USB 734 bool 735 help 736 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 737 pins, select it when the pins are assigned to USB. 738 739config SYS_FSL_BOOTROM_BASE 740 hex 741 depends on FSL_LSCH2 742 default 0 743 744config SYS_FSL_BOOTROM_SIZE 745 hex 746 depends on FSL_LSCH2 747 default 0x1000000 748