1 2menuconfig MTD_RAW_NAND 3 bool "Raw NAND Device Support" 4if MTD_RAW_NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SPL_SYS_NAND_SELF_INIT 13 bool 14 depends on !SPL_NAND_SIMPLE 15 help 16 This option, if enabled, provides more flexible and linux-like 17 NAND initialization process, in SPL. 18 19config TPL_SYS_NAND_SELF_INIT 20 bool 21 depends on TPL_NAND_SUPPORT 22 help 23 This option, if enabled, provides more flexible and linux-like 24 NAND initialization process, in SPL. 25 26config TPL_NAND_INIT 27 bool 28 29config SPL_NAND_INIT 30 bool 31 32config SYS_MAX_NAND_DEVICE 33 int "Maximum number of NAND devices to support" 34 default 1 35 36config SYS_NAND_DRIVER_ECC_LAYOUT 37 bool "Omit standard ECC layouts to save space" 38 help 39 Omit standard ECC layouts to save space. Select this if your driver 40 is known to provide its own ECC layout. 41 42config SYS_NAND_USE_FLASH_BBT 43 bool "Enable BBT (Bad Block Table) support" 44 help 45 Enable the BBT (Bad Block Table) usage. 46 47config SYS_NAND_NO_SUBPAGE_WRITE 48 bool "Disable subpage write support" 49 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD 50 51config DM_NAND_ATMEL 52 bool "Support Atmel NAND controller with DM support" 53 select SYS_NAND_SELF_INIT 54 imply SYS_NAND_USE_FLASH_BBT 55 help 56 Enable this driver for NAND flash platforms using an Atmel NAND 57 controller. 58 59config NAND_ATMEL 60 bool "Support Atmel NAND controller" 61 select SYS_NAND_SELF_INIT 62 imply SYS_NAND_USE_FLASH_BBT 63 help 64 Enable this driver for NAND flash platforms using an Atmel NAND 65 controller. 66 67if NAND_ATMEL 68 69config ATMEL_NAND_HWECC 70 bool "Atmel Hardware ECC" 71 72config ATMEL_NAND_HW_PMECC 73 bool "Atmel Programmable Multibit ECC (PMECC)" 74 select ATMEL_NAND_HWECC 75 help 76 The Programmable Multibit ECC (PMECC) controller is a programmable 77 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 78 79config PMECC_CAP 80 int "PMECC Correctable ECC Bits" 81 depends on ATMEL_NAND_HW_PMECC 82 default 2 83 help 84 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 85 86config PMECC_SECTOR_SIZE 87 int "PMECC Sector Size" 88 depends on ATMEL_NAND_HW_PMECC 89 default 512 90 help 91 Sector size, in bytes, can be 512 or 1024. 92 93config SPL_GENERATE_ATMEL_PMECC_HEADER 94 bool "Atmel PMECC Header Generation" 95 depends on SPL 96 select ATMEL_NAND_HWECC 97 select ATMEL_NAND_HW_PMECC 98 help 99 Generate Programmable Multibit ECC (PMECC) header for SPL image. 100 101choice 102 prompt "NAND bus width (bits)" 103 default SYS_NAND_DBW_8 104 105config SYS_NAND_DBW_8 106 bool "NAND bus width is 8 bits" 107 108config SYS_NAND_DBW_16 109 bool "NAND bus width is 16 bits" 110 111endchoice 112 113endif 114 115config NAND_BRCMNAND 116 bool "Support Broadcom NAND controller" 117 depends on OF_CONTROL && DM && DM_MTD 118 select SYS_NAND_SELF_INIT 119 help 120 Enable the driver for NAND flash on platforms using a Broadcom NAND 121 controller. 122 123config NAND_BRCMNAND_6368 124 bool "Support Broadcom NAND controller on bcm6368" 125 depends on NAND_BRCMNAND && ARCH_BMIPS 126 help 127 Enable support for broadcom nand driver on bcm6368. 128 129config NAND_BRCMNAND_6753 130 bool "Support Broadcom NAND controller on bcm6753" 131 depends on NAND_BRCMNAND && BCM6855 132 help 133 Enable support for broadcom nand driver on bcm6753. 134 135config NAND_BRCMNAND_68360 136 bool "Support Broadcom NAND controller on bcm68360" 137 depends on NAND_BRCMNAND && BCM6856 138 help 139 Enable support for broadcom nand driver on bcm68360. 140 141config NAND_BRCMNAND_6838 142 bool "Support Broadcom NAND controller on bcm6838" 143 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 144 help 145 Enable support for broadcom nand driver on bcm6838. 146 147config NAND_BRCMNAND_6858 148 bool "Support Broadcom NAND controller on bcm6858" 149 depends on NAND_BRCMNAND && BCM6858 150 help 151 Enable support for broadcom nand driver on bcm6858. 152 153config NAND_BRCMNAND_63158 154 bool "Support Broadcom NAND controller on bcm63158" 155 depends on NAND_BRCMNAND && BCM63158 156 help 157 Enable support for broadcom nand driver on bcm63158. 158 159config NAND_BRCMNAND_IPROC 160 bool "Support Broadcom NAND controller on the iproc family" 161 depends on NAND_BRCMNAND 162 help 163 Enable support for broadcom nand driver on the Broadcom 164 iproc family such as Northstar (BCM5301x, BCM4708...) 165 166config NAND_DAVINCI 167 bool "Support TI Davinci NAND controller" 168 select SYS_NAND_SELF_INIT if TARGET_DA850EVM 169 help 170 Enable this driver for NAND flash controllers available in TI Davinci 171 and Keystone2 platforms 172 173choice 174 prompt "Type of ECC used on NAND" 175 default SYS_NAND_4BIT_HW_ECC_OOBFIRST 176 depends on NAND_DAVINCI 177 178config SYS_NAND_HW_ECC 179 bool "Use 1-bit HW ECC" 180 181config SYS_NAND_4BIT_HW_ECC_OOBFIRST 182 bool "Use 4-bit HW ECC with OOB at the front" 183 184config SYS_NAND_SOFT_ECC 185 bool "Use software ECC" 186 187endchoice 188 189choice 190 prompt "NAND page size" 191 depends on NAND_DAVINCI 192 default SYS_NAND_PAGE_2K 193 194config SYS_NAND_PAGE_2K 195 bool "Page size is 2K" 196 197config SYS_NAND_PAGE_4K 198 bool "Page size is 4K" 199 200endchoice 201 202config KEYSTONE_RBL_NAND 203 depends on ARCH_KEYSTONE 204 def_bool y 205 206config SPL_NAND_LOAD 207 def_bool y 208 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT 209 210config NAND_DENALI 211 bool 212 select SYS_NAND_SELF_INIT 213 imply CMD_NAND 214 215config NAND_DENALI_DT 216 bool "Support Denali NAND controller as a DT device" 217 select NAND_DENALI 218 select SPL_SYS_NAND_SELF_INIT 219 depends on OF_CONTROL && DM_MTD 220 help 221 Enable the driver for NAND flash on platforms using a Denali NAND 222 controller as a DT device. 223 224config NAND_FSL_ELBC 225 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver" 226 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT 227 select SPL_SYS_NAND_SELF_INIT 228 select SYS_NAND_SELF_INIT 229 depends on FSL_ELBC 230 help 231 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. 232 233config NAND_FSL_ELBC_DT 234 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)" 235 depends on NAND_FSL_ELBC 236 237config NAND_FSL_IFC 238 bool "Support Freescale Integrated Flash Controller NAND driver" 239 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT 240 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK 241 select SPL_SYS_NAND_SELF_INIT 242 select SYS_NAND_SELF_INIT 243 select FSL_IFC 244 help 245 Enable the Freescale Integrated Flash Controller NAND driver. 246 247config NAND_KIRKWOOD 248 bool "Support for Kirkwood NAND controller" 249 depends on ARCH_KIRKWOOD 250 default y 251 252config NAND_ECC_BCH 253 bool 254 255config NAND_KMETER1 256 bool "Support KMETER1 NAND controller" 257 depends on VENDOR_KM 258 select NAND_ECC_BCH 259 260config NAND_LPC32XX_MLC 261 bool "Support LPC32XX_MLC controller" 262 select SYS_NAND_SELF_INIT 263 help 264 Enable the LPC32XX MLC NAND controller. 265 266config NAND_LPC32XX_SLC 267 bool "Support LPC32XX_SLC controller" 268 help 269 Enable the LPC32XX SLC NAND controller. 270 271config NAND_OMAP_GPMC 272 bool "Support OMAP GPMC NAND controller" 273 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 274 select SYS_NAND_SELF_INIT if ARCH_K3 275 select SPL_NAND_INIT if ARCH_K3 276 select SPL_SYS_NAND_SELF_INIT if ARCH_K3 277 help 278 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 279 GPMC controller is used for parallel NAND flash devices, and can 280 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 281 and BCH16 ECC algorithms. 282 283if NAND_OMAP_GPMC 284 285config NAND_OMAP_GPMC_PREFETCH 286 bool "Enable GPMC Prefetch" 287 default y 288 help 289 On OMAP platforms that use the GPMC controller 290 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 291 uses the prefetch mode to speed up read operations. 292 293config NAND_OMAP_ELM 294 bool "Enable ELM driver for OMAPxx and AMxx platforms." 295 depends on !OMAP34XX 296 help 297 ELM controller is used for ECC error detection (not ECC calculation) 298 of BCH4, BCH8 and BCH16 ECC algorithms. 299 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 300 thus such SoC platforms need to depend on software library for ECC error 301 detection. However ECC calculation on such plaforms would still be 302 done by GPMC controller. 303 304choice 305 prompt "ECC scheme" 306 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 307 help 308 On OMAP platforms, this CONFIG specifies NAND ECC scheme. 309 It can take following values: 310 OMAP_ECC_HAM1_CODE_SW 311 1-bit Hamming code using software lib. 312 (for legacy devices only) 313 OMAP_ECC_HAM1_CODE_HW 314 1-bit Hamming code using GPMC hardware. 315 (for legacy devices only) 316 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW 317 4-bit BCH code (unsupported) 318 OMAP_ECC_BCH4_CODE_HW 319 4-bit BCH code (unsupported) 320 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 321 8-bit BCH code with 322 - ecc calculation using GPMC hardware engine, 323 - error detection using software library. 324 - requires CONFIG_BCH to enable software BCH library 325 (For legacy device which do not have ELM h/w engine) 326 OMAP_ECC_BCH8_CODE_HW 327 8-bit BCH code with 328 - ecc calculation using GPMC hardware engine, 329 - error detection using ELM hardware engine. 330 OMAP_ECC_BCH16_CODE_HW 331 16-bit BCH code with 332 - ecc calculation using GPMC hardware engine, 333 - error detection using ELM hardware engine. 334 335 How to select ECC scheme on OMAP and AMxx platforms ? 336 ----------------------------------------------------- 337 Though higher ECC schemes have more capability to detect and correct 338 bit-flips, but still selection of ECC scheme is dependent on following 339 - hardware engines present in SoC. 340 Some legacy OMAP SoC do not have ELM h/w engine thus such 341 SoC cannot support BCHx_HW ECC schemes. 342 - size of OOB/Spare region 343 With higher ECC schemes, more OOB/Spare area is required to 344 store ECC. So choice of ECC scheme is limited by NAND oobsize. 345 346 In general following expression can help: 347 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES 348 where 349 NAND_OOBSIZE = number of bytes available in 350 OOB/spare area per NAND page. 351 NAND_PAGESIZE = bytes in main-area of NAND page. 352 ECC_BYTES = number of ECC bytes generated to 353 protect 512 bytes of data, which is: 354 3 for HAM1_xx ecc schemes 355 7 for BCH4_xx ecc schemes 356 14 for BCH8_xx ecc schemes 357 26 for BCH16_xx ecc schemes 358 359 example to check for BCH16 on 2K page NAND 360 NAND_PAGESIZE = 2048 361 NAND_OOBSIZE = 64 362 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE 363 Thus BCH16 cannot be supported on 2K page NAND. 364 365 However, for 4K pagesize NAND 366 NAND_PAGESIZE = 4096 367 NAND_OOBSIZE = 224 368 ECC_BYTES = 26 369 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE 370 Thus BCH16 can be supported on 4K page NAND. 371 372config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW 373 bool "1-bit Hamming code using software lib" 374 375config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW 376 bool "1-bit Hamming code using GPMC hardware" 377 378config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW 379 bool "8-bit BCH code with HW calculation SW error detection" 380 381config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 382 bool "8-bit BCH code with HW calculation and error detection" 383 384config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW 385 bool "16-bit BCH code with HW calculation and error detection" 386 387endchoice 388 389config NAND_OMAP_ECCSCHEME 390 int 391 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW 392 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW 393 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW 394 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 395 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW 396 help 397 This must be kept in sync with the enum in 398 include/linux/mtd/omap_gpmc.h 399 400endif 401 402config NAND_VF610_NFC 403 bool "Support for Freescale NFC for VF610" 404 select SYS_NAND_SELF_INIT 405 select SYS_NAND_DRIVER_ECC_LAYOUT 406 imply CMD_NAND 407 help 408 Enables support for NAND Flash Controller on some Freescale 409 processors like the VF610, MCF54418 or Kinetis K70. 410 The driver supports a maximum 2k page size. The driver 411 currently does not support hardware ECC. 412 413if NAND_VF610_NFC 414 415config NAND_VF610_NFC_DT 416 bool "Support Vybrid's vf610 NAND controller as a DT device" 417 depends on OF_CONTROL && DM_MTD 418 help 419 Enable the driver for Vybrid's vf610 NAND flash on platforms 420 using device tree. 421 422choice 423 prompt "Hardware ECC strength" 424 depends on NAND_VF610_NFC 425 default SYS_NAND_VF610_NFC_45_ECC_BYTES 426 help 427 Select the ECC strength used in the hardware BCH ECC block. 428 429config SYS_NAND_VF610_NFC_45_ECC_BYTES 430 bool "24-error correction (45 ECC bytes)" 431 432config SYS_NAND_VF610_NFC_60_ECC_BYTES 433 bool "32-error correction (60 ECC bytes)" 434 435endchoice 436 437endif 438 439config NAND_PXA3XX 440 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 441 select SYS_NAND_SELF_INIT 442 select DM_MTD 443 select REGMAP 444 select SYSCON 445 imply CMD_NAND 446 help 447 This enables the driver for the NAND flash device found on 448 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 449 450config NAND_SUNXI 451 bool "Support for NAND on Allwinner SoCs" 452 default ARCH_SUNXI 453 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 454 select SYS_NAND_SELF_INIT 455 select SYS_NAND_U_BOOT_LOCATIONS 456 select SPL_NAND_SUPPORT 457 select SPL_SYS_NAND_SELF_INIT 458 imply CMD_NAND 459 ---help--- 460 Enable support for NAND. This option enables the standard and 461 SPL drivers. 462 The SPL driver only supports reading from the NAND using DMA 463 transfers. 464 465if NAND_SUNXI 466 467config NAND_SUNXI_SPL_ECC_STRENGTH 468 int "Allwinner NAND SPL ECC Strength" 469 default 64 470 471config NAND_SUNXI_SPL_ECC_SIZE 472 int "Allwinner NAND SPL ECC Step Size" 473 default 1024 474 475config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 476 int "Allwinner NAND SPL Usable Page Size" 477 default 1024 478 479endif 480 481config NAND_ARASAN 482 bool "Configure Arasan Nand" 483 select SYS_NAND_SELF_INIT 484 depends on DM_MTD 485 imply CMD_NAND 486 help 487 This enables Nand driver support for Arasan nand flash 488 controller. This uses the hardware ECC for read and 489 write operations. 490 491config NAND_MXC 492 bool "MXC NAND support" 493 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 494 imply CMD_NAND 495 help 496 This enables the NAND driver for the NAND flash controller on the 497 i.MX27 / i.MX31 / i.MX5 processors. 498 499config SYS_NAND_SIZE 500 int "Size of NAND in kilobytes" 501 depends on NAND_MXC && SPL_NAND_SUPPORT 502 default 268435456 503 504config MXC_NAND_HWECC 505 bool "Hardware ECC support in MXC NAND" 506 depends on NAND_MXC 507 508config NAND_MXS 509 bool "MXS NAND support" 510 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M 511 select SPL_SYS_NAND_SELF_INIT 512 select SYS_NAND_SELF_INIT 513 imply CMD_NAND 514 select APBH_DMA 515 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 516 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 517 help 518 This enables NAND driver for the NAND flash controller on the 519 MXS processors. 520 521if NAND_MXS 522 523config NAND_MXS_DT 524 bool "Support MXS NAND controller as a DT device" 525 depends on OF_CONTROL && DM_MTD 526 help 527 Enable the driver for MXS NAND flash on platforms using 528 device tree. 529 530config NAND_MXS_USE_MINIMUM_ECC 531 bool "Use minimum ECC strength supported by the controller" 532 default false 533 534endif 535 536config NAND_MXIC 537 bool "Macronix raw NAND controller" 538 select SYS_NAND_SELF_INIT 539 help 540 This selects the Macronix raw NAND controller driver. 541 542config NAND_ZYNQ 543 bool "Support for Zynq Nand controller" 544 select SPL_SYS_NAND_SELF_INIT 545 select SYS_NAND_SELF_INIT 546 select DM_MTD 547 imply CMD_NAND 548 help 549 This enables Nand driver support for Nand flash controller 550 found on Zynq SoC. 551 552config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 553 bool "Enable use of 1st stage bootloader timing for NAND" 554 depends on NAND_ZYNQ 555 help 556 This flag prevent U-boot reconfigure NAND flash controller and reuse 557 the NAND timing from 1st stage bootloader. 558 559config NAND_OCTEONTX 560 bool "Support for OcteonTX NAND controller" 561 select SYS_NAND_SELF_INIT 562 imply CMD_NAND 563 help 564 This enables Nand flash controller hardware found on the OcteonTX 565 processors. 566 567config NAND_OCTEONTX_HW_ECC 568 bool "Support Hardware ECC for OcteonTX NAND controller" 569 depends on NAND_OCTEONTX 570 default y 571 help 572 This enables Hardware BCH engine found on the OcteonTX processors to 573 support ECC for NAND flash controller. 574 575config NAND_STM32_FMC2 576 bool "Support for NAND controller on STM32MP SoCs" 577 depends on ARCH_STM32MP 578 select SYS_NAND_SELF_INIT 579 imply CMD_NAND 580 help 581 Enables support for NAND Flash chips on SoCs containing the FMC2 582 NAND controller. This controller is found on STM32MP SoCs. 583 The controller supports a maximum 8k page size and supports 584 a maximum 8-bit correction error per sector of 512 bytes. 585 586config CORTINA_NAND 587 bool "Support for NAND controller on Cortina-Access SoCs" 588 depends on CORTINA_PLATFORM 589 select SYS_NAND_SELF_INIT 590 select DM_MTD 591 imply CMD_NAND 592 help 593 Enables support for NAND Flash chips on Coartina-Access SoCs platform 594 This controller is found on Presidio/Venus SoCs. 595 The controller supports a maximum 8k page size and supports 596 a maximum 40-bit error correction per sector of 1024 bytes. 597 598config ROCKCHIP_NAND 599 bool "Support for NAND controller on Rockchip SoCs" 600 depends on ARCH_ROCKCHIP 601 select SYS_NAND_SELF_INIT 602 select DM_MTD 603 imply CMD_NAND 604 help 605 Enables support for NAND Flash chips on Rockchip SoCs platform. 606 This controller is found on Rockchip SoCs. 607 There are four different versions of NAND FLASH Controllers, 608 including: 609 NFC v600: RK2928, RK3066, RK3188 610 NFC v622: RK3036, RK3128 611 NFC v800: RK3308, RV1108 612 NFC v900: PX30, RK3326 613 614config TEGRA_NAND 615 bool "Support for NAND controller on Tegra SoCs" 616 depends on ARCH_TEGRA 617 select SYS_NAND_SELF_INIT 618 imply CMD_NAND 619 help 620 Enables support for NAND Flash chips on Tegra SoCs platforms. 621 622config NAND_MT7621 623 bool "Support for MediaTek MT7621 NAND flash controller" 624 depends on SOC_MT7621 625 select SYS_NAND_SELF_INIT 626 select SPL_SYS_NAND_SELF_INIT 627 imply CMD_NAND 628 help 629 This enables NAND driver for the NAND flash controller on MediaTek 630 MT7621 platform. 631 The controller supports 4~12 bits correction per 512 bytes with a 632 maximum 4KB page size. 633 634comment "Generic NAND options" 635 636config SYS_NAND_BLOCK_SIZE 637 hex "NAND chip eraseblock size" 638 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \ 639 MVEBU_SPL_BOOT_DEVICE_NAND 640 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \ 641 !NAND_FSL_IFC && !NAND_MT7621 642 help 643 Number of data bytes in one eraseblock for the NAND chip on the 644 board. This is the multiple of NAND_PAGE_SIZE and the number of 645 pages. 646 647config SYS_NAND_ONFI_DETECTION 648 bool "Enable detection of ONFI compliant devices during probe" 649 help 650 Enables detection of ONFI compliant devices during probe. 651 And fetching device parameters flashed on device, by parsing 652 ONFI parameter page. 653 654config SYS_NAND_PAGE_COUNT 655 hex "NAND chip page count" 656 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ 657 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \ 658 NAND_OMAP_GPMC) 659 help 660 Number of pages in the NAND chip. 661 662config SYS_NAND_PAGE_SIZE 663 hex "NAND chip page size" 664 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ 665 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ 666 MVEBU_SPL_BOOT_DEVICE_NAND || \ 667 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER 668 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621 669 help 670 Number of data bytes in one page for the NAND chip on the 671 board, not including the OOB area. 672 673config SYS_NAND_OOBSIZE 674 hex "NAND chip OOB size" 675 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ 676 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ 677 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER 678 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC 679 help 680 Number of bytes in the Out-Of-Band area for the NAND chip on 681 the board. 682 683# Enhance depends when converting drivers to Kconfig which use this config 684# option (mxc_nand, ndfc, omap_gpmc). 685config SYS_NAND_BUSWIDTH_16BIT 686 bool "Use 16-bit NAND interface" 687 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 688 help 689 Indicates that NAND device has 16-bit wide data-bus. In absence of this 690 config, bus-width of NAND device is assumed to be either 8-bit and later 691 determined by reading ONFI params. 692 Above config is useful when NAND device's bus-width information cannot 693 be determined from on-chip ONFI params, like in following scenarios: 694 - SPL boot does not support reading of ONFI parameters. This is done to 695 keep SPL code foot-print small. 696 - In current U-Boot flow using nand_init(), driver initialization 697 happens in board_nand_init() which is called before any device probe 698 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 699 not available while configuring controller. So a static CONFIG_NAND_xx 700 is needed to know the device's bus-width in advance. 701 702if SPL 703 704config SYS_NAND_5_ADDR_CYCLE 705 bool "Wait 5 address cycles during NAND commands" 706 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \ 707 (SPL_NAND_SUPPORT && NAND_ATMEL) 708 default y 709 help 710 Some controllers require waiting for 5 address cycles when issuing 711 some commands, on NAND chips larger than 128MiB. 712 713choice 714 prompt "NAND bad block marker/indicator position in the OOB" 715 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \ 716 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC) 717 default HAS_NAND_LARGE_BADBLOCK_POS 718 help 719 In the OOB, which position contains the badblock information. 720 721config HAS_NAND_LARGE_BADBLOCK_POS 722 bool "Set the bad block marker/indicator to the 'large' position" 723 724config HAS_NAND_SMALL_BADBLOCK_POS 725 bool "Set the bad block marker/indicator to the 'small' position" 726 727endchoice 728 729config SYS_NAND_BAD_BLOCK_POS 730 int 731 default 0 if HAS_NAND_LARGE_BADBLOCK_POS 732 default 5 if HAS_NAND_SMALL_BADBLOCK_POS 733 734config SYS_NAND_U_BOOT_LOCATIONS 735 bool "Define U-boot binaries locations in NAND" 736 help 737 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 738 This option should not be enabled when compiling U-boot for boards 739 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 740 file. 741 742config SYS_NAND_U_BOOT_OFFS 743 hex "Location in NAND to read U-Boot from" 744 default 0x800000 if NAND_SUNXI 745 depends on SYS_NAND_U_BOOT_LOCATIONS 746 help 747 Set the offset from the start of the nand where u-boot should be 748 loaded from. 749 750config SYS_NAND_U_BOOT_OFFS_REDUND 751 hex "Location in NAND to read U-Boot from" 752 default SYS_NAND_U_BOOT_OFFS 753 depends on SYS_NAND_U_BOOT_LOCATIONS 754 help 755 Set the offset from the start of the nand where the redundant u-boot 756 should be loaded from. 757 758config SPL_NAND_AM33XX_BCH 759 bool "Enables SPL-NAND driver which supports ELM based" 760 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX 761 default y 762 help 763 Hardware ECC correction. This is useful for platforms which have ELM 764 hardware engine and use NAND boot mode. 765 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 766 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 767 SPL-NAND driver with software ECC correction support. 768 769config SPL_NAND_DENALI 770 bool "Support Denali NAND controller for SPL" 771 depends on SPL_NAND_SUPPORT 772 help 773 This is a small implementation of the Denali NAND controller 774 for use on SPL. 775 776config NAND_DENALI_SPARE_AREA_SKIP_BYTES 777 int "Number of bytes skipped in OOB area" 778 depends on SPL_NAND_DENALI 779 range 0 63 780 help 781 This option specifies the number of bytes to skip from the beginning 782 of OOB area before last ECC sector data starts. This is potentially 783 used to preserve the bad block marker in the OOB area. 784 785config SPL_NAND_SIMPLE 786 bool "Use simple SPL NAND driver" 787 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT 788 help 789 Support for NAND boot using simple NAND drivers that 790 expose the cmd_ctrl() interface. 791 792config SYS_NAND_HW_ECC_OOBFIRST 793 bool "In SPL, read the OOB first and then the data from NAND" 794 depends on SPL_NAND_SIMPLE 795 796endif 797 798endif # if NAND 799