1
2config BITBANGMII
3	bool "Bit-banged ethernet MII management channel support"
4
5config BITBANGMII_MULTI
6	bool "Enable the multi bus support"
7	depends on BITBANGMII
8
9config MV88E6352_SWITCH
10	bool "Marvell 88E6352 switch support"
11
12menuconfig PHYLIB
13	bool "Ethernet PHY (physical media interface) support"
14	depends on NET
15	help
16	  Enable Ethernet PHY (physical media interface) support.
17
18if PHYLIB
19
20config PHY_ADDR_ENABLE
21	bool "Limit phy address"
22	default y if ARCH_SUNXI
23	help
24	  Select this if you want to control which phy address is used
25
26if PHY_ADDR_ENABLE
27config PHY_ADDR
28	int "PHY address"
29	default 1 if ARCH_SUNXI
30	default 0
31	help
32	  The address of PHY on MII bus. Usually in range of 0 to 31.
33endif
34
35config B53_SWITCH
36	bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
37	help
38	  Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
39	  This currently supports BCM53125 and similar models.
40
41if B53_SWITCH
42
43config B53_CPU_PORT
44	int "CPU port"
45	default 8
46
47config B53_PHY_PORTS
48	hex "Bitmask of PHY ports"
49
50endif # B53_SWITCH
51
52config MV88E61XX_SWITCH
53	bool "Marvell MV88E61xx Ethernet switch PHY support."
54
55if MV88E61XX_SWITCH
56
57config MV88E61XX_CPU_PORT
58	int "CPU Port"
59
60config MV88E61XX_PHY_PORTS
61	hex "Bitmask of PHY Ports"
62
63config MV88E61XX_FIXED_PORTS
64	hex "Bitmask of PHYless serdes Ports"
65	default 0x0
66	help
67	  These are ports without PHYs that may be wired directly to other
68	  serdes interfaces
69
70endif # MV88E61XX_SWITCH
71
72config PHYLIB_10G
73	bool "Generic 10G PHY support"
74
75config PHY_ADIN
76	bool "Analog Devices Industrial Ethernet PHYs"
77	help
78		Add support for configuring RGMII on Analog Devices ADIN PHYs.
79
80menuconfig PHY_AQUANTIA
81	bool "Aquantia Ethernet PHYs support"
82	select PHY_GIGE
83	select PHYLIB_10G
84
85config PHY_AQUANTIA_UPLOAD_FW
86	bool "Aquantia firmware loading support"
87	depends on PHY_AQUANTIA
88	help
89		Aquantia PHYs use firmware which can be either loaded automatically
90		from storage directly attached to the phy or loaded by the boot loader
91		via MDIO commands.  The firmware is loaded from a file, specified by
92		the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
93
94config PHY_AQUANTIA_FW_PART
95	string "Aquantia firmware partition"
96	depends on PHY_AQUANTIA_UPLOAD_FW
97	help
98		Partition containing the firmware file.
99
100config PHY_AQUANTIA_FW_NAME
101	string "Aquantia firmware filename"
102	depends on PHY_AQUANTIA_UPLOAD_FW
103	help
104		Firmware filename.
105
106config PHY_ATHEROS
107	bool "Atheros Ethernet PHYs support"
108
109config SPL_PHY_ATHEROS
110	bool "Atheros Ethernet PHYs support (SPL)"
111
112config PHY_BROADCOM
113	bool "Broadcom Ethernet PHYs support"
114
115config PHY_CORTINA
116	bool "Cortina Ethernet PHYs support"
117
118config SYS_CORTINA_NO_FW_UPLOAD
119	bool "Cortina firmware loading support"
120	depends on PHY_CORTINA
121	help
122		Cortina phy has provision to store phy firmware in attached dedicated
123		EEPROM. And boards designed with such EEPROM does not require firmware
124		upload.
125
126choice
127	prompt "Location of the Cortina firmware"
128	default SYS_CORTINA_FW_IN_NOR
129	depends on PHY_CORTINA
130
131config SYS_CORTINA_FW_IN_MMC
132	bool "Cortina firmware in MMC"
133
134config SYS_CORTINA_FW_IN_NAND
135	bool "Cortina firmware in NAND flash"
136
137config SYS_CORTINA_FW_IN_NOR
138	bool "Cortina firmware in NOR flash"
139
140config SYS_CORTINA_FW_IN_REMOTE
141	bool "Cortina firmware in remote device"
142
143config SYS_CORTINA_FW_IN_SPIFLASH
144	bool "Cortina firmware in SPI flash"
145
146endchoice
147
148config CORTINA_FW_ADDR
149	hex "Cortina Firmware Address"
150	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
151	default 0x0
152
153config CORTINA_FW_LENGTH
154	hex "Cortina Firmware Length"
155	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
156	default 0x40000
157
158config PHY_CORTINA_ACCESS
159	bool "Cortina Access Ethernet PHYs support"
160	default y
161	depends on CORTINA_NI_ENET
162	help
163		Cortina Access Ethernet PHYs init process
164
165config PHY_DAVICOM
166	bool "Davicom Ethernet PHYs support"
167
168config PHY_ET1011C
169	bool "LSI TruePHY ET1011C support"
170
171config PHY_LXT
172	bool "LXT971 Ethernet PHY support"
173
174config PHY_MARVELL
175	bool "Marvell Ethernet PHYs support"
176
177config PHY_MARVELL_10G
178	bool "Marvell Alaska 10Gbit PHYs"
179	help
180	  Support for the Marvell Alaska MV88X3310 and compatible PHYs.
181
182config PHY_MESON_GXL
183	bool "Amlogic Meson GXL Internal PHY support"
184
185config PHY_MICREL
186	bool "Micrel Ethernet PHYs support"
187	help
188	  Enable support for the GbE PHYs manufactured by Micrel (now
189	  a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
190	  KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
191	  family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
192	  KSZ90x1 family support" is selected).
193
194if PHY_MICREL
195
196config PHY_MICREL_KSZ9021
197	bool
198	select PHY_MICREL_KSZ90X1
199
200config PHY_MICREL_KSZ9031
201	bool
202	select PHY_MICREL_KSZ90X1
203
204config PHY_MICREL_KSZ90X1
205	bool "Micrel KSZ90x1 family support"
206	select PHY_GIGE
207	help
208	  Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
209	  enabled, the extended register read/write for KSZ90x1 PHYs
210	  is supported through the 'mdio' command and any RGMII signal
211	  delays configured in the device tree will be applied to the
212	  PHY during initialization.
213
214config PHY_MICREL_KSZ8XXX
215	bool "Micrel KSZ8xxx family support"
216	help
217	  Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
218	  (now a part of Microchip). This includes drivers for the KSZ804,
219	  KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
220
221endif # PHY_MICREL
222
223config PHY_MSCC
224	bool "Microsemi Corp Ethernet PHYs support"
225
226config PHY_NATSEMI
227	bool "National Semiconductor Ethernet PHYs support"
228
229config PHY_NXP_C45_TJA11XX
230	tristate "NXP C45 TJA11XX PHYs"
231	help
232	  Enable support for NXP C45 TJA11XX PHYs.
233	  Currently supports only the TJA1103 PHY.
234
235config PHY_NXP_TJA11XX
236	bool "NXP TJA11XX Ethernet PHYs support"
237	help
238	  Currently supports the NXP TJA1100 and TJA1101 PHY.
239
240config PHY_REALTEK
241	bool "Realtek Ethernet PHYs support"
242
243config RTL8211X_PHY_FORCE_MASTER
244	bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
245	depends on PHY_REALTEK
246	help
247	  Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
248	  This can work around link stability and data corruption issues on gigabit
249	  links which can occur in slave mode on certain PHYs, e.g. on the
250	  RTL8211C(L).
251
252	  Please note that two directly connected devices (i.e. via crossover cable)
253	  will not be able to establish a link between each other if they both force
254	  master mode. Multiple devices forcing master mode when connected by a
255	  network switch do not pose a problem as the switch configures its affected
256	  ports into slave mode.
257
258	  This option only affects gigabit links. If you must establish a direct
259	  connection between two devices which both force master mode, try forcing
260	  the link speed to 100MBit/s.
261
262	  If unsure, say N.
263
264config RTL8211F_PHY_FORCE_EEE_RXC_ON
265	bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
266	depends on PHY_REALTEK
267	help
268	  The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
269	  transitions to/from a lower power consumption level (Low Power Idle
270	  mode) based on link utilization. When no packets are being
271	  transmitted, the system goes to Low Power Idle mode to save power.
272
273	  Under particular circumstances this setting can cause issues where
274	  the PHY is unable to transmit or receive any packet when in LPI mode.
275	  The problem is caused when the PHY is configured to stop receiving
276	  the xMII clock while it is signaling LPI. For some PHYs the bit
277	  configuring this behavior is set by the Linux kernel, causing the
278	  issue in U-Boot on reboot if the PHY retains the register value.
279
280	  Default n, which means that the PHY state is not changed. To work
281	  around the issues, change this setting to y.
282
283config RTL8201F_PHY_S700_RMII_TIMINGS
284	bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
285	depends on PHY_REALTEK
286	help
287	  This provides an option to configure specific timing requirements (needed
288	  for proper PHY operations) for the PHY module present on ACTION SEMI S700
289	  based cubieboard7. Exact timing requiremnets seems to be SoC specific
290	  (and it's undocumented) that comes from vendor code itself.
291
292config PHY_SMSC
293	bool  "Microchip(SMSC) Ethernet PHYs support"
294
295config PHY_TERANETICS
296	bool "Teranetics Ethernet PHYs support"
297
298config PHY_TI
299	bool "Texas Instruments Ethernet PHYs support"
300	---help---
301	  Adds PHY registration support for TI PHYs.
302
303config PHY_TI_DP83867
304	select PHY_TI
305	bool "Texas Instruments Ethernet DP83867 PHY support"
306	---help---
307	  Adds support for the TI DP83867 1Gbit PHY.
308
309config PHY_TI_DP83869
310	select PHY_TI
311	bool "Texas Instruments Ethernet DP83869 PHY support"
312	---help---
313	  Adds support for the TI DP83869 1Gbit PHY.
314
315config PHY_TI_GENERIC
316	select PHY_TI
317	bool "Texas Instruments Generic Ethernet PHYs support"
318	---help---
319	  Adds support for Generic TI PHYs that don't need special handling but
320	  the PHY name is associated with a PHY ID.
321
322config PHY_VITESSE
323	bool "Vitesse Ethernet PHYs support"
324
325config PHY_XILINX
326	bool "Xilinx Ethernet PHYs support"
327
328config PHY_XILINX_GMII2RGMII
329	bool "Xilinx GMII to RGMII Ethernet PHYs support"
330	help
331	  This adds support for Xilinx GMII to RGMII IP core. This IP acts
332	  as bridge between MAC connected over GMII and external phy that
333	  is connected over RGMII interface.
334
335config PHY_XWAY
336	bool "Intel XWAY PHY support"
337	help
338	  This adds support for the Intel XWAY (formerly Lantiq) Gbe PHYs.
339
340config PHY_ETHERNET_ID
341	bool "Read ethernet PHY id"
342	depends on DM_GPIO
343	default y if ZYNQ_GEM
344	help
345	  Enable this config to read ethernet phy id from the phy node of DT
346	  and create a phy device using id.
347
348config PHY_FIXED
349	bool "Fixed-Link PHY"
350	help
351	  Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
352	  connection (MII, RGMII, ...).
353	  There is nothing like autoneogation and so
354	  on, the link is always up with fixed speed and fixed duplex-setting.
355	  More information: doc/device-tree-bindings/net/fixed-link.txt
356
357config PHY_NCSI
358	bool "NC-SI based PHY"
359
360endif #PHYLIB
361
362config FSL_MEMAC
363	bool "NXP mEMAC PHY support"
364
365config SYS_MEMAC_LITTLE_ENDIAN
366	bool "mEMAC is access in little endian mode"
367	depends on FSL_MEMAC || FSL_LS_MDIO
368
369config PHY_RESET_DELAY
370	int "Extra delay after reset before MII register access"
371	default 0
372	help
373	  Some PHYs need extra delay after reset before any MII register access
374	  is possible.  For such PHY, set this option to the usec delay
375	  required.
376