1config RISCV
2	def_bool y
3	select FUNCTION_ALIGNMENT_16B
4
5config RISCV_64
6	def_bool y
7	select 64BIT
8
9config ARCH_DEFCONFIG
10	string
11	default "arch/riscv/configs/tiny64_defconfig"
12
13menu "Architecture Features"
14
15source "arch/Kconfig"
16
17endmenu
18
19menu "ISA Selection"
20
21choice
22	prompt "Base ISA"
23	default RISCV_ISA_RV64G if RISCV_64
24	help
25	  This selects the base ISA extensions that Xen will target.
26
27config RISCV_ISA_RV64G
28	bool "RV64G"
29	help
30	  Use the RV64I base ISA, plus
31	  "M" for multiply/divide,
32	  "A" for atomic instructions,
33	  “F”/"D" for  {single/double}-precision floating-point instructions,
34	  "Zicsr" for control and status register access,
35	  "Zifencei" for instruction-fetch fence.
36
37endchoice
38
39config RISCV_ISA_C
40	bool "Compressed extension"
41	default y
42	help
43	  Add "C" to the ISA subsets that the toolchain is allowed to
44	  emit when building Xen, which results in compressed instructions
45	  in the Xen binary.
46
47	  If unsure, say Y.
48
49endmenu
50
51source "common/Kconfig"
52
53source "drivers/Kconfig"
54