1if ARCH_STM32MP
2
3config SPL
4	select SPL_BOARD_INIT
5	select SPL_CLK
6	select SPL_DM
7	select SPL_DM_SEQ_ALIAS
8	select SPL_DRIVERS_MISC
9	select SPL_FRAMEWORK
10	select SPL_GPIO
11	select SPL_LIBCOMMON_SUPPORT
12	select SPL_LIBGENERIC_SUPPORT
13	select SPL_OF_CONTROL
14	select SPL_OF_TRANSLATE
15	select SPL_PINCTRL
16	select SPL_REGMAP
17	select SPL_DM_RESET
18	select SPL_SERIAL
19	select SPL_SYSCON
20	select SPL_WATCHDOG if WATCHDOG
21	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22	imply SPL_BOOTSTAGE if BOOTSTAGE
23	imply SPL_DISPLAY_PRINT
24	imply SPL_LIBDISK_SUPPORT
25	imply SPL_SPI_LOAD if SPL_SPI
26
27config SYS_SOC
28	default "stm32mp"
29
30config SYS_MALLOC_LEN
31	default 0x2000000
32
33config ENV_SIZE
34	default 0x2000
35
36choice
37	prompt "Select STMicroelectronics STM32MPxxx Soc"
38	default STM32MP15x
39
40config STM32MP13x
41	bool "Support STMicroelectronics STM32MP13x Soc"
42	select ARM_SMCCC
43	select CPU_V7A
44	select CPU_V7_HAS_NONSEC
45	select CPU_V7_HAS_VIRT
46	select OF_BOARD
47	select OF_BOARD_SETUP
48	select PINCTRL_STM32
49	select STM32_RCC
50	select STM32_RESET
51	select STM32_SERIAL
52	select SYS_ARCH_TIMER
53	imply CMD_NVEDIT_INFO
54	help
55		support of STMicroelectronics SOC STM32MP13x family
56		STMicroelectronics MPU with core ARMv7
57
58config STM32MP15x
59	bool "Support STMicroelectronics STM32MP15x Soc"
60	select ARCH_SUPPORT_PSCI
61	select BINMAN
62	select CPU_V7A
63	select CPU_V7_HAS_NONSEC
64	select CPU_V7_HAS_VIRT
65	select OF_BOARD if TFABOOT
66	select OF_BOARD_SETUP
67	select PINCTRL_STM32
68	select STM32_RCC
69	select STM32_RESET
70	select STM32_SERIAL
71	select SUPPORT_SPL
72	select SYS_ARCH_TIMER
73	imply CMD_NVEDIT_INFO
74	help
75		support of STMicroelectronics SOC STM32MP15x family
76		STM32MP157, STM32MP153 or STM32MP151
77		STMicroelectronics MPU with core ARMv7
78		dual core A7 for STM32MP157/3, monocore for STM32MP151
79endchoice
80
81config NR_DRAM_BANKS
82	default 1
83
84config DDR_CACHEABLE_SIZE
85	hex "Size of the DDR marked cacheable in pre-reloc stage"
86	default 0x40000000
87	help
88		Define the size of the DDR marked as cacheable in U-Boot
89		pre-reloc stage.
90		This option can be useful to avoid speculatif access
91		to secured area of DDR used by TF-A or OP-TEE before U-Boot
92		initialization.
93		The areas marked "no-map" in device tree should be located
94		before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
95
96config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
97	hex "Partition on MMC2 to use to load U-Boot from"
98	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
99	default 1
100	help
101	  Partition on the second MMC to load U-Boot from when the MMC is being
102	  used in raw mode
103
104config STM32_ETZPC
105	bool "STM32 Extended TrustZone Protection"
106	depends on STM32MP15x || STM32MP13x
107	default y
108	imply BOOTP_SERVERIP
109	help
110	  Say y to enable STM32 Extended TrustZone Protection
111
112config STM32_ECDSA_VERIFY
113	bool "STM32 ECDSA verification via the ROM API"
114	depends on SPL_ECDSA_VERIFY
115	default y
116	help
117	  Say y to enable the uclass driver for ECDSA verification using the
118	  ROM API provided on STM32MP.
119	  The ROM API is only available during SPL for now.
120
121config CMD_STM32KEY
122	bool "command stm32key to fuse public key hash"
123	help
124		fuse public key hash in corresponding fuse used to authenticate
125		binary.
126		This command is used to evaluate the secure boot on stm32mp SOC,
127		it is deactivated by default in real products.
128
129source "arch/arm/mach-stm32mp/Kconfig.13x"
130source "arch/arm/mach-stm32mp/Kconfig.15x"
131
132source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
133endif
134