1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * Copyright (C) 2018 Renesas Electronics Corp. 7 * 8 */ 9 10 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 13 enum rcar_gen3_clk_types { 14 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 15 CLK_TYPE_GEN3_PLL0, 16 CLK_TYPE_GEN3_PLL1, 17 CLK_TYPE_GEN3_PLL2, 18 CLK_TYPE_GEN3_PLL3, 19 CLK_TYPE_GEN3_PLL4, 20 CLK_TYPE_GEN3_SDH, 21 CLK_TYPE_R8A77970_SD0H, 22 CLK_TYPE_GEN3_SD, 23 CLK_TYPE_R8A77970_SD0, 24 CLK_TYPE_GEN3_R, 25 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 26 CLK_TYPE_GEN3_Z, 27 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 28 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 29 CLK_TYPE_GEN3_RPCSRC, 30 CLK_TYPE_GEN3_D3_RPCSRC, 31 CLK_TYPE_GEN3_E3_RPCSRC, 32 CLK_TYPE_GEN3_RPC, 33 CLK_TYPE_GEN3_RPCD2, 34 35 CLK_TYPE_GEN4_MAIN, 36 CLK_TYPE_GEN4_PLL1, 37 CLK_TYPE_GEN4_PLL2, 38 CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */ 39 CLK_TYPE_GEN4_PLL3, 40 CLK_TYPE_GEN4_PLL5, 41 CLK_TYPE_GEN4_PLL4, 42 CLK_TYPE_GEN4_PLL6, 43 CLK_TYPE_GEN4_SDSRC, 44 CLK_TYPE_GEN4_SDH, 45 CLK_TYPE_GEN4_SD, 46 CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ 47 CLK_TYPE_GEN4_Z, 48 CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ 49 CLK_TYPE_GEN4_RPCSRC, 50 CLK_TYPE_GEN4_RPC, 51 CLK_TYPE_GEN4_RPCD2, 52 53 /* SoC specific definitions start here */ 54 CLK_TYPE_GEN3_SOC_BASE, 55 }; 56 57 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ 58 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) 59 60 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 61 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 62 63 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 64 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 65 (_parent0) << 16 | (_parent1), \ 66 .div = (_div0) << 16 | (_div1), .offset = _md) 67 68 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 69 _div_clean) \ 70 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 71 _parent_clean, _div_clean) 72 73 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 74 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 75 76 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 77 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 78 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 79 80 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ 81 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 82 83 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ 84 DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \ 85 (_parent0) << 16 | (_parent1), .div = 5) 86 87 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ 88 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ 89 (_parent0) << 16 | (_parent1), .div = 8) 90 91 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ 92 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset) 93 94 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ 95 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) 96 97 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 98 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ 99 (_parent0) << 16 | (_parent1), \ 100 .div = (_div0) << 16 | (_div1), .offset = _md) 101 102 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ 103 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) 104 105 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ 106 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 107 108 struct rcar_gen3_cpg_pll_config { 109 u8 extal_div; 110 u8 pll1_mult; 111 u8 pll1_div; 112 u8 pll3_mult; 113 u8 pll3_div; 114 u8 osc_prediv; 115 }; 116 117 struct rcar_gen4_cpg_pll_config { 118 u8 extal_div; 119 u8 pll1_mult; 120 u8 pll1_div; 121 u8 pll2_mult; 122 u8 pll2_div; 123 u8 pll3_mult; 124 u8 pll3_div; 125 u8 pll4_mult; 126 u8 pll4_div; 127 u8 pll5_mult; 128 u8 pll5_div; 129 u8 pll6_mult; 130 u8 pll6_div; 131 u8 osc_prediv; 132 }; 133 134 #define CPG_RST_MODEMR 0x060 135 #define CPG_RST_MODEMR0 0x000 136 137 #define CPG_SDCKCR_STPnHCK BIT(9) 138 #define CPG_SDCKCR_STPnCK BIT(8) 139 #define CPG_SDCKCR_SRCFC_MASK GENMASK(4, 2) 140 #define CPG_SDCKCR_FC_MASK GENMASK(1, 0) 141 /* V3M specifics */ 142 #define CPG_SDCKCR_SDHFC_MASK GENMASK(11, 8) 143 #define CPG_SDCKCR_SD0FC_MASK GENMASK(7, 4) 144 145 #define CPG_RPCCKCR 0x238 146 #define CPG_RPCCKCR_DIV_POST_MASK GENMASK(4, 3) 147 #define CPG_RPCCKCR_DIV_PRE_MASK GENMASK(2, 0) 148 149 #define CPG_RCKCR 0x240 150 151 struct gen3_clk_priv { 152 void __iomem *base; 153 struct cpg_mssr_info *info; 154 struct clk clk_extal; 155 struct clk clk_extalr; 156 u32 cpg_mode; 157 union { 158 const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config; 159 const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config; 160 }; 161 }; 162 163 int gen3_cpg_bind(struct udevice *parent); 164 165 extern const struct clk_ops gen3_clk_ops; 166 167 #endif 168