| /qemu/include/qemu/ |
| A D | log.h | 53 #define qemu_log_mask(MASK, FMT, ...) \ argument
67 #define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ argument
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| /qemu/target/arm/tcg/ |
| A D | iwmmxt_helper.c | 299 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
305 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
312 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
318 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
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| A D | sve_helper.c | 3619 #define DO_CMP_PPZZ(NAME, TYPE, OP, H, MASK) \ argument
3687 #define DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H, MASK) \ argument
3764 #define DO_CMP_PPZI(NAME, TYPE, OP, H, MASK) \ argument
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| /qemu/target/hexagon/mmvec/ |
| A D | macros.h | 48 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
68 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
94 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
108 #define fV_AL_CHECK(EA, MASK) \ argument
293 #define fSTOREMMVQ(EA, SRC, MASK) \ argument
297 #define fSTOREMMVNQ(EA, SRC, MASK) \ argument
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| /qemu/target/loongarch/tcg/ |
| A D | vec_helper.c | 2327 #define VFRSTP(NAME, BIT, MASK, E) \ argument
3166 #define XVINSVE0(NAME, E, MASK) \ argument
3177 #define XVPICKVE(NAME, E, BIT, MASK) \ argument
3475 #define VEXTRINS(NAME, BIT, E, MASK) \ argument
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| /qemu/hw/scsi/ |
| A D | vmw_pvscsi.h | 30 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
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| /qemu/tests/qtest/libqos/ |
| A D | ahci.c | 1261 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) in ahci_command_wait() argument
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| /qemu/tcg/ |
| A D | tcg.c | 3053 #define CONST(CASE, MASK) \ in process_op_defs() argument
3055 #define REGS(CASE, MASK) \ in process_op_defs() argument
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| /qemu/target/riscv/ |
| A D | vector_helper.c | 1292 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ argument
1339 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ argument
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