| /qemu/tests/tcg/loongarch64/ |
| A D | test_bit.c | 5 #define TEST_CLO(N) \ argument
17 #define TEST_CLZ(N) \ argument
29 #define TEST_CTO(N) \ argument
41 #define TEST_CTZ(N) \ argument
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| A D | test_div.c | 5 #define TEST_DIV(N, M) \ argument
19 #define TEST_MOD(N, M) \ argument
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| A D | test_fpcom.c | 3 #define TEST_COMP(N) \ argument
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| A D | test_pcadd.c | 5 #define TEST_PCADDU(N) \ argument
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| A D | test_fclass.c | 15 #define TEST_FCLASS(N) \ argument
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| /qemu/target/loongarch/ |
| A D | vec.h | 45 #define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M) argument
47 #define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\ argument
49 #define DO_REM(N, M) (unlikely(M == 0) ? 0 :\ argument
56 #define DO_CLO_B(N) (clz32(~N & 0xff) - 24) argument
57 #define DO_CLO_H(N) (clz32(~N & 0xffff) - 16) argument
58 #define DO_CLO_W(N) (clz32(~N)) argument
59 #define DO_CLO_D(N) (clz64(~N)) argument
60 #define DO_CLZ_B(N) (clz32(N) - 24) argument
61 #define DO_CLZ_H(N) (clz32(N) - 16) argument
62 #define DO_CLZ_W(N) (clz32(N)) argument
[all …]
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| A D | cpu-csr.h | 133 #define LOONGARCH_CSR_SAVE(N) (0x30 + N) argument
190 #define LOONGARCH_CSR_DMW(N) (0x180 + N) argument
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| /qemu/target/arm/tcg/ |
| A D | mve_helper.c | 821 #define DO_NOT(N) (~(N)) argument
837 #define DO_NEG(N) (-(N)) argument
865 #define DO_MOVI(N, I) (I) argument
962 #define DO_ADD(N, M) ((N) + (M)) argument
963 #define DO_SUB(N, M) ((N) - (M)) argument
964 #define DO_MUL(N, M) ((N) * (M)) argument
2665 #define DO_LT(N, M) ((N) < (M)) argument
2666 #define DO_GT(N, M) ((N) > (M)) argument
2752 #define DO_VQABS_B(N, SATP) \ argument
2754 #define DO_VQABS_H(N, SATP) \ argument
[all …]
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| A D | sve_helper.c | 198 #define DO_AND(N, M) (N & M) argument
199 #define DO_EOR(N, M) (N ^ M) argument
200 #define DO_ORR(N, M) (N | M) argument
201 #define DO_BIC(N, M) (N & ~M) argument
202 #define DO_ADD(N, M) (N + M) argument
203 #define DO_SUB(N, M) (N - M) argument
207 #define DO_MUL(N, M) (N * M) argument
866 #define DO_CNOT(N) (N == 0) argument
885 #define DO_NOT(N) (~N) argument
920 #define DO_NEG(N) (-N) argument
[all …]
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| /qemu/tests/tcg/alpha/ |
| A D | test-cond.c | 5 #define TEST_COND(N) \ argument
17 #define TEST_COND(N) \ argument
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| /qemu/target/hexagon/ |
| A D | macros.h | 253 #define fVSATUVALN(N, VAL) \ argument
257 #define fSATUVALN(N, VAL) \ argument
262 #define fSATVALN(N, VAL) \ argument
267 #define fVSATVALN(N, VAL) \ argument
273 #define fSATN(N, VAL) \ argument
275 #define fVSATN(N, VAL) \ argument
299 #define fVSATUN(N, VAL) \ argument
301 #define fSATUN(N, VAL) \ argument
595 #define fGETWORD(N, SRC) \ argument
597 #define fGETUWORD(N, SRC) \ argument
[all …]
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| A D | genptr.c | 285 TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) in gen_get_byte()
295 TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign) in gen_get_byte_i64()
308 TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign) in gen_get_half()
318 void gen_set_half(int N, TCGv result, TCGv src) in gen_set_half()
323 void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) in gen_set_half_i64()
330 void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) in gen_set_byte_i64()
573 static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV) in gen_ploopNsr()
583 static void gen_ploopNsi(DisasContext *ctx, int N, int count, int riV) in gen_ploopNsi()
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| A D | decode.c | 27 #define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) argument
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| /qemu/linux-user/ |
| A D | gen-vdso.c | 40 #define N 32 macro
48 #define N 64 macro
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| /qemu/common-user/host/sparc64/ |
| A D | safe-syscall.inc.S | 28 #define PARAM(N) STACK_BIAS + WINDOW_SIZE + N * 8 argument
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| /qemu/tests/tcg/aarch64/ |
| A D | sve-str.c | 4 #define N (256 + 16) macro
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| /qemu/target/riscv/ |
| A D | vector_helper.c | 751 #define DO_SWAP(N, M) (M) in GEN_VEXT_LDFF() argument
752 #define DO_AND(N, M) (N & M) in GEN_VEXT_LDFF() argument
753 #define DO_XOR(N, M) (N ^ M) in GEN_VEXT_LDFF() argument
754 #define DO_OR(N, M) (N | M) in GEN_VEXT_LDFF() argument
755 #define DO_ADD(N, M) (N + M) in GEN_VEXT_LDFF() argument
881 #define DO_SUB(N, M) (N - M) argument
882 #define DO_RSUB(N, M) (M - N) argument
1400 #define DO_MSEQ(N, M) (N == M) argument
1402 #define DO_MSLT(N, M) (N < M) argument
1404 #define DO_MSGT(N, M) (N > M) argument
[all …]
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| /qemu/linux-user/aarch64/ |
| A D | signal.c | 97 #define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \ argument
99 #define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \ argument
119 #define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ argument
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| /qemu/include/tcg/ |
| A D | tcg-op.h | 105 #define DEF_ATOMIC2(N, S) \ argument
110 #define DEF_ATOMIC3(N, S) \ argument
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| /qemu/target/s390x/tcg/ |
| A D | translate.c | 909 #define F0(N) FMT_##N, argument
910 #define F1(N, X1) F0(N) argument
911 #define F2(N, X1, X2) F0(N) argument
912 #define F3(N, X1, X2, X3) F0(N) argument
913 #define F4(N, X1, X2, X3, X4) F0(N) argument
914 #define F5(N, X1, X2, X3, X4, X5) F0(N) argument
915 #define F6(N, X1, X2, X3, X4, X5, X6) F0(N) argument
974 #define F0(N) { { } }, argument
975 #define F1(N, X1) { { X1 } }, argument
976 #define F2(N, X1, X2) { { X1, X2 } }, argument
[all …]
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| /qemu/tests/unit/ |
| A D | test-qht.c | 11 #define N 5000 macro
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| /qemu/hw/display/ |
| A D | exynos4210_fimd.c | 377 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ argument
400 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ argument
420 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ argument
782 #define DEF_DRAW_LINE_PALETTE(N) \ argument
811 #define DEF_DRAW_LINE_NOPALETTE(N) \ argument
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| /qemu/hw/misc/ |
| A D | tz-ppc.c | 304 #define DEFINE_PORT(N) \ argument
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| /qemu/target/mips/tcg/sysemu/ |
| A D | mips-semi.c | 131 #define E(N) case E##N: err = UHI_E##N; break in uhi_cb() argument
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| /qemu/target/mips/tcg/ |
| A D | lmmi_helper.c | 41 # define BYTE_ORDER_XOR(N) N argument
43 # define BYTE_ORDER_XOR(N) 0 argument
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