1menu "RISC-V architecture"
2	depends on RISCV
3
4config SYS_ARCH
5	default "riscv"
6
7choice
8	prompt "Target select"
9	optional
10
11config TARGET_AE350
12	bool "Support ae350"
13
14config TARGET_MICROCHIP_ICICLE
15	bool "Support Microchip PolarFire-SoC Icicle Board"
16
17config TARGET_QEMU_VIRT
18	bool "Support QEMU Virt Board"
19
20config TARGET_SIFIVE_UNLEASHED
21	bool "Support SiFive Unleashed Board"
22
23config TARGET_SIFIVE_UNMATCHED
24	bool "Support SiFive Unmatched Board"
25	select SYS_CACHE_SHIFT_6
26
27config TARGET_STARFIVE_VISIONFIVE2
28	bool "Support StarFive VisionFive2 Board"
29
30config TARGET_SIPEED_MAIX
31	bool "Support Sipeed Maix Board"
32	select SYS_CACHE_SHIFT_6
33
34config TARGET_OPENPITON_RISCV64
35	bool "Support RISC-V cores on OpenPiton SoC"
36
37endchoice
38
39config SYS_ICACHE_OFF
40	bool "Do not enable icache"
41	help
42	  Do not enable instruction cache in U-Boot.
43
44config SPL_SYS_ICACHE_OFF
45	bool "Do not enable icache in SPL"
46	depends on SPL
47	default SYS_ICACHE_OFF
48	help
49	  Do not enable instruction cache in SPL.
50
51config SYS_DCACHE_OFF
52	bool "Do not enable dcache"
53	help
54	  Do not enable data cache in U-Boot.
55
56config SPL_SYS_DCACHE_OFF
57	bool "Do not enable dcache in SPL"
58	depends on SPL
59	default SYS_DCACHE_OFF
60	help
61	  Do not enable data cache in SPL.
62
63# board-specific options below
64source "board/AndesTech/ae350/Kconfig"
65source "board/emulation/qemu-riscv/Kconfig"
66source "board/microchip/mpfs_icicle/Kconfig"
67source "board/sifive/unleashed/Kconfig"
68source "board/sifive/unmatched/Kconfig"
69source "board/openpiton/riscv64/Kconfig"
70source "board/sipeed/maix/Kconfig"
71source "board/starfive/visionfive2/Kconfig"
72
73# platform-specific options below
74source "arch/riscv/cpu/andesv5/Kconfig"
75source "arch/riscv/cpu/fu540/Kconfig"
76source "arch/riscv/cpu/fu740/Kconfig"
77source "arch/riscv/cpu/generic/Kconfig"
78source "arch/riscv/cpu/jh7110/Kconfig"
79
80# architecture-specific options below
81
82choice
83	prompt "Base ISA"
84	default ARCH_RV32I
85
86config ARCH_RV32I
87	bool "RV32I"
88	select 32BIT
89	help
90	  Choose this option to target the RV32I base integer instruction set.
91
92config ARCH_RV64I
93	bool "RV64I"
94	select 64BIT
95	select PHYS_64BIT
96	help
97	  Choose this option to target the RV64I base integer instruction set.
98
99endchoice
100
101choice
102	prompt "Code Model"
103	default CMODEL_MEDLOW
104
105config CMODEL_MEDLOW
106	bool "medium low code model"
107	help
108	  U-Boot and its statically defined symbols must lie within a single 2 GiB
109	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
110
111config CMODEL_MEDANY
112	bool "medium any code model"
113	help
114	  U-Boot and its statically defined symbols must be within any single 2 GiB
115	  address range.
116
117endchoice
118
119choice
120	prompt "Run Mode"
121	default RISCV_MMODE
122
123config RISCV_MMODE
124	bool "Machine"
125	help
126	  Choose this option to build U-Boot for RISC-V M-Mode.
127
128config RISCV_SMODE
129	bool "Supervisor"
130	help
131	  Choose this option to build U-Boot for RISC-V S-Mode.
132
133endchoice
134
135choice
136	prompt "SPL Run Mode"
137	default SPL_RISCV_MMODE
138	depends on SPL
139
140config SPL_RISCV_MMODE
141	bool "Machine"
142	help
143	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
144
145config SPL_RISCV_SMODE
146	bool "Supervisor"
147	help
148	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
149
150endchoice
151
152config RISCV_ISA_C
153	bool "Emit compressed instructions"
154	default y
155	help
156	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
157	  when building U-Boot, which results in compressed instructions in the
158	  U-Boot binary.
159
160config RISCV_ISA_F
161	bool "Standard extension for Single-Precision Floating Point"
162	default y
163	help
164	  Adds "F" to the ISA string passed to the compiler.
165
166config RISCV_ISA_D
167	bool "Standard extension for Double-Precision Floating Point"
168	depends on RISCV_ISA_F
169	default y
170	help
171	  Adds "D" to the ISA string passed to the compiler and changes the
172	  riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
173	  lp64d.
174
175config RISCV_ISA_A
176	def_bool y
177
178config 32BIT
179	bool
180
181config 64BIT
182	bool
183
184config DMA_ADDR_T_64BIT
185	bool
186	default y if 64BIT
187
188config SIFIVE_CLINT
189	bool
190	depends on RISCV_MMODE
191	help
192	  The SiFive CLINT block holds memory-mapped control and status registers
193	  associated with software and timer interrupts.
194
195config SPL_SIFIVE_CLINT
196	bool
197	depends on SPL_RISCV_MMODE
198	help
199	  The SiFive CLINT block holds memory-mapped control and status registers
200	  associated with software and timer interrupts.
201
202config SIFIVE_CACHE
203	bool
204	help
205	  This enables the operations to configure SiFive cache
206
207config ANDES_PLICSW
208	bool
209	depends on RISCV_MMODE || SPL_RISCV_MMODE
210	select REGMAP
211	select SYSCON
212	select SPL_REGMAP if SPL
213	select SPL_SYSCON if SPL
214	help
215	  The Andes PLICSW block holds memory-mapped claim and pending
216	  registers associated with software interrupt.
217
218config SMP
219	bool "Symmetric Multi-Processing"
220	depends on SBI_V01 || !RISCV_SMODE
221	help
222	  This enables support for systems with more than one CPU. If
223	  you say N here, U-Boot will run on single and multiprocessor
224	  machines, but will use only one CPU of a multiprocessor
225	  machine. If you say Y here, U-Boot will run on many, but not
226	  all, single processor machines.
227
228config SPL_SMP
229	bool "Symmetric Multi-Processing in SPL"
230	depends on SPL && SPL_RISCV_MMODE
231	default y
232	help
233	  This enables support for systems with more than one CPU in SPL.
234	  If you say N here, U-Boot SPL will run on single and multiprocessor
235	  machines, but will use only one CPU of a multiprocessor
236	  machine. If you say Y here, U-Boot SPL will run on many, but not
237	  all, single processor machines.
238
239config NR_CPUS
240	int "Maximum number of CPUs (2-32)"
241	range 2 32
242	depends on SMP || SPL_SMP
243	default 8
244	help
245	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
246	  Stack memory is pre-allocated. U-Boot must therefore know the
247	  maximum number of CPUs that may be present.
248
249config SBI
250	bool
251	default y if RISCV_SMODE || SPL_RISCV_SMODE
252
253choice
254	prompt "SBI support"
255	default SBI_V02
256
257config SBI_V01
258	bool "SBI v0.1 support"
259	depends on SBI
260	help
261	  This config allows kernel to use SBI v0.1 APIs. This will be
262	  deprecated in future once legacy M-mode software are no longer in use.
263
264config SBI_V02
265	bool "SBI v0.2 or later support"
266	depends on SBI
267	help
268	  The SBI specification introduced the concept of extensions in version
269	  v0.2. With this configuration option U-Boot can detect and use SBI
270	  extensions. With the HSM extension introduced in SBI 0.2, only a
271	  single hart needs to boot and enter the operating system. The booting
272	  hart can bring up secondary harts one by one afterwards.
273
274	  Choose this option if OpenSBI release v0.7 or above is used together
275	  with U-Boot.
276
277endchoice
278
279config SBI_IPI
280	bool
281	depends on SBI
282	default y if RISCV_SMODE || SPL_RISCV_SMODE
283	depends on SMP
284
285config XIP
286	bool "XIP mode"
287	help
288	  XIP (eXecute In Place) is a method for executing code directly
289	  from a NOR flash memory without copying the code to ram.
290	  Say yes here if U-Boot boots from flash directly.
291
292config SPL_XIP
293	bool "Enable XIP mode for SPL"
294	help
295	  If SPL starts in read-only memory (XIP for example) then we shouldn't
296	  rely on lock variables (for example hart_lottery and available_harts_lock),
297	  this affects only SPL, other stages should proceed as non-XIP.
298
299config AVAILABLE_HARTS
300	bool "Send IPI by available harts"
301	default y
302	help
303	  By default, IPI sending mechanism will depend on available_harts.
304	  If disable this, it will send IPI by CPUs node numbers of device tree.
305
306config SHOW_REGS
307	bool "Show registers on unhandled exception"
308
309config RISCV_PRIV_1_9
310	bool "Use version 1.9 of the RISC-V priviledged specification"
311	help
312	  Older versions of the RISC-V priviledged specification had
313	  separate counter enable CSRs for each privilege mode. Writing
314	  to the unified mcounteren CSR on a processor implementing the
315	  old specification will result in an illegal instruction
316	  exception. In addition to counter CSR changes, the way virtual
317	  memory is configured was also changed.
318
319config STACK_SIZE_SHIFT
320	int
321	default 14
322
323config OF_BOARD_FIXUP
324	default y if OF_SEPARATE && RISCV_SMODE
325
326menu "Use assembly optimized implementation of memory routines"
327
328config USE_ARCH_MEMCPY
329	bool "Use an assembly optimized implementation of memcpy"
330	default y
331	help
332	  Enable the generation of an optimized version of memcpy.
333	  Such an implementation may be faster under some conditions
334	  but may increase the binary size.
335
336config SPL_USE_ARCH_MEMCPY
337	bool "Use an assembly optimized implementation of memcpy for SPL"
338	default y if USE_ARCH_MEMCPY
339	depends on SPL
340	help
341	  Enable the generation of an optimized version of memcpy.
342	  Such an implementation may be faster under some conditions
343	  but may increase the binary size.
344
345config TPL_USE_ARCH_MEMCPY
346	bool "Use an assembly optimized implementation of memcpy for TPL"
347	default y if USE_ARCH_MEMCPY
348	depends on TPL
349	help
350	  Enable the generation of an optimized version of memcpy.
351	  Such an implementation may be faster under some conditions
352	  but may increase the binary size.
353
354config USE_ARCH_MEMMOVE
355	bool "Use an assembly optimized implementation of memmove"
356	default y
357	help
358	  Enable the generation of an optimized version of memmove.
359	  Such an implementation may be faster under some conditions
360	  but may increase the binary size.
361
362config SPL_USE_ARCH_MEMMOVE
363	bool "Use an assembly optimized implementation of memmove for SPL"
364	default y if USE_ARCH_MEMCPY
365	depends on SPL
366	help
367	  Enable the generation of an optimized version of memmove.
368	  Such an implementation may be faster under some conditions
369	  but may increase the binary size.
370
371config TPL_USE_ARCH_MEMMOVE
372	bool "Use an assembly optimized implementation of memmove for TPL"
373	default y if USE_ARCH_MEMCPY
374	depends on TPL
375	help
376	  Enable the generation of an optimized version of memmove.
377	  Such an implementation may be faster under some conditions
378	  but may increase the binary size.
379
380config USE_ARCH_MEMSET
381	bool "Use an assembly optimized implementation of memset"
382	default y
383	help
384	  Enable the generation of an optimized version of memset.
385	  Such an implementation may be faster under some conditions
386	  but may increase the binary size.
387
388config SPL_USE_ARCH_MEMSET
389	bool "Use an assembly optimized implementation of memset for SPL"
390	default y if USE_ARCH_MEMSET
391	depends on SPL
392	help
393	  Enable the generation of an optimized version of memset.
394	  Such an implementation may be faster under some conditions
395	  but may increase the binary size.
396
397config TPL_USE_ARCH_MEMSET
398	bool "Use an assembly optimized implementation of memset for TPL"
399	default y if USE_ARCH_MEMSET
400	depends on TPL
401	help
402	  Enable the generation of an optimized version of memset.
403	  Such an implementation may be faster under some conditions
404	  but may increase the binary size.
405
406endmenu
407
408endmenu
409