1 /****************************************************************************** 2 * config.h 3 * 4 * A Linux-style configuration list. 5 */ 6 7 #ifndef __X86_CONFIG_H__ 8 #define __X86_CONFIG_H__ 9 10 #define LONG_BYTEORDER 3 11 #define CONFIG_PAGING_LEVELS 4 12 13 #define BYTES_PER_LONG (1 << LONG_BYTEORDER) 14 #define BITS_PER_LONG (BYTES_PER_LONG << 3) 15 #define BITS_PER_BYTE 8 16 #define POINTER_ALIGN BYTES_PER_LONG 17 18 #define BITS_PER_LLONG 64 19 20 #define BITS_PER_XEN_ULONG BITS_PER_LONG 21 22 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1 23 #define CONFIG_NUMA_EMU 1 24 25 #define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER) 26 #define CONFIG_DOMU_MAX_ORDER PAGETABLE_ORDER 27 #define CONFIG_HWDOM_MAX_ORDER 12 28 29 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */ 30 #define CONFIG_X86_L1_CACHE_SHIFT 7 31 32 #define CONFIG_ACPI_CSTATE 1 33 34 #define CONFIG_WATCHDOG 1 35 36 #define CONFIG_MULTIBOOT 1 37 38 #define HZ 100 39 40 #define OPT_CONSOLE_STR "vga" 41 42 /* Linkage for x86 */ 43 #ifdef __ASSEMBLY__ 44 #define CODE_FILL 0x90 45 #define ALIGN .align CONFIG_FUNCTION_ALIGNMENT, CODE_FILL 46 #define ENTRY(name) \ 47 ALIGN; \ 48 GLOBAL(name) 49 #define GLOBAL(name) \ 50 .globl name; \ 51 .hidden name; \ 52 name: 53 #endif 54 55 #define NR_hypercalls 64 56 57 #define STACK_ORDER 3 58 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) 59 60 #define IST_SHSTK_SIZE 1024 61 62 #define TRAMPOLINE_STACK_SPACE PAGE_SIZE 63 #define TRAMPOLINE_SPACE (KB(64) - TRAMPOLINE_STACK_SPACE) 64 #define WAKEUP_STACK_MIN 3072 65 66 #define MBI_SPACE_MIN (2 * PAGE_SIZE) 67 68 /* Primary stack is restricted to 8kB by guard pages. */ 69 #define PRIMARY_STACK_SIZE 8192 70 71 /* Primary shadow stack is slot 5 of 8, immediately under the primary stack. */ 72 #define PRIMARY_SHSTK_SLOT 5 73 74 /* Total size of syscall and emulation stubs. */ 75 #define STUB_BUF_SHIFT (L1_CACHE_SHIFT > 7 ? L1_CACHE_SHIFT : 7) 76 #define STUB_BUF_SIZE (1 << STUB_BUF_SHIFT) 77 #define STUBS_PER_PAGE (PAGE_SIZE / STUB_BUF_SIZE) 78 79 /* Return value for zero-size _xmalloc(), distinguished from NULL. */ 80 #define ZERO_BLOCK_PTR ((void *)0xBAD0BAD0BAD0BAD0UL) 81 82 /* Override include/xen/list.h to make these non-canonical addresses. */ 83 #define LIST_POISON1 ((void *)0x0100100100100100UL) 84 #define LIST_POISON2 ((void *)0x0200200200200200UL) 85 86 #ifndef __ASSEMBLY__ 87 extern unsigned long trampoline_phys; 88 #define bootsym_phys(sym) \ 89 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+trampoline_phys) 90 #define bootsym(sym) \ 91 (*((typeof(sym) *)__va(bootsym_phys(sym)))) 92 93 extern char trampoline_start[], trampoline_end[]; 94 extern char trampoline_realmode_entry[]; 95 extern unsigned int trampoline_xen_phys_start; 96 extern unsigned char trampoline_cpu_started; 97 extern char wakeup_start[]; 98 99 extern unsigned char video_flags; 100 101 extern unsigned short boot_edid_caps; 102 extern unsigned char boot_edid_info[128]; 103 #endif 104 105 #include <xen/const.h> 106 107 #define PML4_ENTRY_BITS 39 108 #define PML4_ENTRY_BYTES (_AC(1,UL) << PML4_ENTRY_BITS) 109 #define PML4_ADDR(_slot) \ 110 (((_AC(_slot, UL) >> 8) * _AC(0xffff000000000000,UL)) | \ 111 (_AC(_slot, UL) << PML4_ENTRY_BITS)) 112 113 /* 114 * Memory layout: 115 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255] 116 * Guest-defined use (see below for compatibility mode guests). 117 * 0x0000800000000000 - 0xffff7fffffffffff [16EB] 118 * Inaccessible: current arch only supports 48-bit sign-extended VAs. 119 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256] 120 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 121 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256] 122 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE). 123 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257] 124 * ioremap for PCI mmconfig space 125 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258] 126 * Guest linear page table. 127 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259] 128 * Shadow linear page table. 129 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260] 130 * Per-domain mappings (e.g., GDT, LDT). 131 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261] 132 * Machine-to-phys translation table. 133 * 0xffff82c000000000 - 0xffff82cfffffffff [64GB, 2^36 bytes, PML4:261] 134 * vmap()/ioremap()/fixmap area. 135 * 0xffff82d000000000 - 0xffff82d03fffffff [1GB, 2^30 bytes, PML4:261] 136 * Compatibility machine-to-phys translation table (CONFIG_PV32). 137 * 0xffff82d040000000 - 0xffff82d07fffffff [1GB, 2^30 bytes, PML4:261] 138 * Xen text, static data, bss. 139 #ifndef CONFIG_BIGMEM 140 * 0xffff82d080000000 - 0xffff82dfffffffff [62GB, PML4:261] 141 * Reserved for future use. 142 * 0xffff82e000000000 - 0xffff82ffffffffff [128GB, 2^37 bytes, PML4:261] 143 * Page-frame information array. 144 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271] 145 * 1:1 direct mapping of all physical memory. 146 #else 147 * 0xffff82d080000000 - 0xffff82ffffffffff [190GB, PML4:261] 148 * Reserved for future use. 149 * 0xffff830000000000 - 0xffff847fffffffff [1.5TB, 3*2^39 bytes, PML4:262-264] 150 * Page-frame information array. 151 * 0xffff848000000000 - 0xffff87ffffffffff [3.5TB, 7*2^39 bytes, PML4:265-271] 152 * 1:1 direct mapping of all physical memory. 153 #endif 154 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511] 155 * PV: Guest-defined use. 156 * 0xffff880000000000 - 0xffffff7fffffffff [119.5TB, PML4:272-510] 157 * HVM/idle: continuation of 1:1 mapping 158 * 0xffffff8000000000 - 0xffffffffffffffff [512GB, 2^39 bytes PML4:511] 159 * HVM/idle: unused 160 * 161 * Compatibility guest area layout: 162 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0] 163 * Guest-defined use. 164 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0] 165 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 166 * 0x0000000100000000 - 0x000001ffffffffff [2TB-4GB, PML4:0-3] 167 * Unused / Reserved for future use. 168 * 0x0000020000000000 - 0x0000027fffffffff [512GB, 2^39 bytes, PML4:4] 169 * Mirror of per-domain mappings (for argument translation area; also HVM). 170 * 0x0000028000000000 - 0x00007fffffffffff [125.5TB, PML4:5-255] 171 * Unused / Reserved for future use. 172 */ 173 174 175 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256 176 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271 177 #define ROOT_PAGETABLE_XEN_SLOTS \ 178 (L4_PAGETABLE_ENTRIES - ROOT_PAGETABLE_FIRST_XEN_SLOT - 1) 179 #define ROOT_PAGETABLE_PV_XEN_SLOTS \ 180 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1) 181 182 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */ 183 #define HYPERVISOR_VIRT_START (PML4_ADDR(256)) 184 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16) 185 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */ 186 #define RO_MPT_VIRT_START (PML4_ADDR(256)) 187 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2) 188 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE) 189 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB) 190 * - full 16-bit segment support needs 44 bits 191 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits) 192 */ 193 #define PCI_MCFG_VIRT_START (PML4_ADDR(257)) 194 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES) 195 /* Slot 258: linear page table (guest table). */ 196 #define LINEAR_PT_VIRT_START (PML4_ADDR(258)) 197 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 198 /* Slot 259: linear page table (shadow table). */ 199 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259)) 200 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 201 /* Slot 260: per-domain mappings (including map cache). */ 202 #define PERDOMAIN_VIRT_START (PML4_ADDR(260)) 203 #define PERDOMAIN_SLOT_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER)) 204 #define PERDOMAIN_SLOTS 3 205 #define PERDOMAIN_VIRT_SLOT(s) (PERDOMAIN_VIRT_START + (s) * \ 206 (PERDOMAIN_SLOT_MBYTES << 20)) 207 /* Slot 4: mirror of per-domain mappings (for compat xlat area accesses). */ 208 #define PERDOMAIN_ALT_VIRT_START PML4_ADDR(4) 209 /* Slot 261: machine-to-phys conversion table (256GB). */ 210 #define RDWR_MPT_VIRT_START (PML4_ADDR(261)) 211 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE) 212 /* Slot 261: vmap()/ioremap()/fixmap area (64GB). */ 213 #define VMAP_VIRT_START RDWR_MPT_VIRT_END 214 #define VMAP_VIRT_END (VMAP_VIRT_START + GB(64)) 215 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */ 216 #define RDWR_COMPAT_MPT_VIRT_START VMAP_VIRT_END 217 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1)) 218 /* Slot 261: xen text, static data, bss, per-cpu stubs and executable fixmap (1GB). */ 219 #define XEN_VIRT_START RDWR_COMPAT_MPT_VIRT_END 220 #define XEN_VIRT_END (XEN_VIRT_START + GB(1)) 221 222 #ifndef CONFIG_BIGMEM 223 /* Slot 261: page-frame information array (128GB). */ 224 #define FRAMETABLE_SIZE GB(128) 225 #else 226 /* Slot 262-264: page-frame information array (1.5TB). */ 227 #define FRAMETABLE_SIZE GB(1536) 228 #endif 229 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START 230 #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) 231 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE) 232 233 #ifndef CONFIG_BIGMEM 234 /* Slot 262-271/510: A direct 1:1 mapping of all of physical memory. */ 235 #define DIRECTMAP_VIRT_START (PML4_ADDR(262)) 236 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 262)) 237 #else 238 /* Slot 265-271/510: A direct 1:1 mapping of all of physical memory. */ 239 #define DIRECTMAP_VIRT_START (PML4_ADDR(265)) 240 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 265)) 241 #endif 242 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE) 243 244 #ifndef __ASSEMBLY__ 245 246 #ifdef CONFIG_PV32 247 248 /* This is not a fixed value, just a lower limit. */ 249 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000 250 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart) 251 252 #else /* !CONFIG_PV32 */ 253 254 #define HYPERVISOR_COMPAT_VIRT_START(d) ((void)(d), 0) 255 256 #endif /* CONFIG_PV32 */ 257 258 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START 259 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U 260 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ 261 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) 262 263 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \ 264 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d)) 265 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U) 266 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \ 267 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1) 268 269 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS 270 #define COMPAT_HAVE_PV_GUEST_ENTRY XEN_HAVE_PV_GUEST_ENTRY 271 #define COMPAT_HAVE_PV_UPCALL_MASK XEN_HAVE_PV_UPCALL_MASK 272 273 #endif 274 275 #define __HYPERVISOR_CS 0xe008 276 #define __HYPERVISOR_DS64 0x0000 277 #define __HYPERVISOR_DS32 0xe010 278 #define __HYPERVISOR_DS __HYPERVISOR_DS64 279 280 #define SYMBOLS_ORIGIN XEN_VIRT_START 281 282 /* For generic assembly code: use macros to define operation/operand sizes. */ 283 #define __OS "q" /* Operation Suffix */ 284 #define __OP "r" /* Operand Prefix */ 285 286 #ifndef __ASSEMBLY__ 287 extern unsigned long xen_phys_start; 288 #endif 289 290 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */ 291 #define GDT_LDT_VCPU_SHIFT 5 292 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT) 293 #define GDT_LDT_MBYTES PERDOMAIN_SLOT_MBYTES 294 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT)) 295 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_SLOT(0) 296 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20)) 297 298 /* The address of a particular VCPU's GDT or LDT. */ 299 #define GDT_VIRT_START(v) \ 300 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT)) 301 #define LDT_VIRT_START(v) \ 302 (GDT_VIRT_START(v) + (64*1024)) 303 304 /* map_domain_page() map cache. The second per-domain-mapping sub-area. */ 305 #define MAPCACHE_VCPU_ENTRIES (CONFIG_PAGING_LEVELS * CONFIG_PAGING_LEVELS) 306 #define MAPCACHE_ENTRIES (MAX_VIRT_CPUS * MAPCACHE_VCPU_ENTRIES) 307 #define MAPCACHE_VIRT_START PERDOMAIN_VIRT_SLOT(1) 308 #define MAPCACHE_VIRT_END (MAPCACHE_VIRT_START + \ 309 MAPCACHE_ENTRIES * PAGE_SIZE) 310 311 /* Argument translation area. The third per-domain-mapping sub-area. */ 312 #define ARG_XLAT_VIRT_START PERDOMAIN_VIRT_SLOT(2) 313 /* Allow for at least one guard page (COMPAT_ARG_XLAT_SIZE being 2 pages): */ 314 #define ARG_XLAT_VA_SHIFT (2 + PAGE_SHIFT) 315 #define ARG_XLAT_START(v) \ 316 (ARG_XLAT_VIRT_START + ((v)->vcpu_id << ARG_XLAT_VA_SHIFT)) 317 318 #define ELFSIZE 64 319 320 #define ARCH_CRASH_SAVE_VMCOREINFO 321 322 #endif /* __X86_CONFIG_H__ */ 323