| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 60 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
72 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ argument
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| /u-boot/drivers/clk/imx/ |
| A D | clk-pll14xx.c | 55 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
63 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
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| /u-boot/drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 50 #define UNIPHIER_CLK_RATE(_id, _rate) \ argument
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| /u-boot/drivers/clk/starfive/ |
| A D | clk-jh7110-pll.c | 52 #define PLLX_RATE(_rate, _pd, _fd) \ argument
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| /u-boot/arch/arm/include/asm/arch-imx9/ |
| A D | clock.h | 185 #define INT_PLL_RATE(_rate, _r, _m, _o) \ argument
193 #define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \ argument
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| /u-boot/drivers/clk/renesas/ |
| A D | renesas-cpg-mssr.h | 92 #define DEF_RATE(_name, _id, _rate) \ argument
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_px30.c | 36 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
48 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
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| A D | clk_rk3308.c | 35 #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
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| A D | clk_rv1126.c | 25 #define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
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| A D | clk_rk3568.c | 33 #define RK3568_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
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| /u-boot/include/ |
| A D | k3-clk.h | 148 #define CLK_FIXED_RATE(_name, _rate, _flags) \ argument
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mtk.h | 69 #define FIXED_CLK(_id, _parent, _rate) { \ argument
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | clock.h | 190 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ argument
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| A D | clock_imx8mm.h | 15 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
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