1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Atmel PIO4 device driver
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
7 */
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <fdtdec.h>
12 #include <malloc.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/global_data.h>
15 #include <asm/gpio.h>
16 #include <linux/bitops.h>
17 #include <mach/gpio.h>
18 #include <mach/atmel_pio4.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
atmel_pio4_port_base(u32 port)22 static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
23 {
24 struct atmel_pio4_port *base = NULL;
25
26 switch (port) {
27 case AT91_PIO_PORTA:
28 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
29 break;
30 case AT91_PIO_PORTB:
31 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
32 break;
33 case AT91_PIO_PORTC:
34 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
35 break;
36 case AT91_PIO_PORTD:
37 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
38 break;
39 #if (ATMEL_PIO_PORTS > 4)
40 case AT91_PIO_PORTE:
41 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE;
42 break;
43 #endif
44 default:
45 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
46 port);
47 break;
48 }
49
50 return base;
51 }
52
atmel_pio4_config_io_func(u32 port,u32 pin,u32 func,u32 config)53 static int atmel_pio4_config_io_func(u32 port, u32 pin,
54 u32 func, u32 config)
55 {
56 struct atmel_pio4_port *port_base;
57 u32 reg, mask;
58
59 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
60 return -EINVAL;
61
62 port_base = atmel_pio4_port_base(port);
63 if (!port_base)
64 return -EINVAL;
65
66 mask = 1 << pin;
67 reg = func;
68 reg |= config;
69
70 writel(mask, &port_base->mskr);
71 writel(reg, &port_base->cfgr);
72
73 return 0;
74 }
75
atmel_pio4_set_gpio(u32 port,u32 pin,u32 config)76 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
77 {
78 return atmel_pio4_config_io_func(port, pin,
79 ATMEL_PIO_CFGR_FUNC_GPIO,
80 config);
81 }
82
atmel_pio4_set_a_periph(u32 port,u32 pin,u32 config)83 int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
84 {
85 return atmel_pio4_config_io_func(port, pin,
86 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
87 config);
88 }
89
atmel_pio4_set_b_periph(u32 port,u32 pin,u32 config)90 int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
91 {
92 return atmel_pio4_config_io_func(port, pin,
93 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
94 config);
95 }
96
atmel_pio4_set_c_periph(u32 port,u32 pin,u32 config)97 int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
98 {
99 return atmel_pio4_config_io_func(port, pin,
100 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
101 config);
102 }
103
atmel_pio4_set_d_periph(u32 port,u32 pin,u32 config)104 int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
105 {
106 return atmel_pio4_config_io_func(port, pin,
107 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
108 config);
109 }
110
atmel_pio4_set_e_periph(u32 port,u32 pin,u32 config)111 int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
112 {
113 return atmel_pio4_config_io_func(port, pin,
114 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
115 config);
116 }
117
atmel_pio4_set_f_periph(u32 port,u32 pin,u32 config)118 int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
119 {
120 return atmel_pio4_config_io_func(port, pin,
121 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
122 config);
123 }
124
atmel_pio4_set_g_periph(u32 port,u32 pin,u32 config)125 int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
126 {
127 return atmel_pio4_config_io_func(port, pin,
128 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
129 config);
130 }
131
atmel_pio4_set_pio_output(u32 port,u32 pin,u32 value)132 int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
133 {
134 struct atmel_pio4_port *port_base;
135 u32 reg, mask;
136
137 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
138 return -EINVAL;
139
140 port_base = atmel_pio4_port_base(port);
141 if (!port_base)
142 return -EINVAL;
143
144 mask = 0x01 << pin;
145 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
146
147 writel(mask, &port_base->mskr);
148 writel(reg, &port_base->cfgr);
149
150 if (value)
151 writel(mask, &port_base->sodr);
152 else
153 writel(mask, &port_base->codr);
154
155 return 0;
156 }
157
atmel_pio4_get_pio_input(u32 port,u32 pin)158 int atmel_pio4_get_pio_input(u32 port, u32 pin)
159 {
160 struct atmel_pio4_port *port_base;
161 u32 reg, mask;
162
163 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
164 return -EINVAL;
165
166 port_base = atmel_pio4_port_base(port);
167 if (!port_base)
168 return -EINVAL;
169
170 mask = 0x01 << pin;
171 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
172
173 writel(mask, &port_base->mskr);
174 writel(reg, &port_base->cfgr);
175
176 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
177 }
178
179 #if CONFIG_IS_ENABLED(DM_GPIO)
180
181 /**
182 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
183 * @nbanks: number of PIO banks
184 * @last_bank_count: number of lines in the last bank (can be less than
185 * the rest of the banks).
186 */
187 struct atmel_pioctrl_data {
188 u32 nbanks;
189 u32 last_bank_count;
190 };
191
192 struct atmel_pio4_plat {
193 struct atmel_pio4_port *reg_base;
194 };
195
atmel_pio4_bank_base(struct udevice * dev,u32 bank)196 static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
197 u32 bank)
198 {
199 struct atmel_pio4_plat *plat = dev_get_plat(dev);
200 struct atmel_pio4_port *port_base =
201 (struct atmel_pio4_port *)((u32)plat->reg_base +
202 ATMEL_PIO_BANK_OFFSET * bank);
203
204 return port_base;
205 }
206
atmel_pio4_direction_input(struct udevice * dev,unsigned offset)207 static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
208 {
209 u32 bank = ATMEL_PIO_BANK(offset);
210 u32 line = ATMEL_PIO_LINE(offset);
211 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
212 u32 mask = BIT(line);
213
214 writel(mask, &port_base->mskr);
215
216 clrbits_le32(&port_base->cfgr,
217 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
218
219 return 0;
220 }
221
atmel_pio4_direction_output(struct udevice * dev,unsigned offset,int value)222 static int atmel_pio4_direction_output(struct udevice *dev,
223 unsigned offset, int value)
224 {
225 u32 bank = ATMEL_PIO_BANK(offset);
226 u32 line = ATMEL_PIO_LINE(offset);
227 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
228 u32 mask = BIT(line);
229
230 writel(mask, &port_base->mskr);
231
232 clrsetbits_le32(&port_base->cfgr,
233 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
234
235 if (value)
236 writel(mask, &port_base->sodr);
237 else
238 writel(mask, &port_base->codr);
239
240 return 0;
241 }
242
atmel_pio4_get_value(struct udevice * dev,unsigned offset)243 static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
244 {
245 u32 bank = ATMEL_PIO_BANK(offset);
246 u32 line = ATMEL_PIO_LINE(offset);
247 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
248 u32 mask = BIT(line);
249
250 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
251 }
252
atmel_pio4_set_value(struct udevice * dev,unsigned offset,int value)253 static int atmel_pio4_set_value(struct udevice *dev,
254 unsigned offset, int value)
255 {
256 u32 bank = ATMEL_PIO_BANK(offset);
257 u32 line = ATMEL_PIO_LINE(offset);
258 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
259 u32 mask = BIT(line);
260
261 if (value)
262 writel(mask, &port_base->sodr);
263 else
264 writel(mask, &port_base->codr);
265
266 return 0;
267 }
268
atmel_pio4_get_function(struct udevice * dev,unsigned offset)269 static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
270 {
271 u32 bank = ATMEL_PIO_BANK(offset);
272 u32 line = ATMEL_PIO_LINE(offset);
273 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
274 u32 mask = BIT(line);
275
276 writel(mask, &port_base->mskr);
277
278 return (readl(&port_base->cfgr) &
279 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
280 }
281
282 static const struct dm_gpio_ops atmel_pio4_ops = {
283 .direction_input = atmel_pio4_direction_input,
284 .direction_output = atmel_pio4_direction_output,
285 .get_value = atmel_pio4_get_value,
286 .set_value = atmel_pio4_set_value,
287 .get_function = atmel_pio4_get_function,
288 };
289
atmel_pio4_bind(struct udevice * dev)290 static int atmel_pio4_bind(struct udevice *dev)
291 {
292 return dm_scan_fdt_dev(dev);
293 }
294
atmel_pio4_probe(struct udevice * dev)295 static int atmel_pio4_probe(struct udevice *dev)
296 {
297 struct atmel_pio4_plat *plat = dev_get_plat(dev);
298 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
299 struct atmel_pioctrl_data *pioctrl_data;
300 struct clk clk;
301 fdt_addr_t addr_base;
302 u32 nbanks;
303 int ret;
304
305 ret = clk_get_by_index(dev, 0, &clk);
306 if (ret)
307 return ret;
308
309 ret = clk_enable(&clk);
310 if (ret)
311 return ret;
312
313 clk_free(&clk);
314
315 addr_base = dev_read_addr(dev);
316 if (addr_base == FDT_ADDR_T_NONE)
317 return -EINVAL;
318
319 plat->reg_base = (struct atmel_pio4_port *)addr_base;
320
321 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
322 nbanks = pioctrl_data->nbanks;
323
324 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
325 NULL);
326 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
327
328 /* if last bank has limited number of pins, adjust accordingly */
329 if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
330 uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
331 uc_priv->gpio_count += pioctrl_data->last_bank_count;
332 }
333
334 return 0;
335 }
336
337 /*
338 * The number of banks can be different from a SoC to another one.
339 * We can have up to 16 banks.
340 */
341 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
342 .nbanks = 4,
343 .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
344 };
345
346 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
347 .nbanks = 5,
348 .last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
349 };
350
351 static const struct udevice_id atmel_pio4_ids[] = {
352 {
353 .data = (ulong)&atmel_sama5d2_pioctrl_data,
354 }, {
355 .data = (ulong)µchip_sama7g5_pioctrl_data,
356 },
357 {}
358 };
359
360 U_BOOT_DRIVER(gpio_atmel_pio4) = {
361 .name = "gpio_atmel_pio4",
362 .id = UCLASS_GPIO,
363 .ops = &atmel_pio4_ops,
364 .probe = atmel_pio4_probe,
365 .bind = atmel_pio4_bind,
366 .of_match = atmel_pio4_ids,
367 .plat_auto = sizeof(struct atmel_pio4_plat),
368 };
369
370 #endif
371