1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021
4 * lixinde <lixinde@phytium.com.cn>
5 * weichangzheng <weichangzheng@phytium.com.cn>
6 */
7
8 #include <stdio.h>
9 #include <string.h>
10 #include <asm/io.h>
11 #include <linux/arm-smccc.h>
12 #include <init.h>
13 #include "cpu.h"
14
15 struct pll_config {
16 u32 magic;
17 u32 version;
18 u32 size;
19 u8 rev1[4];
20 u32 core_pll;
21 u32 res1;
22 u32 lmu_pll;
23 u32 res2;
24 u32 res3;
25 u32 res4;
26 u32 res5;
27 } __attribute((aligned(4)));
28
29 struct pll_config const pll_base_info = {
30 .magic = PARAMETER_PLL_MAGIC,
31 .version = 0x1,
32 .size = 0x30,
33 .core_pll = 2300, /*MHz*/
34 .lmu_pll = 667, /*MHz*/
35 };
36
get_reset_source(void)37 u32 get_reset_source(void)
38 {
39 struct arm_smccc_res res;
40
41 arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
42 return res.a0;
43 }
44
pll_init(void)45 void pll_init(void)
46 {
47 u8 buffer[0x100];
48 struct arm_smccc_res res;
49
50 memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
51 arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
52 if (res.a0 != 0)
53 panic("PLL init failed :0x%lx\n", res.a0);
54 }
55
check_reset(void)56 void check_reset(void)
57 {
58 u32 rst;
59
60 rst = get_reset_source();
61
62 switch (rst) {
63 case CPU_RESET_POWER_ON:
64 pll_init();
65 break;
66 case CPU_RESET_PLL:
67 break;
68 case CPU_RESET_WATCH_DOG:
69 break;
70 default:
71 panic("other reset source\n");
72 }
73 }
74