1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <log.h>
9 #include <spl.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <linux/delay.h>
14
15 #include "ddr3_init.h"
16
17 #if defined(MV88F78X60)
18 #include "ddr3_axp_vars.h"
19 #elif defined(MV88F67XX)
20 #include "ddr3_a370_vars.h"
21 #elif defined(MV88F672X)
22 #include "ddr3_a375_vars.h"
23 #endif
24
25 #ifdef STATIC_TRAINING
26 static void ddr3_static_training_init(void);
27 #endif
28 #ifdef DUNIT_STATIC
29 static void ddr3_static_mc_init(void);
30 #endif
31 #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING)
32 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void);
33 #endif
34 #if defined(MV88F672X)
35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
36 #endif
37 u32 mv_board_id_get(void);
38 extern void ddr3_set_sw_wl_rl_debug(u32);
39 extern void ddr3_set_pbs(u32);
40 extern void ddr3_set_log_level(u32 val);
41
42 static u32 log_level = DDR3_LOG_LEVEL;
43
44 static u32 ddr3_init_main(void);
45
46 /*
47 * Name: ddr3_set_log_level
48 * Desc: This routine initialize the log_level acording to nLogLevel
49 * which getting from user
50 * Args: nLogLevel
51 * Notes:
52 * Returns: None.
53 */
ddr3_set_log_level(u32 val)54 void ddr3_set_log_level(u32 val)
55 {
56 log_level = val;
57 }
58
59 /*
60 * Name: ddr3_get_log_level
61 * Desc: This routine returns the log level
62 * Args: none
63 * Notes:
64 * Returns: log level.
65 */
ddr3_get_log_level(void)66 u32 ddr3_get_log_level(void)
67 {
68 return log_level;
69 }
70
debug_print_reg(u32 reg)71 static void debug_print_reg(u32 reg)
72 {
73 printf("0x%08x = 0x%08x\n", reg, reg_read(reg));
74 }
75
print_dunit_setup(void)76 static void print_dunit_setup(void)
77 {
78 puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");
79
80 #ifdef DUNIT_STATIC
81 puts("\nStatic D-UNIT Setup:\n");
82 #endif
83 #ifdef DUNIT_SPD
84 puts("\nDynamic(using SPD) D-UNIT Setup:\n");
85 #endif
86 debug_print_reg(REG_SDRAM_CONFIG_ADDR);
87 debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR);
88 debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR);
89 debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR);
90 debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR);
91 debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR);
92 debug_print_reg(REG_SDRAM_OPERATION_ADDR);
93 debug_print_reg(REG_SDRAM_MODE_ADDR);
94 debug_print_reg(REG_SDRAM_EXT_MODE_ADDR);
95 debug_print_reg(REG_DDR_CONT_HIGH_ADDR);
96 debug_print_reg(REG_ODT_TIME_LOW_ADDR);
97 debug_print_reg(REG_SDRAM_ERROR_ADDR);
98 debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR);
99 debug_print_reg(REG_OUDDR3_TIMING_ADDR);
100 debug_print_reg(REG_ODT_TIME_HIGH_ADDR);
101 debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR);
102 debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR);
103 debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR);
104 #ifndef MV88F67XX
105 debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR);
106 debug_print_reg(REG_DRAM_AXI_CTRL_ADDR);
107 debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR);
108 debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR);
109 debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR);
110 debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR);
111 debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR);
112 debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR);
113 debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR);
114 debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
115 debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
116 debug_print_reg(REG_DDR3_MR0_ADDR);
117 debug_print_reg(REG_DDR3_MR1_ADDR);
118 debug_print_reg(REG_DDR3_MR2_ADDR);
119 debug_print_reg(REG_DDR3_MR3_ADDR);
120 debug_print_reg(REG_DDR3_RANK_CTRL_ADDR);
121 debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR);
122 debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL);
123 debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG);
124 debug_print_reg(DLB_AGING_REGISTER);
125 debug_print_reg(DLB_EVICTION_CONTROL_REG);
126 debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG);
127 #if defined(MV88F672X)
128 debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0));
129 debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0));
130 debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1));
131 debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1));
132 #else
133 debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR);
134 #endif
135 debug_print_reg(REG_CDI_CONFIG_ADDR);
136 #endif
137 }
138
139 #if !defined(STATIC_TRAINING)
ddr3_restore_and_set_final_windows(u32 * win_backup)140 static void ddr3_restore_and_set_final_windows(u32 *win_backup)
141 {
142 u32 ui, reg, cs;
143 u32 win_ctrl_reg, num_of_win_regs;
144 u32 cs_ena = ddr3_get_cs_ena_from_reg();
145
146 #if defined(MV88F672X)
147 if (DDR3_FAST_PATH_EN == 0)
148 return;
149 #endif
150
151 #if defined(MV88F672X)
152 win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
153 num_of_win_regs = 8;
154 #else
155 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
156 num_of_win_regs = 16;
157 #endif
158
159 /* Return XBAR windows 4-7 or 16-19 init configuration */
160 for (ui = 0; ui < num_of_win_regs; ui++)
161 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);
162
163 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");
164
165 #if defined(MV88F672X)
166 /* Set L2 filtering to 1G */
167 reg_write(0x8c04, 0x40000000);
168
169 /* Open fast path windows */
170 for (cs = 0; cs < MAX_CS; cs++) {
171 if (cs_ena & (1 << cs)) {
172 /* set fast path window control for the cs */
173 reg = 0x1FFFFFE1;
174 reg |= (cs << 2);
175 reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
176 /* Open fast path Window */
177 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
178 /* set fast path window base address for the cs */
179 reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
180 /* Set base address */
181 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
182 }
183 }
184 #else
185 reg = 0x1FFFFFE1;
186 for (cs = 0; cs < MAX_CS; cs++) {
187 if (cs_ena & (1 << cs)) {
188 reg |= (cs << 2);
189 break;
190 }
191 }
192
193 /* Open fast path Window to - 0.5G */
194 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
195 #endif
196 }
197
ddr3_save_and_set_training_windows(u32 * win_backup)198 static void ddr3_save_and_set_training_windows(u32 *win_backup)
199 {
200 u32 cs_ena = ddr3_get_cs_ena_from_reg();
201 u32 reg, tmp_count, cs, ui;
202 u32 win_ctrl_reg, win_base_reg, win_remap_reg;
203 u32 num_of_win_regs, win_jump_index;
204
205 #if defined(MV88F672X)
206 /* Disable L2 filtering */
207 reg_write(0x8c04, 0);
208
209 win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
210 win_base_reg = REG_XBAR_WIN_16_BASE_ADDR;
211 win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR;
212 win_jump_index = 0x8;
213 num_of_win_regs = 8;
214 #else
215 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
216 win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
217 win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
218 win_jump_index = 0x10;
219 num_of_win_regs = 16;
220 #endif
221
222 /* Close XBAR Window 19 - Not needed */
223 /* {0x000200e8} - Open Mbus Window - 2G */
224 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
225
226 /* Save XBAR Windows 4-19 init configurations */
227 for (ui = 0; ui < num_of_win_regs; ui++)
228 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
229
230 /* Open XBAR Windows 4-7 or 16-19 for other CS */
231 reg = 0;
232 tmp_count = 0;
233 for (cs = 0; cs < MAX_CS; cs++) {
234 if (cs_ena & (1 << cs)) {
235 switch (cs) {
236 case 0:
237 reg = 0x0E00;
238 break;
239 case 1:
240 reg = 0x0D00;
241 break;
242 case 2:
243 reg = 0x0B00;
244 break;
245 case 3:
246 reg = 0x0700;
247 break;
248 }
249 reg |= (1 << 0);
250 reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
251
252 reg_write(win_ctrl_reg + win_jump_index * tmp_count,
253 reg);
254 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
255 reg_write(win_base_reg + win_jump_index * tmp_count,
256 reg);
257
258 if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) {
259 reg_write(win_remap_reg +
260 win_jump_index * tmp_count, 0);
261 }
262
263 tmp_count++;
264 }
265 }
266 }
267 #endif /* !defined(STATIC_TRAINING) */
268
269 /*
270 * Name: ddr3_init - Main DDR3 Init function
271 * Desc: This routine initialize the DDR3 MC and runs HW training.
272 * Args: None.
273 * Notes:
274 * Returns: None.
275 */
ddr3_init(void)276 int ddr3_init(void)
277 {
278 unsigned int status;
279
280 ddr3_set_pbs(DDR3_PBS);
281 ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL);
282
283 status = ddr3_init_main();
284 if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
285 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");
286 if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
287 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup");
288 if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
289 DEBUG_INIT_S("DDR3 Training Error: Max CS limit");
290 if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
291 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit");
292 if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
293 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");
294 if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
295 DEBUG_INIT_S("DDR3 Training Error: TWSI failure");
296 if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
297 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match");
298 if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
299 DEBUG_INIT_S("DDR3 Training Error: TWSI bad type");
300 if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
301 DEBUG_INIT_S("DDR3 Training Error: bus width no match");
302 if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
303 DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
304
305 return status;
306 }
307
print_ddr_target_freq(u32 cpu_freq,u32 fab_opt)308 static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt)
309 {
310 puts("\nDDR3 Training Sequence - Run DDR3 at ");
311
312 switch (cpu_freq) {
313 #if defined(MV88F672X)
314 case 21:
315 puts("533 Mhz\n");
316 break;
317 #else
318 case 1:
319 puts("533 Mhz\n");
320 break;
321 case 2:
322 if (fab_opt == 5)
323 puts("600 Mhz\n");
324 if (fab_opt == 9)
325 puts("400 Mhz\n");
326 break;
327 case 3:
328 puts("667 Mhz\n");
329 break;
330 case 4:
331 if (fab_opt == 5)
332 puts("750 Mhz\n");
333 if (fab_opt == 9)
334 puts("500 Mhz\n");
335 break;
336 case 0xa:
337 puts("400 Mhz\n");
338 break;
339 case 0xb:
340 if (fab_opt == 5)
341 puts("800 Mhz\n");
342 if (fab_opt == 9)
343 puts("553 Mhz\n");
344 if (fab_opt == 0xA)
345 puts("640 Mhz\n");
346 break;
347 #endif
348 default:
349 puts("NOT DEFINED FREQ\n");
350 }
351 }
352
ddr3_init_main(void)353 static u32 ddr3_init_main(void)
354 {
355 u32 target_freq;
356 u32 reg = 0;
357 u32 cpu_freq, fab_opt, hclk_time_ps, soc_num;
358 __maybe_unused u32 ecc = DRAM_ECC;
359 __maybe_unused int dqs_clk_aligned = 0;
360 __maybe_unused u32 scrub_offs, scrub_size;
361 __maybe_unused u32 ddr_width = BUS_WIDTH;
362 __maybe_unused int status;
363 __maybe_unused u32 win_backup[16];
364 __maybe_unused struct udevice *udev;
365 __maybe_unused int ret;
366
367 /* SoC/Board special Initializtions */
368 fab_opt = ddr3_get_fab_opt();
369
370 #ifdef CONFIG_SPD_EEPROM
371 ret = i2c_get_chip_for_busnum(0, BUS_WIDTH_ECC_TWSI_ADDR, 1, &udev);
372 if (ret) {
373 printf("Cannot find SPD EEPROM\n");
374 return MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP;
375 }
376 #endif
377
378 ddr3_print_version();
379 DEBUG_INIT_S("4\n");
380 /* Lib version 5.5.4 */
381
382 fab_opt = ddr3_get_fab_opt();
383
384 /* Switching CPU to MRVL ID */
385 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
386 SAR1_CPU_CORE_OFFSET;
387 switch (soc_num) {
388 case 0x3:
389 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
390 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
391 case 0x1:
392 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
393 case 0x0:
394 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
395 default:
396 break;
397 }
398
399 /* Power down deskew PLL */
400 #if !defined(MV88F672X)
401 /* 0x18780 [25] */
402 reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));
403 reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);
404 #endif
405
406 /*
407 * Stage 0 - Set board configuration
408 */
409 cpu_freq = ddr3_get_cpu_freq();
410 if (fab_opt > FAB_OPT)
411 fab_opt = FAB_OPT - 1;
412
413 if (ddr3_get_log_level() > 0)
414 print_ddr_target_freq(cpu_freq, fab_opt);
415
416 #if defined(MV88F672X)
417 get_target_freq(cpu_freq, &target_freq, &hclk_time_ps);
418 #else
419 target_freq = cpu_ddr_ratios[fab_opt][cpu_freq];
420 hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq];
421 #endif
422 if ((target_freq == 0) || (hclk_time_ps == 0)) {
423 DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");
424 if (target_freq == 0) {
425 DEBUG_INIT_C("target_freq", target_freq, 2);
426 DEBUG_INIT_C("fab_opt", fab_opt, 2);
427 DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
428 } else if (hclk_time_ps == 0) {
429 DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2);
430 DEBUG_INIT_C("fab_opt", fab_opt, 2);
431 DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
432 }
433
434 return MV_DDR3_TRAINING_ERR_BAD_SAR;
435 }
436
437 #if defined(ECC_SUPPORT)
438 scrub_offs = U_BOOT_START_ADDR;
439 scrub_size = U_BOOT_SCRUB_SIZE;
440 #else
441 scrub_offs = 0;
442 scrub_size = 0;
443 #endif
444
445 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
446 ecc = 0;
447 if (ddr3_check_config(udev, CONFIG_ECC))
448 ecc = 1;
449 #endif
450
451 #ifdef DQS_CLK_ALIGNED
452 dqs_clk_aligned = 1;
453 #endif
454
455 /* Check if DRAM is already initialized */
456 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
457 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
458 DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");
459 return MV_OK;
460 }
461
462 /*
463 * Stage 1 - Dunit Setup
464 */
465
466 #ifdef DUNIT_STATIC
467 /*
468 * For Static D-Unit Setup use must set the correct static values
469 * at the ddr3_*soc*_vars.h file
470 */
471 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");
472 ddr3_static_mc_init();
473
474 #ifdef ECC_SUPPORT
475 ecc = DRAM_ECC;
476 if (ecc) {
477 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
478 reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
479 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
480 }
481 #endif
482 #endif
483
484 #if defined(MV88F78X60) || defined(MV88F672X)
485 #if defined(AUTO_DETECTION_SUPPORT)
486 /*
487 * Configurations for both static and dynamic MC setups
488 *
489 * Dynamically Set 32Bit and ECC for AXP (Relevant only for
490 * Marvell DB boards)
491 */
492 if (ddr3_check_config(udev, CONFIG_BUS_WIDTH)) {
493 ddr_width = 32;
494 DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
495 }
496 #endif
497
498 #if defined(MV88F672X)
499 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
500 if ((reg >> 15) & 1)
501 ddr_width = 32;
502 else
503 ddr_width = 16;
504 #endif
505 #endif
506
507 #ifdef DUNIT_SPD
508 status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
509 if (MV_OK != status) {
510 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");
511 return status;
512 }
513 #endif
514
515 /* Fix read ready phases for all SOC in reg 0x15C8 */
516 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
517 reg &= ~(REG_TRAINING_DEBUG_3_MASK);
518 reg |= 0x4; /* Phase 0 */
519 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
520 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
521 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
522 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
523 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
524 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
525 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
526 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
527 reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
528
529 #if defined(MV88F672X)
530 /*
531 * AxiBrespMode[8] = Compliant,
532 * AxiAddrDecodeCntrl[11] = Internal,
533 * AxiDataBusWidth[0] = 128bit
534 */
535 /* 0x14A8 - AXI Control Register */
536 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
537 #else
538 /* 0x14A8 - AXI Control Register */
539 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);
540 reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);
541
542 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &
543 (1 << REG_DDR_IO_CLK_RATIO_OFFS))) {
544 /* 0x14A8 - AXI Control Register */
545 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);
546 reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);
547 }
548 #endif
549
550 #if !defined(MV88F67XX)
551 /*
552 * ARMADA-370 activate DLB later at the u-boot,
553 * Armada38x - No DLB activation at this time
554 */
555 reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);
556
557 #if defined(MV88F78X60)
558 /* WA according to eratta GL-8672902*/
559 if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
560 reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);
561 #endif
562
563 reg_write(DLB_AGING_REGISTER, 0x0f7f007f);
564 reg_write(DLB_EVICTION_CONTROL_REG, 0x0);
565 reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);
566
567 reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);
568 reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);
569 reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);
570 reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);
571
572 #if defined(MV88F78X60)
573 /* WA according to eratta GL-8672902 */
574 if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
575 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
576 reg |= DLB_ENABLE;
577 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
578 }
579 #endif /* end defined(MV88F78X60) */
580 #endif /* end !defined(MV88F67XX) */
581
582 if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
583 print_dunit_setup();
584
585 /*
586 * Stage 2 - Training Values Setup
587 */
588 #ifdef STATIC_TRAINING
589 /*
590 * DRAM Init - After all the D-unit values are set, its time to init
591 * the D-unit
592 */
593 /* Wait for '0' */
594 reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
595 do {
596 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
597 (1 << REG_SDRAM_INIT_CTRL_OFFS);
598 } while (reg);
599
600 /* ddr3 init using static parameters - HW training is disabled */
601 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");
602 ddr3_static_training_init();
603
604 #if defined(MV88F78X60)
605 /*
606 * If ECC is enabled, need to scrub the U-Boot area memory region -
607 * Run training function with Xor bypass just to scrub the memory
608 */
609 status = ddr3_hw_training(target_freq, ddr_width,
610 1, scrub_offs, scrub_size,
611 dqs_clk_aligned, DDR3_TRAINING_DEBUG,
612 REG_DIMM_SKIP_WL);
613 if (MV_OK != status) {
614 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
615 return status;
616 }
617 #endif
618 #else
619 /* Set X-BAR windows for the training sequence */
620 ddr3_save_and_set_training_windows(win_backup);
621
622 /* Run DDR3 Training Sequence */
623 /* DRAM Init */
624 reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
625 do {
626 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
627 (1 << REG_SDRAM_INIT_CTRL_OFFS);
628 } while (reg); /* Wait for '0' */
629
630 /* ddr3 init using DDR3 HW training procedure */
631 DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");
632 status = ddr3_hw_training(target_freq, ddr_width,
633 0, scrub_offs, scrub_size,
634 dqs_clk_aligned, DDR3_TRAINING_DEBUG,
635 REG_DIMM_SKIP_WL);
636 if (MV_OK != status) {
637 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
638 return status;
639 }
640 #endif
641
642 /*
643 * Stage 3 - Finish
644 */
645 #if defined(MV88F78X60) || defined(MV88F672X)
646 /* Disable ECC Ignore bit */
647 reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
648 ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
649 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
650 #endif
651
652 #if !defined(STATIC_TRAINING)
653 /* Restore and set windows */
654 ddr3_restore_and_set_final_windows(win_backup);
655 #endif
656
657 /* Update DRAM init indication in bootROM register */
658 reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
659 reg_write(REG_BOOTROM_ROUTINE_ADDR,
660 reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
661
662 #if !defined(MV88F67XX)
663 #if defined(MV88F78X60)
664 if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
665 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
666 if (ecc == 0)
667 reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
668 }
669 #endif /* end defined(MV88F78X60) */
670
671 reg_write(DLB_EVICTION_CONTROL_REG, 0x9);
672
673 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
674 reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
675 DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR);
676 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
677 #endif /* end !defined(MV88F67XX) */
678
679 #ifdef STATIC_TRAINING
680 DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");
681 #else
682 DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");
683 #endif
684
685 return MV_OK;
686 }
687
688 /*
689 * Name: ddr3_get_cpu_freq
690 * Desc: read S@R and return CPU frequency
691 * Args:
692 * Notes:
693 * Returns: required value
694 */
695
ddr3_get_cpu_freq(void)696 u32 ddr3_get_cpu_freq(void)
697 {
698 u32 reg, cpu_freq;
699
700 #if defined(MV88F672X)
701 /* Read sample at reset setting */
702 reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0xE8200 */
703 cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
704 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
705 #else
706 /* Read sample at reset setting */
707 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR); /* 0x18230 [23:21] */
708 #if defined(MV88F78X60)
709 cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
710 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
711 reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0x18234 [20] */
712 cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3);
713 #elif defined(MV88F67XX)
714 cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
715 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
716 #endif
717 #endif
718
719 return cpu_freq;
720 }
721
722 /*
723 * Name: ddr3_get_fab_opt
724 * Desc: read S@R and return CPU frequency
725 * Args:
726 * Notes:
727 * Returns: required value
728 */
ddr3_get_fab_opt(void)729 u32 ddr3_get_fab_opt(void)
730 {
731 __maybe_unused u32 reg, fab_opt;
732
733 #if defined(MV88F672X)
734 return 0; /* No fabric */
735 #else
736 /* Read sample at reset setting */
737 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);
738 fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >>
739 REG_SAMPLE_RESET_FAB_OFFS;
740
741 #if defined(MV88F78X60)
742 reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);
743 fab_opt |= (((reg >> 19) & 0x1) << 4);
744 #endif
745
746 return fab_opt;
747 #endif
748 }
749
750 /*
751 * Name: ddr3_get_vco_freq
752 * Desc: read S@R and return VCO frequency
753 * Args:
754 * Notes:
755 * Returns: required value
756 */
ddr3_get_vco_freq(void)757 u32 ddr3_get_vco_freq(void)
758 {
759 u32 fab, cpu_freq, ui_vco_freq;
760
761 fab = ddr3_get_fab_opt();
762 cpu_freq = ddr3_get_cpu_freq();
763
764 if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 ||
765 fab == 15 || fab == 17 || fab == 20)
766 ui_vco_freq = cpu_freq + CLK_CPU;
767 else
768 ui_vco_freq = cpu_freq;
769
770 return ui_vco_freq;
771 }
772
773 #ifdef STATIC_TRAINING
774 /*
775 * Name: ddr3_static_training_init - Init DDR3 Training with
776 * static parameters
777 * Desc: Use this routine to init the controller without the HW training
778 * procedure
779 * User must provide compatible header file with registers data.
780 * Args: None.
781 * Notes:
782 * Returns: None.
783 */
ddr3_static_training_init(void)784 void ddr3_static_training_init(void)
785 {
786 MV_DRAM_MODES *ddr_mode;
787 u32 reg;
788 int j;
789
790 ddr_mode = ddr3_get_static_ddr_mode();
791
792 j = 0;
793 while (ddr_mode->vals[j].reg_addr != 0) {
794 udelay(10); /* haim want to delay each write */
795 reg_write(ddr_mode->vals[j].reg_addr,
796 ddr_mode->vals[j].reg_value);
797
798 if (ddr_mode->vals[j].reg_addr ==
799 REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
800 do {
801 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
802 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
803 } while (reg);
804 j++;
805 }
806 }
807 #endif
808
809 /*
810 * Name: ddr3_get_static_mc_value - Init Memory controller with static
811 * parameters
812 * Desc: Use this routine to init the controller without the HW training
813 * procedure
814 * User must provide compatible header file with registers data.
815 * Args: None.
816 * Notes:
817 * Returns: None.
818 */
ddr3_get_static_mc_value(u32 reg_addr,u32 offset1,u32 mask1,u32 offset2,u32 mask2)819 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
820 u32 mask2)
821 {
822 u32 reg, tmp;
823
824 reg = reg_read(reg_addr);
825
826 tmp = (reg >> offset1) & mask1;
827 if (mask2)
828 tmp |= (reg >> offset2) & mask2;
829
830 return tmp;
831 }
832
833 /*
834 * Name: ddr3_get_static_ddr_mode - Init Memory controller with static
835 * parameters
836 * Desc: Use this routine to init the controller without the HW training
837 * procedure
838 * User must provide compatible header file with registers data.
839 * Args: None.
840 * Notes:
841 * Returns: None.
842 */
ddr3_get_static_ddr_mode(void)843 __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
844 {
845 u32 chip_board_rev, i;
846 u32 size;
847
848 /* Do not modify this code. relevant only for marvell Boards */
849 #if defined(DB_78X60_PCAC)
850 chip_board_rev = Z1_PCAC;
851 #elif defined(DB_78X60_AMC)
852 chip_board_rev = A0_AMC;
853 #elif defined(DB_88F6710_PCAC)
854 chip_board_rev = A0_PCAC;
855 #elif defined(RD_88F6710)
856 chip_board_rev = A0_RD;
857 #elif defined(MV88F672X)
858 chip_board_rev = mv_board_id_get();
859 #else
860 chip_board_rev = A0;
861 #endif
862
863 size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES);
864 for (i = 0; i < size; i++) {
865 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
866 (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
867 (chip_board_rev == ddr_modes[i].chip_board_rev))
868 return &ddr_modes[i];
869 }
870
871 return &ddr_modes[0];
872 }
873
874 #ifdef DUNIT_STATIC
875 /*
876 * Name: ddr3_static_mc_init - Init Memory controller with static parameters
877 * Desc: Use this routine to init the controller without the HW training
878 * procedure
879 * User must provide compatible header file with registers data.
880 * Args: None.
881 * Notes:
882 * Returns: None.
883 */
ddr3_static_mc_init(void)884 void ddr3_static_mc_init(void)
885 {
886 MV_DRAM_MODES *ddr_mode;
887 u32 reg;
888 int j;
889
890 ddr_mode = ddr3_get_static_ddr_mode();
891 j = 0;
892 while (ddr_mode->regs[j].reg_addr != 0) {
893 reg_write(ddr_mode->regs[j].reg_addr,
894 ddr_mode->regs[j].reg_value);
895 if (ddr_mode->regs[j].reg_addr ==
896 REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
897 do {
898 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
899 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
900 } while (reg);
901 j++;
902 }
903 }
904 #endif
905
906 /*
907 * Name: ddr3_check_config - Check user configurations: ECC/MultiCS
908 * Desc:
909 * Args: twsi Address
910 * Notes: Only Available for ArmadaXP/Armada 370 DB boards
911 * Returns: None.
912 */
ddr3_check_config(struct udevice * udev,MV_CONFIG_TYPE config_type)913 int ddr3_check_config(struct udevice *udev, MV_CONFIG_TYPE config_type)
914 {
915 #ifdef AUTO_DETECTION_SUPPORT
916 u8 data = 0;
917 int ret;
918 int offset;
919
920 if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH))
921 offset = 1;
922 else
923 offset = 0;
924
925 ret = dm_i2c_read(udev, offset, &data, 1);
926 if (!ret) {
927 switch (config_type) {
928 case CONFIG_ECC:
929 if (data & 0x2)
930 return 1;
931 break;
932 case CONFIG_BUS_WIDTH:
933 if (data & 0x1)
934 return 1;
935 break;
936 #ifdef DB_88F6710
937 case CONFIG_MULTI_CS:
938 if (CFG_MULTI_CS_MODE(data))
939 return 1;
940 break;
941 #else
942 case CONFIG_MULTI_CS:
943 break;
944 #endif
945 }
946 }
947 #endif
948
949 return 0;
950 }
951
952 /*
953 * Name: ddr3_cl_to_valid_cl - this return register matching CL value
954 * Desc:
955 * Args: clValue - the value
956
957 * Notes:
958 * Returns: required CL value
959 */
ddr3_cl_to_valid_cl(u32 cl)960 u32 ddr3_cl_to_valid_cl(u32 cl)
961 {
962 switch (cl) {
963 case 5:
964 return 2;
965 break;
966 case 6:
967 return 4;
968 break;
969 case 7:
970 return 6;
971 break;
972 case 8:
973 return 8;
974 break;
975 case 9:
976 return 10;
977 break;
978 case 10:
979 return 12;
980 break;
981 case 11:
982 return 14;
983 break;
984 case 12:
985 return 1;
986 break;
987 case 13:
988 return 3;
989 break;
990 case 14:
991 return 5;
992 break;
993 default:
994 return 2;
995 }
996 }
997
998 /*
999 * Name: ddr3_cl_to_valid_cl - this return register matching CL value
1000 * Desc:
1001 * Args: clValue - the value
1002 * Notes:
1003 * Returns: required CL value
1004 */
ddr3_valid_cl_to_cl(u32 ui_valid_cl)1005 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
1006 {
1007 switch (ui_valid_cl) {
1008 case 1:
1009 return 12;
1010 break;
1011 case 2:
1012 return 5;
1013 break;
1014 case 3:
1015 return 13;
1016 break;
1017 case 4:
1018 return 6;
1019 break;
1020 case 5:
1021 return 14;
1022 break;
1023 case 6:
1024 return 7;
1025 break;
1026 case 8:
1027 return 8;
1028 break;
1029 case 10:
1030 return 9;
1031 break;
1032 case 12:
1033 return 10;
1034 break;
1035 case 14:
1036 return 11;
1037 break;
1038 default:
1039 return 0;
1040 }
1041 }
1042
1043 /*
1044 * Name: ddr3_get_cs_num_from_reg
1045 * Desc:
1046 * Args:
1047 * Notes:
1048 * Returns:
1049 */
ddr3_get_cs_num_from_reg(void)1050 u32 ddr3_get_cs_num_from_reg(void)
1051 {
1052 u32 cs_ena = ddr3_get_cs_ena_from_reg();
1053 u32 cs_count = 0;
1054 u32 cs;
1055
1056 for (cs = 0; cs < MAX_CS; cs++) {
1057 if (cs_ena & (1 << cs))
1058 cs_count++;
1059 }
1060
1061 return cs_count;
1062 }
1063
1064 /*
1065 * Name: ddr3_get_cs_ena_from_reg
1066 * Desc:
1067 * Args:
1068 * Notes:
1069 * Returns:
1070 */
ddr3_get_cs_ena_from_reg(void)1071 u32 ddr3_get_cs_ena_from_reg(void)
1072 {
1073 return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
1074 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
1075 }
1076
1077 /*
1078 * mv_ctrl_rev_get - Get Marvell controller device revision number
1079 *
1080 * DESCRIPTION:
1081 * This function returns 8bit describing the device revision as defined
1082 * in PCI Express Class Code and Revision ID Register.
1083 *
1084 * INPUT:
1085 * None.
1086 *
1087 * OUTPUT:
1088 * None.
1089 *
1090 * RETURN:
1091 * 8bit desscribing Marvell controller revision number
1092 *
1093 */
1094 #if !defined(MV88F672X)
mv_ctrl_rev_get(void)1095 u8 mv_ctrl_rev_get(void)
1096 {
1097 u8 rev_num;
1098
1099 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1100 /* Check pex power state */
1101 u32 pex_power;
1102 pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
1103 if (pex_power == 0)
1104 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
1105 #endif
1106 rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
1107 PCI_CLASS_CODE_AND_REVISION_ID));
1108
1109 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1110 /* Return to power off state */
1111 if (pex_power == 0)
1112 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
1113 #endif
1114
1115 return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
1116 }
1117
1118 #endif
1119
1120 #if defined(MV88F672X)
get_target_freq(u32 freq_mode,u32 * ddr_freq,u32 * hclk_ps)1121 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
1122 {
1123 u32 tmp, hclk;
1124
1125 switch (freq_mode) {
1126 case CPU_333MHz_DDR_167MHz_L2_167MHz:
1127 hclk = 84;
1128 tmp = DDR_100;
1129 break;
1130 case CPU_266MHz_DDR_266MHz_L2_133MHz:
1131 case CPU_333MHz_DDR_222MHz_L2_167MHz:
1132 case CPU_400MHz_DDR_200MHz_L2_200MHz:
1133 case CPU_400MHz_DDR_267MHz_L2_200MHz:
1134 case CPU_533MHz_DDR_267MHz_L2_267MHz:
1135 case CPU_500MHz_DDR_250MHz_L2_250MHz:
1136 case CPU_600MHz_DDR_300MHz_L2_300MHz:
1137 case CPU_800MHz_DDR_267MHz_L2_400MHz:
1138 case CPU_900MHz_DDR_300MHz_L2_450MHz:
1139 tmp = DDR_300;
1140 hclk = 150;
1141 break;
1142 case CPU_333MHz_DDR_333MHz_L2_167MHz:
1143 case CPU_500MHz_DDR_334MHz_L2_250MHz:
1144 case CPU_666MHz_DDR_333MHz_L2_333MHz:
1145 tmp = DDR_333;
1146 hclk = 165;
1147 break;
1148 case CPU_533MHz_DDR_356MHz_L2_267MHz:
1149 tmp = DDR_360;
1150 hclk = 180;
1151 break;
1152 case CPU_400MHz_DDR_400MHz_L2_200MHz:
1153 case CPU_600MHz_DDR_400MHz_L2_300MHz:
1154 case CPU_800MHz_DDR_400MHz_L2_400MHz:
1155 case CPU_400MHz_DDR_400MHz_L2_400MHz:
1156 tmp = DDR_400;
1157 hclk = 200;
1158 break;
1159 case CPU_666MHz_DDR_444MHz_L2_333MHz:
1160 case CPU_900MHz_DDR_450MHz_L2_450MHz:
1161 tmp = DDR_444;
1162 hclk = 222;
1163 break;
1164 case CPU_500MHz_DDR_500MHz_L2_250MHz:
1165 case CPU_1000MHz_DDR_500MHz_L2_500MHz:
1166 case CPU_1000MHz_DDR_500MHz_L2_333MHz:
1167 tmp = DDR_500;
1168 hclk = 250;
1169 break;
1170 case CPU_533MHz_DDR_533MHz_L2_267MHz:
1171 case CPU_800MHz_DDR_534MHz_L2_400MHz:
1172 case CPU_1100MHz_DDR_550MHz_L2_550MHz:
1173 tmp = DDR_533;
1174 hclk = 267;
1175 break;
1176 case CPU_600MHz_DDR_600MHz_L2_300MHz:
1177 case CPU_900MHz_DDR_600MHz_L2_450MHz:
1178 case CPU_1200MHz_DDR_600MHz_L2_600MHz:
1179 tmp = DDR_600;
1180 hclk = 300;
1181 break;
1182 case CPU_666MHz_DDR_666MHz_L2_333MHz:
1183 case CPU_1000MHz_DDR_667MHz_L2_500MHz:
1184 tmp = DDR_666;
1185 hclk = 333;
1186 break;
1187 default:
1188 *ddr_freq = 0;
1189 *hclk_ps = 0;
1190 break;
1191 }
1192
1193 *ddr_freq = tmp; /* DDR freq define */
1194 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */
1195
1196 return;
1197 }
1198 #endif
1199