| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rv1108.c | 153 uint8_t div; in rv1108_mac_set_clk() local
178 u32 div; in rv1108_sfc_set_clk() local
197 u32 div, val; in rv1108_saradc_get_clk() local
222 u32 div, val; in rv1108_aclk_vio1_get_clk() local
248 u32 div, val; in rv1108_aclk_vio0_get_clk() local
283 u32 div, val; in rv1108_dclk_vop_get_clk() local
311 u32 div, val; in rv1108_aclk_bus_get_clk() local
339 u32 div, val; in rv1108_aclk_peri_get_clk() local
351 u32 div, val; in rv1108_hclk_peri_get_clk() local
363 u32 div, val; in rv1108_pclk_peri_get_clk() local
[all …]
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| A D | clk_rk3588.c | 622 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
781 int src_clk, div; in rk3588_mmc_set_clk() local
867 u32 div, con, parent; in rk3588_aux16m_get_clk() local
888 u32 div; in rk3588_aux16m_set_clk() local
967 int src_clk, div; in rk3588_aclk_vop_set_clk() local
1182 u32 con, div; in rk3588_gmac_get_clk() local
1210 int div; in rk3588_gmac_set_clk() local
1387 u32 con, div, src; in rk3588_pciephy_get_rate() local
1421 u32 clk_src, div; in rk3588_pciephy_set_rate() local
1894 int ret, div; in rk3588_clk_init() local
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| A D | clk_rk3308.c | 132 u32 div, con, con_id; in rk3308_i2c_get_clk() local
198 u8 div; in rk3308_mac_set_clk() local
242 u32 div, con, con_id; in rk3308_mmc_get_clk() local
314 u32 div, con; in rk3308_saradc_get_clk() local
342 u32 div, con; in rk3308_tsadc_get_clk() local
370 u32 div, con, con_id; in rk3308_spi_get_clk() local
429 u32 div, con; in rk3308_pwm_get_clk() local
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() local
612 u32 div, con, parent = priv->dpll_hz; in rk3308_peri_get_clk() local
675 u32 div, con, parent = priv->vpll0_hz; in rk3308_audio_get_clk() local
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| A D | clk_rv1126.c | 194 u32 div, con; in rv1126_i2c_get_pmuclk() local
241 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
318 u32 div, con; in rv1126_spi_get_pmuclk() local
346 u32 div, con; in rv1126_pdpmu_get_pmuclk() local
570 u32 con, div; in rv1126_pdcore_get_clk() local
689 u32 con, div, parent; in rv1126_pdphp_get_clk() local
741 u32 con, div; in rv1126_pdaudio_get_clk() local
766 u32 div, con; in rv1126_i2c_get_clk() local
828 u32 div, con; in rv1126_spi_get_clk() local
855 u32 div, sel, con; in rv1126_pwm_get_clk() local
[all …]
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| A D | clk_rk3128.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
43 const struct pll_div *div) in rkclk_set_pll()
80 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
286 uint div, mux; in rockchip_mmc_get_clk() local
352 u32 div, con; in rk3128_peri_get_pclk() local
397 u32 div, val; in rk3128_saradc_get_clk() local
461 u32 div, con, parent; in rk3128_vop_get_rate() local
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| A D | clk_rk3368.c | 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
94 const struct pll_div *div) in rkclk_set_pll()
164 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
227 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent() local
259 u32 con_id, mux = 0, div = 0; in rk3368_mmc_set_clk() local
331 u8 div; in rk3368_gmac_set_clk() local
386 u32 div, val; in rk3368_spi_get_clk() local
434 u32 div, val; in rk3368_saradc_get_clk() local
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| A D | clk_px30.c | 292 u32 div, con; in px30_i2c_get_clk() local
483 u32 div, con; in px30_nandc_get_clk() local
515 u32 div, con, con_id; in px30_mmc_get_clk() local
587 u32 div, con; in px30_sfc_get_clk() local
613 u32 div, con; in px30_pwm_get_clk() local
666 u32 div, con; in px30_saradc_get_clk() local
692 u32 div, con; in px30_tsadc_get_clk() local
718 u32 div, con; in px30_spi_get_clk() local
1088 u8 div; in px30_mac_set_clk() local
1536 u32 div, con; in px30_pclk_pmu_get_pmuclk() local
[all …]
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| A D | clk_rk3328.c | 35 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
212 const struct pll_div *div) in rkclk_set_pll()
338 u32 div, con; in rk3328_i2c_get_clk() local
427 u8 div; in rk3328_gmac2io_set_clk() local
449 u32 div, con, con_id; in rk3328_mmc_get_clk() local
514 u32 div, con; in rk3328_pwm_get_clk() local
524 u32 div = GPLL_HZ / hz; in rk3328_pwm_set_clk() local
536 u32 div, val; in rk3328_saradc_get_clk() local
561 u32 div, val; in rk3328_spi_get_clk() local
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| A D | clk_rk3288.c | 138 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
152 const struct pll_div *div) in rkclk_set_pll()
234 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
319 u8 div; in rockchip_mac_set_clk() local
581 uint div, mux; in rockchip_mmc_get_clk() local
664 uint div, mux; in rockchip_spi_get_clk() local
727 u32 div, val; in rockchip_saradc_get_clk() local
847 u32 div; in rk3288_clk_set_rate() local
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| A D | clk_rk3066.c | 73 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
86 const struct pll_div *div) in rk3066_clk_set_pll()
257 uint div; in rk3066_clk_mmc_get_clk() local
322 uint div; in rk3066_clk_spi_get_clk() local
369 u32 div, con; in rk3066_clk_saradc_get_clk() local
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| A D | clk_rk322x.c | 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
48 const struct pll_div *div) in rkclk_set_pll()
220 uint div, mux; in rockchip_mmc_get_clk() local
260 u8 div; in rk322x_mac_set_clk() local
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| /u-boot/drivers/clk/ |
| A D | clk-divider.c | 65 unsigned int div; in divider_recalc_rate() local
97 unsigned int div) in clk_divider_is_valid_table_div()
108 unsigned int div, unsigned long flags) in clk_divider_is_valid_div()
118 unsigned int div) in clk_divider_get_table_val()
129 unsigned int div, unsigned long flags, u8 width) in _get_val()
145 unsigned int div, value; in divider_get_val() local
191 struct clk_divider *div; in _register_divider() local
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| A D | clk-fixed-factor.c | 43 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor()
71 unsigned int mult, unsigned int div) in clk_register_fixed_factor()
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| /u-boot/arch/arm/mach-s5pc1xx/ |
| A D | clock.c | 133 unsigned long div; in s5pc110_get_arm_clk() local
153 unsigned long div; in s5pc100_get_arm_clk() local
176 uint div, d0_bus_ratio; in get_hclk() local
193 uint div, d1_bus_ratio, pclkd1_ratio; in get_pclkd1() local
214 unsigned int div; in get_hclk_sys() local
243 unsigned int div; in get_pclk_sys() local
319 void set_mmc_clk(int dev_index, unsigned int div) in set_mmc_clk()
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| /u-boot/drivers/clk/imx/ |
| A D | clk-pllv3.c | 54 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_get_rate() local
64 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_set_rate() local
78 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_generic_get_rate() local
87 u32 val, div; in clk_pllv3_generic_set_rate() local
162 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_sys_get_rate() local
173 u32 val, div; in clk_pllv3_sys_set_rate() local
210 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_av_get_rate() local
228 u32 val, div; in clk_pllv3_av_set_rate() local
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| /u-boot/arch/arm/mach-at91/armv7/ |
| A D | clock.c | 43 unsigned mul, div; in at91_pll_rate() local
196 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) in at91_enable_periph_generated_clk()
262 u32 regval, clk_source, div; in at91_get_periph_generated_clk() local
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| /u-boot/arch/arm/cpu/arm926ejs/mxs/ |
| A D | clock.c | 42 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
74 uint32_t div; in mxs_get_hclk() local
92 uint32_t clkctrl, clkseq, div; in mxs_get_emiclk() local
123 uint32_t clkctrl, clkseq, div; in mxs_get_gpmiclk() local
149 uint32_t div; in mxs_set_ioclk() local
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| /u-boot/drivers/clk/ti/ |
| A D | clk-divider.c | 57 unsigned int div) in _get_val()
76 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up() local
175 int div; in clk_ti_divider_round_rate() local
188 int div; in clk_ti_divider_set_rate() local
216 unsigned int div; in clk_ti_divider_get_rate() local
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| /u-boot/drivers/adc/ |
| A D | stm32-adc-core.c | 38 int div; member
67 int div; in stm32h7_adc_clk_sel() local
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | clock_slice.c | 520 int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div) in clock_set_postdiv()
548 int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div) in clock_get_postdiv()
572 int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, in clock_set_autopostdiv()
610 int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, in clock_get_autopostdiv()
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| /u-boot/drivers/clk/mvebu/ |
| A D | armada-37xx-tbg.c | 58 unsigned int div[NUM_TBG]; member
73 unsigned int div; in tbg_get_div() local
128 unsigned int mult, div; in armada_37xx_tbg_clk_probe() local
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| /u-boot/drivers/clk/nuvoton/ |
| A D | clk_npcm.c | 119 u32 val, div; in npcm_clk_get_div() local
138 static u32 npcm_clk_set_div(struct clk *clk, u32 div) in npcm_clk_set_div()
167 u32 div; in npcm_clk_get_fout() local
243 u32 div; in npcm_clk_set_rate() local
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| /u-boot/arch/arm/mach-exynos/ |
| A D | clock.c | 118 unsigned int div; in exynos_get_pll_clk() local
370 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate() local
469 unsigned int src = 0, div = 0, sub_div = 0; in exynos542x_get_periph_rate() local
575 unsigned long div; in exynos4_get_arm_clk() local
597 unsigned long div; in exynos4x12_get_arm_clk() local
619 unsigned long div; in exynos5_get_arm_clk() local
835 static void exynos4_set_mmc_clk(int dev_index, unsigned int div) in exynos4_set_mmc_clk()
870 static void exynos5_set_mmc_clk(int dev_index, unsigned int div) in exynos5_set_mmc_clk()
894 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) in exynos5420_set_mmc_clk()
1361 unsigned int div; in exynos5_set_i2s_clk_prescaler() local
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| /u-boot/drivers/clk/renesas/ |
| A D | rcar-cpg-lib.c | 63 unsigned int div) in rcar_clk_get_table_val()
77 u32 value, div; in rcar_clk_get_rate64_div_table() local
96 u32 value = 0, div = 0; in rcar_clk_set_rate64_div_table() local
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| /u-boot/arch/arm/mach-at91/arm920t/ |
| A D | clock.c | 44 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
93 unsigned mul, div; in at91_pll_rate() local
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