1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6 #include "ddr3_init.h"
7 #include "mv_ddr_common.h"
8
9 #if defined(CONFIG_DDR4)
10 static char *ddr_type = "DDR4";
11 #else /* CONFIG_DDR4 */
12 static char *ddr_type = "DDR3";
13 #endif /* CONFIG_DDR4 */
14
15 /*
16 * generic_init_controller controls D-unit configuration:
17 * '1' - dynamic D-unit configuration,
18 */
19 u8 generic_init_controller = 1;
20
21 static int mv_ddr_training_params_set(u8 dev_num);
22
23 /*
24 * Name: ddr3_init - Main DDR3 Init function
25 * Desc: This routine initialize the DDR3 MC and runs HW training.
26 * Args: None.
27 * Notes:
28 * Returns: None.
29 */
ddr3_init(void)30 int ddr3_init(void)
31 {
32 int status;
33 int is_manual_cal_done;
34
35 /* Print mv_ddr version */
36 mv_ddr_ver_print();
37
38 mv_ddr_pre_training_fixup();
39
40 /* SoC/Board special initializations */
41 mv_ddr_pre_training_soc_config(ddr_type);
42
43 /* Set log level for training library */
44 mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
45
46 mv_ddr_early_init();
47
48 if (mv_ddr_topology_map_update()) {
49 printf("mv_ddr: failed to update topology\n");
50 return MV_FAIL;
51 }
52
53 if (mv_ddr_early_init2() != MV_OK)
54 return MV_FAIL;
55
56 /* Set training algorithm's parameters */
57 status = mv_ddr_training_params_set(0);
58 if (MV_OK != status)
59 return status;
60
61 mv_ddr_mc_config();
62
63 is_manual_cal_done = mv_ddr_manual_cal_do();
64
65 mv_ddr_mc_init();
66
67 if (!is_manual_cal_done) {
68 #if defined(CONFIG_DDR4)
69 status = mv_ddr4_calibration_adjust(0, 1, 0);
70 if (status != MV_OK) {
71 printf("%s: failed (0x%x)\n", __func__, status);
72 return status;
73 }
74 #endif
75 }
76
77
78 status = ddr3_silicon_post_init();
79 if (MV_OK != status) {
80 printf("DDR3 Post Init - FAILED 0x%x\n", status);
81 return status;
82 }
83
84 /* PHY initialization (Training) */
85 status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
86 if (MV_OK != status) {
87 printf("%s Training Sequence - FAILED\n", ddr_type);
88 return status;
89 }
90
91
92 /* Post MC/PHY initializations */
93 mv_ddr_post_training_soc_config(ddr_type);
94
95 mv_ddr_post_training_fixup();
96
97 if (mv_ddr_is_ecc_ena())
98 mv_ddr_mem_scrubbing();
99
100 printf("mv_ddr: completed successfully\n");
101
102 return MV_OK;
103 }
104
105 /*
106 * Name: mv_ddr_training_params_set
107 * Desc:
108 * Args:
109 * Notes: sets internal training params
110 * Returns:
111 */
mv_ddr_training_params_set(u8 dev_num)112 static int mv_ddr_training_params_set(u8 dev_num)
113 {
114 struct tune_train_params params;
115 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
116 int status;
117 u32 cs_num;
118 int ck_delay;
119
120 cs_num = mv_ddr_cs_num_get();
121 ck_delay = mv_ddr_ck_delay_get();
122
123 /* NOTE: do not remove any field initilization */
124 params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
125 params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
126 params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
127 params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
128 params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
129 params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
130 params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
131 params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
132 params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
133
134 #if defined(CONFIG_DDR4)
135 params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4;
136 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4;
137 params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM_DDR4;
138 params.g_dic = TUNE_TRAINING_PARAMS_DIC_DDR4;
139 if (cs_num == 1) {
140 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
141 params.g_rtt_park = TUNE_TRAINING_PARAMS_RTT_PARK_1CS;
142 } else {
143 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
144 params.g_rtt_park = TUNE_TRAINING_PARAMS_RTT_PARK_2CS;
145 }
146 #else /* CONFIG_DDR4 */
147 params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
148 params.g_dic = TUNE_TRAINING_PARAMS_DIC;
149 params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
150 if (cs_num == 1) {
151 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
152 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
153 } else {
154 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
155 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
156 }
157 #endif /* CONFIG_DDR4 */
158
159 if (ck_delay > 0)
160 params.ck_delay = ck_delay;
161
162 /* Use platform specific override ODT value */
163 if (tm->odt_config)
164 params.g_odt_config = tm->odt_config;
165
166 status = ddr3_tip_tune_training_params(dev_num, ¶ms);
167 if (MV_OK != status) {
168 printf("%s Training Sequence - FAILED\n", ddr_type);
169 return status;
170 }
171
172 return MV_OK;
173 }
174