1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
4 * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
5 * Changes for multibus/multiadapter I2C support.
6 *
7 * (C) Copyright 2001
8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9 *
10 * The original I2C interface was
11 * (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
12 * AIRVENT SAM s.p.a - RIMINI(ITALY)
13 * but has been changed substantially.
14 */
15
16 #ifndef _I2C_H_
17 #define _I2C_H_
18
19 #include <linker_lists.h>
20
21 /*
22 * For now there are essentially two parts to this file - driver model
23 * here at the top, and the older code below (with CONFIG_SYS_I2C_LEGACY being
24 * most recent). The plan is to migrate everything to driver model.
25 * The driver model structures and API are separate as they are different
26 * enough as to be incompatible for compilation purposes.
27 */
28
29 enum dm_i2c_chip_flags {
30 DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */
31 DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */
32 DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */
33 };
34
35 /** enum i2c_speed_mode - standard I2C speed modes */
36 enum i2c_speed_mode {
37 IC_SPEED_MODE_STANDARD,
38 IC_SPEED_MODE_FAST,
39 IC_SPEED_MODE_FAST_PLUS,
40 IC_SPEED_MODE_HIGH,
41 IC_SPEED_MODE_FAST_ULTRA,
42
43 IC_SPEED_MODE_COUNT,
44 };
45
46 /** enum i2c_speed_rate - standard I2C speeds in Hz */
47 enum i2c_speed_rate {
48 I2C_SPEED_STANDARD_RATE = 100000,
49 I2C_SPEED_FAST_RATE = 400000,
50 I2C_SPEED_FAST_PLUS_RATE = 1000000,
51 I2C_SPEED_HIGH_RATE = 3400000,
52 I2C_SPEED_FAST_ULTRA_RATE = 5000000,
53 };
54
55 /** enum i2c_address_mode - available address modes */
56 enum i2c_address_mode {
57 I2C_MODE_7_BIT,
58 I2C_MODE_10_BIT
59 };
60
61 /** enum i2c_device_t - Types of I2C devices, used for compatible strings */
62 enum i2c_device_t {
63 I2C_DEVICE_GENERIC,
64 I2C_DEVICE_HID_OVER_I2C,
65 };
66
67 struct udevice;
68 /**
69 * struct dm_i2c_chip - information about an i2c chip
70 *
71 * An I2C chip is a device on the I2C bus. It sits at a particular address
72 * and normally supports 7-bit or 10-bit addressing.
73 *
74 * To obtain this structure, use dev_get_parent_plat(dev) where dev is
75 * the chip to examine.
76 *
77 * @chip_addr: Chip address on bus
78 * @offset_len: Length of offset in bytes. A single byte offset can
79 * represent up to 256 bytes. A value larger than 1 may be
80 * needed for larger devices.
81 * @flags: Flags for this chip (dm_i2c_chip_flags)
82 * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for
83 * devices which steal addresses as part of offset.
84 * If offset_len is zero, then the offset is encoded
85 * completely within the chip address itself.
86 * e.g. a devce with chip address of 0x2c with 512
87 * registers might use the bottom bit of the address
88 * to indicate which half of the address space is being
89 * accessed while still only using 1 byte offset.
90 * This means it will respond to chip address 0x2c and
91 * 0x2d.
92 * A real world example is the Atmel AT24C04. It's
93 * datasheet explains it's usage of this addressing
94 * mode.
95 * @emul: Emulator for this chip address (only used for emulation)
96 * @emul_idx: Emulator index, used for of-platdata and set by each i2c chip's
97 * bind() method. This allows i2c_emul_find() to work with of-platdata.
98 */
99 struct dm_i2c_chip {
100 uint chip_addr;
101 uint offset_len;
102 uint flags;
103 uint chip_addr_offset_mask;
104 #ifdef CONFIG_SANDBOX
105 struct udevice *emul;
106 bool test_mode;
107 int emul_idx;
108 #endif
109 };
110
111 /**
112 * struct dm_i2c_bus- information about an i2c bus
113 *
114 * An I2C bus contains 0 or more chips on it, each at its own address. The
115 * bus can operate at different speeds (measured in Hz, typically 100KHz
116 * or 400KHz).
117 *
118 * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the
119 * I2C bus udevice.
120 *
121 * @speed_hz: Bus speed in hertz (typically 100000)
122 * @max_transaction_bytes: Maximal size of single I2C transfer
123 */
124 struct dm_i2c_bus {
125 int speed_hz;
126 int max_transaction_bytes;
127 };
128
129 /*
130 * Not all of these flags are implemented in the U-Boot API
131 */
132 enum dm_i2c_msg_flags {
133 I2C_M_TEN = 0x0010, /* ten-bit chip address */
134 I2C_M_RD = 0x0001, /* read data, from slave to master */
135 I2C_M_STOP = 0x8000, /* send stop after this message */
136 I2C_M_NOSTART = 0x4000, /* no start before this message */
137 I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */
138 I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */
139 I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */
140 I2C_M_RECV_LEN = 0x0400, /* length is first received byte */
141 };
142
143 /**
144 * struct i2c_msg - an I2C message
145 *
146 * @addr: Slave address
147 * @flags: Flags (see enum dm_i2c_msg_flags)
148 * @len: Length of buffer in bytes, may be 0 for a probe
149 * @buf: Buffer to send/receive, or NULL if no data
150 */
151 struct i2c_msg {
152 uint addr;
153 uint flags;
154 uint len;
155 u8 *buf;
156 };
157
158 /**
159 * struct i2c_msg_list - a list of I2C messages
160 *
161 * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem
162 * appropriate in U-Boot.
163 *
164 * @msg: Pointer to i2c_msg array
165 * @nmsgs: Number of elements in the array
166 */
167 struct i2c_msg_list {
168 struct i2c_msg *msgs;
169 uint nmsgs;
170 };
171
172 /**
173 * dm_i2c_read() - read bytes from an I2C chip
174 *
175 * To obtain an I2C device (called a 'chip') given the I2C bus address you
176 * can use i2c_get_chip(). To obtain a bus by bus number use
177 * uclass_get_device_by_seq(UCLASS_I2C, <bus number>).
178 *
179 * To set the address length of a devce use i2c_set_addr_len(). It
180 * defaults to 1.
181 *
182 * @dev: Chip to read from
183 * @offset: Offset within chip to start reading
184 * @buffer: Place to put data
185 * @len: Number of bytes to read
186 *
187 * Return: 0 on success, -ve on failure
188 */
189 int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len);
190
191 /**
192 * dm_i2c_write() - write bytes to an I2C chip
193 *
194 * See notes for dm_i2c_read() above.
195 *
196 * @dev: Chip to write to
197 * @offset: Offset within chip to start writing
198 * @buffer: Buffer containing data to write
199 * @len: Number of bytes to write
200 *
201 * Return: 0 on success, -ve on failure
202 */
203 int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
204 int len);
205
206 /**
207 * dm_i2c_probe() - probe a particular chip address
208 *
209 * This can be useful to check for the existence of a chip on the bus.
210 * It is typically implemented by writing the chip address to the bus
211 * and checking that the chip replies with an ACK.
212 *
213 * @bus: Bus to probe
214 * @chip_addr: 7-bit address to probe (10-bit and others are not supported)
215 * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags)
216 * @devp: Returns the device found, or NULL if none
217 * Return: 0 if a chip was found at that address, -ve if not
218 */
219 int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
220 struct udevice **devp);
221
222 /**
223 * dm_i2c_reg_read() - Read a value from an I2C register
224 *
225 * This reads a single value from the given address in an I2C chip
226 *
227 * @dev: Device to use for transfer
228 * @addr: Address to read from
229 * Return: value read, or -ve on error
230 */
231 int dm_i2c_reg_read(struct udevice *dev, uint offset);
232
233 /**
234 * dm_i2c_reg_write() - Write a value to an I2C register
235 *
236 * This writes a single value to the given address in an I2C chip
237 *
238 * @dev: Device to use for transfer
239 * @addr: Address to write to
240 * @val: Value to write (normally a byte)
241 * Return: 0 on success, -ve on error
242 */
243 int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val);
244
245 /**
246 * dm_i2c_reg_clrset() - Apply bitmask to an I2C register
247 *
248 * Read value, apply bitmask and write modified value back to the
249 * given address in an I2C chip
250 *
251 * @dev: Device to use for transfer
252 * @offset: Address for the R/W operation
253 * @clr: Bitmask of bits that should be cleared
254 * @set: Bitmask of bits that should be set
255 * Return: 0 on success, -ve on error
256 */
257 int dm_i2c_reg_clrset(struct udevice *dev, uint offset, u32 clr, u32 set);
258
259 /**
260 * dm_i2c_xfer() - Transfer messages over I2C
261 *
262 * This transfers a raw message. It is best to use dm_i2c_reg_read/write()
263 * instead.
264 *
265 * @dev: Device to use for transfer
266 * @msg: List of messages to transfer
267 * @nmsgs: Number of messages to transfer
268 * Return: 0 on success, -ve on error
269 */
270 int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs);
271
272 /**
273 * dm_i2c_set_bus_speed() - set the speed of a bus
274 *
275 * @bus: Bus to adjust
276 * @speed: Requested speed in Hz
277 * Return: 0 if OK, -EINVAL for invalid values
278 */
279 int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
280
281 /**
282 * dm_i2c_get_bus_speed() - get the speed of a bus
283 *
284 * @bus: Bus to check
285 * Return: speed of selected I2C bus in Hz, -ve on error
286 */
287 int dm_i2c_get_bus_speed(struct udevice *bus);
288
289 /**
290 * i2c_set_chip_flags() - set flags for a chip
291 *
292 * Typically addresses are 7 bits, but for 10-bit addresses you should set
293 * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing.
294 *
295 * @dev: Chip to adjust
296 * @flags: New flags
297 * Return: 0 if OK, -EINVAL if value is unsupported, other -ve value on error
298 */
299 int i2c_set_chip_flags(struct udevice *dev, uint flags);
300
301 /**
302 * i2c_get_chip_flags() - get flags for a chip
303 *
304 * @dev: Chip to check
305 * @flagsp: Place to put flags
306 * Return: 0 if OK, other -ve value on error
307 */
308 int i2c_get_chip_flags(struct udevice *dev, uint *flagsp);
309
310 /**
311 * i2c_set_offset_len() - set the offset length for a chip
312 *
313 * The offset used to access a chip may be up to 4 bytes long. Typically it
314 * is only 1 byte, which is enough for chips with 256 bytes of memory or
315 * registers. The default value is 1, but you can call this function to
316 * change it.
317 *
318 * @offset_len: New offset length value (typically 1 or 2)
319 */
320 int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
321
322 /**
323 * i2c_get_offset_len() - get the offset length for a chip
324 *
325 * @return: Current offset length value (typically 1 or 2)
326 */
327 int i2c_get_chip_offset_len(struct udevice *dev);
328
329 /**
330 * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset
331 *
332 * Some devices listen on multiple chip addresses to achieve larger offsets
333 * than their single or multiple byte offsets would allow for. You can use this
334 * function to set the bits that are valid to be used for offset overflow.
335 *
336 * @mask: The mask to be used for high offset bits within address
337 * Return: 0 if OK, other -ve value on error
338 */
339 int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask);
340
341 /*
342 * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset
343 *
344 * Return: current chip addr offset mask
345 */
346 uint i2c_get_chip_addr_offset_mask(struct udevice *dev);
347
348 /**
349 * i2c_deblock() - recover a bus that is in an unknown state
350 *
351 * See the deblock() method in 'struct dm_i2c_ops' for full information
352 *
353 * @bus: Bus to recover
354 * Return: 0 if OK, -ve on error
355 */
356 int i2c_deblock(struct udevice *bus);
357
358 /**
359 * i2c_deblock_gpio_loop() - recover a bus from an unknown state by toggling SDA/SCL
360 *
361 * This is the inner logic used for toggling I2C SDA/SCL lines as GPIOs
362 * for deblocking the I2C bus.
363 *
364 * @sda_pin: SDA GPIO
365 * @scl_pin: SCL GPIO
366 * @scl_count: Number of SCL clock cycles generated to deblock SDA
367 * @start_count:Number of I2C start conditions sent after deblocking SDA
368 * @delay: Delay between SCL clock line changes
369 * Return: 0 if OK, -ve on error
370 */
371 struct gpio_desc;
372 int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, struct gpio_desc *scl_pin,
373 unsigned int scl_count, unsigned int start_count,
374 unsigned int delay);
375
376 /**
377 * struct dm_i2c_ops - driver operations for I2C uclass
378 *
379 * Drivers should support these operations unless otherwise noted. These
380 * operations are intended to be used by uclass code, not directly from
381 * other code.
382 */
383 struct dm_i2c_ops {
384 /**
385 * xfer() - transfer a list of I2C messages
386 *
387 * @bus: Bus to read from
388 * @msg: List of messages to transfer
389 * @nmsgs: Number of messages in the list
390 * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte,
391 * -ECOMM if the speed cannot be supported, -EPROTO if the chip
392 * flags cannot be supported, other -ve value on some other error
393 */
394 int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs);
395
396 /**
397 * probe_chip() - probe for the presense of a chip address
398 *
399 * This function is optional. If omitted, the uclass will send a zero
400 * length message instead.
401 *
402 * @bus: Bus to probe
403 * @chip_addr: Chip address to probe
404 * @chip_flags: Probe flags (enum dm_i2c_chip_flags)
405 * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back
406 * to default probem other -ve value on error
407 */
408 int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags);
409
410 /**
411 * set_bus_speed() - set the speed of a bus (optional)
412 *
413 * The bus speed value will be updated by the uclass if this function
414 * does not return an error. This method is optional - if it is not
415 * provided then the driver can read the speed from
416 * dev_get_uclass_priv(bus)->speed_hz
417 *
418 * @bus: Bus to adjust
419 * @speed: Requested speed in Hz
420 * @return 0 if OK, -EINVAL for invalid values
421 */
422 int (*set_bus_speed)(struct udevice *bus, unsigned int speed);
423
424 /**
425 * get_bus_speed() - get the speed of a bus (optional)
426 *
427 * Normally this can be provided by the uclass, but if you want your
428 * driver to check the bus speed by looking at the hardware, you can
429 * implement that here. This method is optional. This method would
430 * normally be expected to return dev_get_uclass_priv(bus)->speed_hz.
431 *
432 * @bus: Bus to check
433 * @return speed of selected I2C bus in Hz, -ve on error
434 */
435 int (*get_bus_speed)(struct udevice *bus);
436
437 /**
438 * set_flags() - set the flags for a chip (optional)
439 *
440 * This is generally implemented by the uclass, but drivers can
441 * check the value to ensure that unsupported options are not used.
442 * This method is optional. If provided, this method will always be
443 * called when the flags change.
444 *
445 * @dev: Chip to adjust
446 * @flags: New flags value
447 * @return 0 if OK, -EINVAL if value is unsupported
448 */
449 int (*set_flags)(struct udevice *dev, uint flags);
450
451 /**
452 * deblock() - recover a bus that is in an unknown state
453 *
454 * I2C is a synchronous protocol and resets of the processor in the
455 * middle of an access can block the I2C Bus until a powerdown of
456 * the full unit is done. This is because slaves can be stuck
457 * waiting for addition bus transitions for a transaction that will
458 * never complete. Resetting the I2C master does not help. The only
459 * way is to force the bus through a series of transitions to make
460 * sure that all slaves are done with the transaction. This method
461 * performs this 'deblocking' if support by the driver.
462 *
463 * This method is optional.
464 */
465 int (*deblock)(struct udevice *bus);
466 };
467
468 #define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops)
469
470 /**
471 * struct i2c_mux_ops - operations for an I2C mux
472 *
473 * The current mux state is expected to be stored in the mux itself since
474 * it is the only thing that knows how to make things work. The mux can
475 * record the current state and then avoid switching unless it is necessary.
476 * So select() can be skipped if the mux is already in the correct state.
477 * Also deselect() can be made a nop if required.
478 */
479 struct i2c_mux_ops {
480 /**
481 * select() - select one of of I2C buses attached to a mux
482 *
483 * This will be called when there is no bus currently selected by the
484 * mux. This method does not need to deselect the old bus since
485 * deselect() will be already have been called if necessary.
486 *
487 * @mux: Mux device
488 * @bus: I2C bus to select
489 * @channel: Channel number correponding to the bus to select
490 * @return 0 if OK, -ve on error
491 */
492 int (*select)(struct udevice *mux, struct udevice *bus, uint channel);
493
494 /**
495 * deselect() - select one of of I2C buses attached to a mux
496 *
497 * This is used to deselect the currently selected I2C bus.
498 *
499 * @mux: Mux device
500 * @bus: I2C bus to deselect
501 * @channel: Channel number correponding to the bus to deselect
502 * @return 0 if OK, -ve on error
503 */
504 int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel);
505 };
506
507 #define i2c_mux_get_ops(dev) ((struct i2c_mux_ops *)(dev)->driver->ops)
508
509 /**
510 * i2c_get_chip() - get a device to use to access a chip on a bus
511 *
512 * This returns the device for the given chip address. The device can then
513 * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc.
514 *
515 * @bus: Bus to examine
516 * @chip_addr: Chip address for the new device
517 * @offset_len: Length of a register offset in bytes (normally 1)
518 * @devp: Returns pointer to new device if found or -ENODEV if not
519 * found
520 */
521 int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len,
522 struct udevice **devp);
523
524 /**
525 * i2c_get_chip_for_busnum() - get a device to use to access a chip on
526 * a bus number
527 *
528 * This returns the device for the given chip address on a particular bus
529 * number.
530 *
531 * @busnum: Bus number to examine
532 * @chip_addr: Chip address for the new device
533 * @offset_len: Length of a register offset in bytes (normally 1)
534 * @devp: Returns pointer to new device if found or -ENODEV if not
535 * found
536 */
537 int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len,
538 struct udevice **devp);
539
540 /**
541 * i2c_chip_of_to_plat() - Decode standard I2C platform data
542 *
543 * This decodes the chip address from a device tree node and puts it into
544 * its dm_i2c_chip structure. This should be called in your driver's
545 * of_to_plat() method.
546 *
547 * @blob: Device tree blob
548 * @node: Node offset to read from
549 * @spi: Place to put the decoded information
550 */
551 int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip);
552
553 /**
554 * i2c_dump_msgs() - Dump a list of I2C messages
555 *
556 * This may be useful for debugging.
557 *
558 * @msg: Message list to dump
559 * @nmsgs: Number of messages
560 */
561 void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs);
562
563 /**
564 * i2c_emul_find() - Find an emulator for an i2c sandbox device
565 *
566 * This looks at the device's 'emul' phandle
567 *
568 * @dev: Device to find an emulator for
569 * @emulp: Returns the associated emulator, if found *
570 * Return: 0 if OK, -ENOENT or -ENODEV if not found
571 */
572 int i2c_emul_find(struct udevice *dev, struct udevice **emulp);
573
574 /**
575 * i2c_emul_set_idx() - Set the emulator index for an i2c sandbox device
576 *
577 * With of-platdata we cannot find the emulator using the device tree, so rely
578 * on the bind() method of each i2c driver calling this function to tell us
579 * the of-platdata idx of the emulator
580 *
581 * @dev: i2c device to set the emulator for
582 * @emul_idx: of-platdata index for that emulator
583 */
584 void i2c_emul_set_idx(struct udevice *dev, int emul_idx);
585
586 /**
587 * i2c_emul_get_device() - Find the device being emulated
588 *
589 * Given an emulator this returns the associated device
590 *
591 * @emul: Emulator for the device
592 * Return: device that @emul is emulating
593 */
594 struct udevice *i2c_emul_get_device(struct udevice *emul);
595
596 /* ACPI operations for generic I2C devices */
597 extern struct acpi_ops i2c_acpi_ops;
598
599 /**
600 * acpi_i2c_of_to_plat() - Read properties intended for ACPI
601 *
602 * This reads the generic I2C properties from the device tree, so that these
603 * can be used to create ACPI information for the device.
604 *
605 * See the i2c/generic-acpi.txt binding file for information about the
606 * properties.
607 *
608 * @dev: I2C device to process
609 * Return: 0 if OK, -EINVAL if acpi,hid is not present
610 */
611 int acpi_i2c_of_to_plat(struct udevice *dev);
612
613 #ifdef CONFIG_SYS_I2C_EARLY_INIT
614 void i2c_early_init_f(void);
615 #endif
616
617 #if !CONFIG_IS_ENABLED(DM_I2C)
618
619 /*
620 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
621 *
622 * The implementation MUST NOT use static or global variables if the
623 * I2C routines are used to read SDRAM configuration information
624 * because this is done before the memories are initialized. Limited
625 * use of stack-based variables are OK (the initial stack size is
626 * limited).
627 *
628 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
629 */
630
631 /*
632 * Configuration items.
633 */
634 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
635
636 #if !defined(CFG_SYS_I2C_MAX_HOPS)
637 /* no muxes used bus = i2c adapters */
638 #define CFG_SYS_I2C_DIRECT_BUS 1
639 #define CFG_SYS_I2C_MAX_HOPS 0
640 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
641 #else
642 /* we use i2c muxes */
643 #undef CFG_SYS_I2C_DIRECT_BUS
644 #endif
645
646 /* define the I2C bus number for RTC and DTT if not already done */
647 #if !defined(CFG_SYS_RTC_BUS_NUM)
648 #define CFG_SYS_RTC_BUS_NUM 0
649 #endif
650
651 struct i2c_adapter {
652 void (*init)(struct i2c_adapter *adap, int speed,
653 int slaveaddr);
654 int (*probe)(struct i2c_adapter *adap, uint8_t chip);
655 int (*read)(struct i2c_adapter *adap, uint8_t chip,
656 uint addr, int alen, uint8_t *buffer,
657 int len);
658 int (*write)(struct i2c_adapter *adap, uint8_t chip,
659 uint addr, int alen, uint8_t *buffer,
660 int len);
661 uint (*set_bus_speed)(struct i2c_adapter *adap,
662 uint speed);
663 int speed;
664 int waitdelay;
665 int slaveaddr;
666 int init_done;
667 int hwadapnr;
668 char *name;
669 };
670
671 #define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
672 _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
673 { \
674 .init = _init, \
675 .probe = _probe, \
676 .read = _read, \
677 .write = _write, \
678 .set_bus_speed = _set_speed, \
679 .speed = _speed, \
680 .slaveaddr = _slaveaddr, \
681 .init_done = 0, \
682 .hwadapnr = _hwadapnr, \
683 .name = #_name \
684 };
685
686 #define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
687 _set_speed, _speed, _slaveaddr, _hwadapnr) \
688 ll_entry_declare(struct i2c_adapter, _name, i2c) = \
689 U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
690 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
691
692 struct i2c_adapter *i2c_get_adapter(int index);
693
694 #ifndef CFG_SYS_I2C_DIRECT_BUS
695 struct i2c_mux {
696 int id;
697 char name[16];
698 };
699
700 struct i2c_next_hop {
701 struct i2c_mux mux;
702 uint8_t chip;
703 uint8_t channel;
704 };
705
706 struct i2c_bus_hose {
707 int adapter;
708 struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS];
709 };
710 #define I2C_NULL_HOP {{-1, ""}, 0, 0}
711 extern struct i2c_bus_hose i2c_bus[];
712
713 #define I2C_ADAPTER(bus) i2c_bus[bus].adapter
714 #else
715 #define I2C_ADAPTER(bus) bus
716 #endif
717 #define I2C_BUS gd->cur_i2c_bus
718
719 #define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
720 #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
721 #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
722
723 #ifndef CFG_SYS_I2C_DIRECT_BUS
724 #define I2C_MUX_PCA9540_ID 1
725 #define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
726 #define I2C_MUX_PCA9542_ID 2
727 #define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
728 #define I2C_MUX_PCA9544_ID 3
729 #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
730 #define I2C_MUX_PCA9547_ID 4
731 #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
732 #define I2C_MUX_PCA9548_ID 5
733 #define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"}
734 #endif
735
736 #ifndef I2C_SOFT_DECLARATIONS
737 # if (defined(CONFIG_AT91RM9200) || \
738 defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
739 defined(CONFIG_AT91SAM9263))
740 # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
741 # else
742 # define I2C_SOFT_DECLARATIONS
743 # endif
744 #endif
745
746 /*
747 * Initialization, must be called once on start up, may be called
748 * repeatedly to change the speed and slave addresses.
749 */
750 void i2c_init(int speed, int slaveaddr);
751 void i2c_init_board(void);
752
753 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
754 /*
755 * i2c_get_bus_num:
756 *
757 * Returns index of currently active I2C bus. Zero-based.
758 */
759 unsigned int i2c_get_bus_num(void);
760
761 /*
762 * i2c_set_bus_num:
763 *
764 * Change the active I2C bus. Subsequent read/write calls will
765 * go to this one.
766 *
767 * bus - bus index, zero based
768 *
769 * Returns: 0 on success, not 0 on failure
770 *
771 */
772 int i2c_set_bus_num(unsigned int bus);
773
774 /*
775 * i2c_init_all():
776 *
777 * Initializes all I2C adapters in the system. All i2c_adap structures must
778 * be initialized beforehead with function pointers and data, including
779 * speed and slaveaddr. Returns 0 on success, non-0 on failure.
780 */
781 void i2c_init_all(void);
782
783 /*
784 * Probe the given I2C chip address. Returns 0 if a chip responded,
785 * not 0 on failure.
786 */
787 int i2c_probe(uint8_t chip);
788
789 /*
790 * Read/Write interface:
791 * chip: I2C chip address, range 0..127
792 * addr: Memory (register) address within the chip
793 * alen: Number of bytes to use for addr (typically 1, 2 for larger
794 * memories, 0 for register type devices with only one
795 * register)
796 * buffer: Where to read/write the data
797 * len: How many bytes to read/write
798 *
799 * Returns: 0 on success, not 0 on failure
800 */
801 int i2c_read(uint8_t chip, unsigned int addr, int alen,
802 uint8_t *buffer, int len);
803
804 int i2c_write(uint8_t chip, unsigned int addr, int alen,
805 uint8_t *buffer, int len);
806
807 /*
808 * Utility routines to read/write registers.
809 */
810 uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
811
812 void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
813
814 /*
815 * i2c_set_bus_speed:
816 *
817 * Change the speed of the active I2C bus
818 *
819 * speed - bus speed in Hz
820 *
821 * Returns: new bus speed
822 *
823 */
824 unsigned int i2c_set_bus_speed(unsigned int speed);
825
826 /*
827 * i2c_get_bus_speed:
828 *
829 * Returns speed of currently active I2C bus in Hz
830 */
831
832 unsigned int i2c_get_bus_speed(void);
833
834 #else
835
836 /*
837 * Probe the given I2C chip address. Returns 0 if a chip responded,
838 * not 0 on failure.
839 */
840 int i2c_probe(uchar chip);
841
842 /*
843 * Read/Write interface:
844 * chip: I2C chip address, range 0..127
845 * addr: Memory (register) address within the chip
846 * alen: Number of bytes to use for addr (typically 1, 2 for larger
847 * memories, 0 for register type devices with only one
848 * register)
849 * buffer: Where to read/write the data
850 * len: How many bytes to read/write
851 *
852 * Returns: 0 on success, not 0 on failure
853 */
854 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
855 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
856
857 /*
858 * Utility routines to read/write registers.
859 */
i2c_reg_read(u8 addr,u8 reg)860 static inline u8 i2c_reg_read(u8 addr, u8 reg)
861 {
862 u8 buf;
863
864 #ifdef DEBUG
865 printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
866 #endif
867
868 i2c_read(addr, reg, 1, &buf, 1);
869
870 return buf;
871 }
872
i2c_reg_write(u8 addr,u8 reg,u8 val)873 static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
874 {
875 #ifdef DEBUG
876 printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
877 __func__, addr, reg, val);
878 #endif
879
880 i2c_write(addr, reg, 1, &val, 1);
881 }
882
883 /*
884 * Functions for setting the current I2C bus and its speed
885 */
886
887 /*
888 * i2c_set_bus_num:
889 *
890 * Change the active I2C bus. Subsequent read/write calls will
891 * go to this one.
892 *
893 * bus - bus index, zero based
894 *
895 * Returns: 0 on success, not 0 on failure
896 *
897 */
898 int i2c_set_bus_num(unsigned int bus);
899
900 /*
901 * i2c_get_bus_num:
902 *
903 * Returns index of currently active I2C bus. Zero-based.
904 */
905
906 unsigned int i2c_get_bus_num(void);
907
908 /*
909 * i2c_set_bus_speed:
910 *
911 * Change the speed of the active I2C bus
912 *
913 * speed - bus speed in Hz
914 *
915 * Returns: 0 on success, not 0 on failure
916 *
917 */
918 int i2c_set_bus_speed(unsigned int);
919
920 /*
921 * i2c_get_bus_speed:
922 *
923 * Returns speed of currently active I2C bus in Hz
924 */
925
926 unsigned int i2c_get_bus_speed(void);
927 #endif /* CONFIG_SYS_I2C_LEGACY */
928
929 /*
930 * only for backwardcompatibility, should go away if we switched
931 * completely to new multibus support.
932 */
933 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS)
934 # if !defined(CFG_SYS_MAX_I2C_BUS)
935 # define CFG_SYS_MAX_I2C_BUS 2
936 # endif
937 # define I2C_MULTI_BUS 1
938 #else
939 # define CFG_SYS_MAX_I2C_BUS 1
940 # define I2C_MULTI_BUS 0
941 #endif
942
943 /* NOTE: These two functions MUST be always_inline to avoid code growth! */
944 static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
I2C_GET_BUS(void)945 static inline unsigned int I2C_GET_BUS(void)
946 {
947 return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
948 }
949
950 static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
I2C_SET_BUS(unsigned int bus)951 static inline void I2C_SET_BUS(unsigned int bus)
952 {
953 if (I2C_MULTI_BUS)
954 i2c_set_bus_num(bus);
955 }
956
957 /* Multi I2C definitions */
958 enum {
959 I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
960 I2C_8, I2C_9, I2C_10,
961 };
962
963 /**
964 * Get FDT values for i2c bus.
965 *
966 * @param blob Device tree blbo
967 * Return: the number of I2C bus
968 */
969 void board_i2c_init(const void *blob);
970
971 /**
972 * Find the I2C bus number by given a FDT I2C node.
973 *
974 * @param blob Device tree blbo
975 * @param node FDT I2C node to find
976 * Return: the number of I2C bus (zero based), or -1 on error
977 */
978 int i2c_get_bus_num_fdt(int node);
979
980 /**
981 * Reset the I2C bus represented by the given a FDT I2C node.
982 *
983 * @param blob Device tree blbo
984 * @param node FDT I2C node to find
985 * Return: 0 if port was reset, -1 if not found
986 */
987 int i2c_reset_port_fdt(const void *blob, int node);
988
989 #endif /* !CONFIG_DM_I2C */
990
991 #endif /* _I2C_H_ */
992