1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008
4 * Texas Instruments, <www.ti.com>
5 *
6 * Author :
7 * Manikandan Pillai <mani.pillai@ti.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/arch/mem.h> /* get mem tables */
17 #include <asm/arch/sys_proto.h>
18 #include <asm/bootm.h>
19 #include <asm/omap_common.h>
20
21 #include <i2c.h>
22 #include <linux/compiler.h>
23
24 extern omap3_sysinfo sysinfo;
25 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
26
27 #ifdef CONFIG_DISPLAY_CPUINFO
28 static char *rev_s[CPU_3XX_MAX_REV] = {
29 "1.0",
30 "2.0",
31 "2.1",
32 "3.0",
33 "3.1",
34 "UNKNOWN",
35 "UNKNOWN",
36 "3.1.2"};
37
38 /* this is the revision table for 37xx CPUs */
39 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
40 "1.0",
41 "1.1",
42 "1.2"};
43 #endif /* CONFIG_DISPLAY_CPUINFO */
44
omap_die_id(unsigned int * die_id)45 void omap_die_id(unsigned int *die_id)
46 {
47 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
48
49 die_id[0] = readl(&id_base->die_id_0);
50 die_id[1] = readl(&id_base->die_id_1);
51 die_id[2] = readl(&id_base->die_id_2);
52 die_id[3] = readl(&id_base->die_id_3);
53 }
54
55 /******************************************
56 * get_cpu_type(void) - extract cpu info
57 ******************************************/
get_cpu_type(void)58 static u32 get_cpu_type(void)
59 {
60 return readl(&ctrl_base->ctrl_omap_stat);
61 }
62
63 /******************************************
64 * get_cpu_id(void) - extract cpu id
65 * returns 0 for ES1.0, cpuid otherwise
66 ******************************************/
get_cpu_id(void)67 static u32 get_cpu_id(void)
68 {
69 struct ctrl_id *id_base;
70 u32 cpuid = 0;
71
72 /*
73 * On ES1.0 the IDCODE register is not exposed on L4
74 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
75 */
76 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
77 if ((cpuid & 0xf) == 0x0) {
78 return 0;
79 } else {
80 /* Decode the IDs on > ES1.0 */
81 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
82
83 cpuid = readl(&id_base->idcode);
84 }
85
86 return cpuid;
87 }
88
89 /******************************************
90 * get_cpu_family(void) - extract cpu info
91 ******************************************/
get_cpu_family(void)92 __used u32 get_cpu_family(void)
93 {
94 u16 hawkeye;
95 u32 cpu_family;
96 u32 cpuid = get_cpu_id();
97
98 if (cpuid == 0)
99 return CPU_OMAP34XX;
100
101 hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
102 switch (hawkeye) {
103 case HAWKEYE_OMAP34XX:
104 cpu_family = CPU_OMAP34XX;
105 break;
106 case HAWKEYE_AM35XX:
107 cpu_family = CPU_AM35XX;
108 break;
109 case HAWKEYE_OMAP36XX:
110 cpu_family = CPU_OMAP36XX;
111 break;
112 default:
113 cpu_family = CPU_OMAP34XX;
114 }
115
116 return cpu_family;
117 }
118
119 /******************************************
120 * get_cpu_rev(void) - extract version info
121 ******************************************/
get_cpu_rev(void)122 __used u32 get_cpu_rev(void)
123 {
124 u32 cpuid = get_cpu_id();
125
126 if (cpuid == 0)
127 return CPU_3XX_ES10;
128 else
129 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
130 }
131
132 /*****************************************************************
133 * get_sku_id(void) - read sku_id to get info on max clock rate
134 *****************************************************************/
get_sku_id(void)135 static u32 get_sku_id(void)
136 {
137 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
138 return readl(&id_base->sku_id) & SKUID_CLK_MASK;
139 }
140
141 /*************************************************************************
142 * get_board_rev() - setup to pass kernel board revision information
143 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
144 *************************************************************************/
145 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)146 u32 __weak get_board_rev(void)
147 {
148 return 0x20;
149 }
150 #endif
151
152 /********************************************************
153 * get_base(); get upper addr of current execution
154 *******************************************************/
get_base(void)155 static u32 get_base(void)
156 {
157 u32 val;
158
159 __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
160 val &= 0xF0000000;
161 val >>= 28;
162 return val;
163 }
164
165 /********************************************************
166 * is_running_in_flash() - tell if currently running in
167 * FLASH.
168 *******************************************************/
is_running_in_flash(void)169 u32 is_running_in_flash(void)
170 {
171 if (get_base() < 4)
172 return 1; /* in FLASH */
173
174 return 0; /* running in SRAM or SDRAM */
175 }
176
177 /********************************************************
178 * is_running_in_sram() - tell if currently running in
179 * SRAM.
180 *******************************************************/
is_running_in_sram(void)181 u32 is_running_in_sram(void)
182 {
183 if (get_base() == 4)
184 return 1; /* in SRAM */
185
186 return 0; /* running in FLASH or SDRAM */
187 }
188
189 /********************************************************
190 * is_running_in_sdram() - tell if currently running in
191 * SDRAM.
192 *******************************************************/
is_running_in_sdram(void)193 u32 is_running_in_sdram(void)
194 {
195 if (get_base() > 4)
196 return 1; /* in SDRAM */
197
198 return 0; /* running in SRAM or FLASH */
199 }
200
201 /***************************************************************
202 * get_boot_type() - Is this an XIP type device or a stream one
203 * bits 4-0 specify type. Bit 5 says mem/perif
204 ***************************************************************/
get_boot_type(void)205 u32 get_boot_type(void)
206 {
207 return (readl(&ctrl_base->status) & SYSBOOT_MASK);
208 }
209
210 #ifdef CONFIG_DISPLAY_CPUINFO
211 /**
212 * Print CPU information
213 */
print_cpuinfo(void)214 int print_cpuinfo (void)
215 {
216 char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
217
218 switch (get_cpu_family()) {
219 case CPU_OMAP34XX:
220 cpu_family_s = "OMAP";
221 switch (get_cpu_type()) {
222 case OMAP3503:
223 cpu_s = "3503";
224 break;
225 case OMAP3515:
226 cpu_s = "3515";
227 break;
228 case OMAP3525:
229 cpu_s = "3525";
230 break;
231 case OMAP3530:
232 cpu_s = "3530";
233 break;
234 default:
235 cpu_s = "35XX";
236 break;
237 }
238 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
239 (get_sku_id() == SKUID_CLK_720MHZ))
240 max_clk = "720 MHz";
241 else
242 max_clk = "600 MHz";
243
244 break;
245 case CPU_AM35XX:
246 cpu_family_s = "AM";
247 switch (get_cpu_type()) {
248 case AM3505:
249 cpu_s = "3505";
250 break;
251 case AM3517:
252 cpu_s = "3517";
253 break;
254 default:
255 cpu_s = "35XX";
256 break;
257 }
258 max_clk = "600 MHz";
259 break;
260 case CPU_OMAP36XX:
261 switch (get_cpu_type()) {
262 case AM3703:
263 cpu_family_s = "AM";
264 cpu_s = "3703";
265 max_clk = "800 MHz";
266 break;
267 case AM3703_1GHZ:
268 cpu_family_s = "AM";
269 cpu_s = "3703";
270 max_clk = "1 GHz";
271 break;
272 case AM3715:
273 cpu_family_s = "AM";
274 cpu_s = "3715";
275 max_clk = "800 MHz";
276 break;
277 case AM3715_1GHZ:
278 cpu_family_s = "AM";
279 cpu_s = "3715";
280 max_clk = "1 GHz";
281 break;
282 case OMAP3725:
283 cpu_family_s = "OMAP";
284 cpu_s = "3625/3725";
285 max_clk = "800 MHz";
286 break;
287 case OMAP3725_1GHZ:
288 cpu_family_s = "OMAP";
289 cpu_s = "3625/3725";
290 max_clk = "1 GHz";
291 break;
292 case OMAP3730:
293 cpu_family_s = "OMAP";
294 cpu_s = "3630/3730";
295 max_clk = "800 MHz";
296 break;
297 case OMAP3730_1GHZ:
298 cpu_family_s = "OMAP";
299 cpu_s = "3630/3730";
300 max_clk = "1 GHz";
301 break;
302 default:
303 cpu_family_s = "OMAP/AM";
304 cpu_s = "36XX/37XX";
305 max_clk = "1 GHz";
306 break;
307 }
308
309 break;
310 default:
311 cpu_family_s = "OMAP";
312 cpu_s = "35XX";
313 max_clk = "600 MHz";
314 }
315
316 switch (get_device_type()) {
317 case TST_DEVICE:
318 sec_s = "TST";
319 break;
320 case EMU_DEVICE:
321 sec_s = "EMU";
322 break;
323 case HS_DEVICE:
324 sec_s = "HS";
325 break;
326 case GP_DEVICE:
327 sec_s = "GP";
328 break;
329 default:
330 sec_s = "?";
331 }
332
333 if (CPU_OMAP36XX == get_cpu_family())
334 printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
335 cpu_family_s, cpu_s, sec_s,
336 rev_s_37xx[get_cpu_rev()], max_clk);
337 else
338 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
339 cpu_family_s, cpu_s, sec_s,
340 rev_s[get_cpu_rev()], max_clk);
341
342 return 0;
343 }
344 #endif /* CONFIG_DISPLAY_CPUINFO */
345