1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012,2015 Stephen Warren 4 */ 5 6 #ifndef _BCM2835_MBOX_H 7 #define _BCM2835_MBOX_H 8 9 #include <linux/compiler.h> 10 #include <asm/arch/base.h> 11 12 /* 13 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") 14 * and the ARM CPU. The ARM CPU is often thought of as the main CPU. 15 * However, the VideoCore actually controls the initial SoC boot, and hides 16 * much of the hardware behind a protocol. This protocol is transported 17 * using the SoC's mailbox hardware module. 18 * 19 * The mailbox hardware supports passing 32-bit values back and forth. 20 * Presumably by software convention of the firmware, the bottom 4 bits of the 21 * value are used to indicate a logical channel, and the upper 28 bits are the 22 * actual payload. Various channels exist using these simple raw messages. See 23 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an 24 * example, the messages on the power management channel are a bitmask of 25 * devices whose power should be enabled. 26 * 27 * The property mailbox channel passes messages that contain the (16-byte 28 * aligned) ARM physical address of a memory buffer. This buffer is passed to 29 * the VC for processing, is modified in-place by the VC, and the address then 30 * passed back to the ARM CPU as the response mailbox message to indicate 31 * request completion. The buffers have a generic and extensible format; each 32 * buffer contains a standard header, a list of "tags", and a terminating zero 33 * entry. Each tag contains an ID indicating its type, and length fields for 34 * generic parsing. With some limitations, an arbitrary set of tags may be 35 * combined together into a single message buffer. This file defines structs 36 * representing the header and many individual tag layouts and IDs. 37 */ 38 39 /* Raw mailbox HW */ 40 41 #define BCM2835_MBOX_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ 42 rpi_bcm283x_base + 0x0000b880; }) 43 44 struct bcm2835_mbox_regs { 45 u32 read; 46 u32 rsvd0[5]; 47 u32 mail0_status; 48 u32 mail0_config; 49 u32 write; 50 u32 rsvd1[5]; 51 u32 mail1_status; 52 u32 mail1_config; 53 }; 54 55 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 56 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 57 58 /* Lower 4-bits are channel ID */ 59 #define BCM2835_CHAN_MASK 0xf 60 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ 61 (chan & BCM2835_CHAN_MASK)) 62 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) 63 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) 64 65 /* Property mailbox buffer structures */ 66 67 #define BCM2835_MBOX_PROP_CHAN 8 68 69 /* All message buffers must start with this header */ 70 struct bcm2835_mbox_hdr { 71 u32 buf_size; 72 u32 code; 73 }; 74 75 #define BCM2835_MBOX_REQ_CODE 0 76 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 77 78 #define BCM2835_MBOX_INIT_HDR(_m_) { \ 79 memset((_m_), 0, sizeof(*(_m_))); \ 80 (_m_)->hdr.buf_size = sizeof(*(_m_)); \ 81 (_m_)->hdr.code = 0; \ 82 (_m_)->end_tag = 0; \ 83 } 84 85 /* 86 * A message buffer contains a list of tags. Each tag must also start with 87 * a standardized header. 88 */ 89 struct bcm2835_mbox_tag_hdr { 90 u32 tag; 91 u32 val_buf_size; 92 u32 val_len; 93 }; 94 95 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ 96 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 97 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 98 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ 99 } 100 101 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ 102 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 103 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 104 (_t_)->tag_hdr.val_len = 0; \ 105 } 106 107 /* When responding, the VC sets this bit in val_len to indicate a response */ 108 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 109 110 /* 111 * Below we define the ID and struct for many possible tags. This header only 112 * defines individual tag structs, not entire message structs, since in 113 * general an arbitrary set of tags may be combined into a single message. 114 * Clients of the mbox API are expected to define their own overall message 115 * structures by combining the header, a set of tags, and a terminating 116 * entry. For example, 117 * 118 * struct msg { 119 * struct bcm2835_mbox_hdr hdr; 120 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; 121 * ... perhaps other tags here ... 122 * u32 end_tag; 123 * }; 124 */ 125 126 #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 127 128 struct bcm2835_mbox_tag_get_board_rev { 129 struct bcm2835_mbox_tag_hdr tag_hdr; 130 union { 131 struct { 132 } req; 133 struct { 134 u32 rev; 135 } resp; 136 } body; 137 }; 138 139 #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 140 141 struct bcm2835_mbox_tag_get_mac_address { 142 struct bcm2835_mbox_tag_hdr tag_hdr; 143 union { 144 struct { 145 } req; 146 struct { 147 u8 mac[6]; 148 u8 pad[2]; 149 } resp; 150 } body; 151 }; 152 153 #define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004 154 155 struct bcm2835_mbox_tag_get_board_serial { 156 struct bcm2835_mbox_tag_hdr tag_hdr; 157 union { 158 struct __packed { 159 u64 serial; 160 } resp; 161 } body; 162 }; 163 164 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 165 166 struct bcm2835_mbox_tag_get_arm_mem { 167 struct bcm2835_mbox_tag_hdr tag_hdr; 168 union { 169 struct { 170 } req; 171 struct { 172 u32 mem_base; 173 u32 mem_size; 174 } resp; 175 } body; 176 }; 177 178 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0 179 #define BCM2835_MBOX_POWER_DEVID_UART0 1 180 #define BCM2835_MBOX_POWER_DEVID_UART1 2 181 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 182 #define BCM2835_MBOX_POWER_DEVID_I2C0 4 183 #define BCM2835_MBOX_POWER_DEVID_I2C1 5 184 #define BCM2835_MBOX_POWER_DEVID_I2C2 6 185 #define BCM2835_MBOX_POWER_DEVID_SPI 7 186 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 187 188 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) 189 /* Device doesn't exist */ 190 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) 191 192 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 193 194 struct bcm2835_mbox_tag_get_power_state { 195 struct bcm2835_mbox_tag_hdr tag_hdr; 196 union { 197 struct { 198 u32 device_id; 199 } req; 200 struct { 201 u32 device_id; 202 u32 state; 203 } resp; 204 } body; 205 }; 206 207 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 208 209 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) 210 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) 211 212 struct bcm2835_mbox_tag_set_power_state { 213 struct bcm2835_mbox_tag_hdr tag_hdr; 214 union { 215 struct { 216 u32 device_id; 217 u32 state; 218 } req; 219 struct { 220 u32 device_id; 221 u32 state; 222 } resp; 223 } body; 224 }; 225 226 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 227 #define BCM2835_MBOX_TAG_GET_MAX_CLOCK_RATE 0x00030004 228 #define BCM2835_MBOX_TAG_GET_MIN_CLOCK_RATE 0x00030007 229 230 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 231 #define BCM2835_MBOX_CLOCK_ID_UART 2 232 #define BCM2835_MBOX_CLOCK_ID_ARM 3 233 #define BCM2835_MBOX_CLOCK_ID_CORE 4 234 #define BCM2835_MBOX_CLOCK_ID_V3D 5 235 #define BCM2835_MBOX_CLOCK_ID_H264 6 236 #define BCM2835_MBOX_CLOCK_ID_ISP 7 237 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8 238 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9 239 #define BCM2835_MBOX_CLOCK_ID_PWM 10 240 #define BCM2835_MBOX_CLOCK_ID_EMMC2 12 241 242 struct bcm2835_mbox_tag_get_clock_rate { 243 struct bcm2835_mbox_tag_hdr tag_hdr; 244 union { 245 struct { 246 u32 clock_id; 247 } req; 248 struct { 249 u32 clock_id; 250 u32 rate_hz; 251 } resp; 252 } body; 253 }; 254 255 #define BCM2835_MBOX_TAG_SET_SDHOST_CLOCK 0x00038042 256 257 struct bcm2835_mbox_tag_set_sdhost_clock { 258 struct bcm2835_mbox_tag_hdr tag_hdr; 259 union { 260 struct { 261 u32 rate_hz; 262 } req; 263 struct { 264 u32 rate_hz; 265 u32 rate_1; 266 u32 rate_2; 267 } resp; 268 } body; 269 }; 270 271 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 272 273 struct bcm2835_mbox_tag_allocate_buffer { 274 struct bcm2835_mbox_tag_hdr tag_hdr; 275 union { 276 struct { 277 u32 alignment; 278 } req; 279 struct { 280 u32 fb_address; 281 u32 fb_size; 282 } resp; 283 } body; 284 }; 285 286 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 287 288 struct bcm2835_mbox_tag_release_buffer { 289 struct bcm2835_mbox_tag_hdr tag_hdr; 290 union { 291 struct { 292 } req; 293 struct { 294 } resp; 295 } body; 296 }; 297 298 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 299 300 struct bcm2835_mbox_tag_blank_screen { 301 struct bcm2835_mbox_tag_hdr tag_hdr; 302 union { 303 struct { 304 /* bit 0 means on, other bots reserved */ 305 u32 state; 306 } req; 307 struct { 308 u32 state; 309 } resp; 310 } body; 311 }; 312 313 /* Physical means output signal */ 314 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 315 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 316 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 317 318 struct bcm2835_mbox_tag_physical_w_h { 319 struct bcm2835_mbox_tag_hdr tag_hdr; 320 union { 321 /* req not used for get */ 322 struct { 323 u32 width; 324 u32 height; 325 } req; 326 struct { 327 u32 width; 328 u32 height; 329 } resp; 330 } body; 331 }; 332 333 /* Virtual means display buffer */ 334 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 335 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 336 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 337 338 struct bcm2835_mbox_tag_virtual_w_h { 339 struct bcm2835_mbox_tag_hdr tag_hdr; 340 union { 341 /* req not used for get */ 342 struct { 343 u32 width; 344 u32 height; 345 } req; 346 struct { 347 u32 width; 348 u32 height; 349 } resp; 350 } body; 351 }; 352 353 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 354 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 355 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 356 357 struct bcm2835_mbox_tag_depth { 358 struct bcm2835_mbox_tag_hdr tag_hdr; 359 union { 360 /* req not used for get */ 361 struct { 362 u32 bpp; 363 } req; 364 struct { 365 u32 bpp; 366 } resp; 367 } body; 368 }; 369 370 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 371 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006 372 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 373 374 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0 375 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1 376 377 struct bcm2835_mbox_tag_pixel_order { 378 struct bcm2835_mbox_tag_hdr tag_hdr; 379 union { 380 /* req not used for get */ 381 struct { 382 u32 order; 383 } req; 384 struct { 385 u32 order; 386 } resp; 387 } body; 388 }; 389 390 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 391 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 392 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 393 394 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 395 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 396 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 397 398 struct bcm2835_mbox_tag_alpha_mode { 399 struct bcm2835_mbox_tag_hdr tag_hdr; 400 union { 401 /* req not used for get */ 402 struct { 403 u32 alpha; 404 } req; 405 struct { 406 u32 alpha; 407 } resp; 408 } body; 409 }; 410 411 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 412 413 struct bcm2835_mbox_tag_pitch { 414 struct bcm2835_mbox_tag_hdr tag_hdr; 415 union { 416 struct { 417 } req; 418 struct { 419 u32 pitch; 420 } resp; 421 } body; 422 }; 423 424 /* Offset of display window within buffer */ 425 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 426 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 427 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 428 429 struct bcm2835_mbox_tag_virtual_offset { 430 struct bcm2835_mbox_tag_hdr tag_hdr; 431 union { 432 /* req not used for get */ 433 struct { 434 u32 x; 435 u32 y; 436 } req; 437 struct { 438 u32 x; 439 u32 y; 440 } resp; 441 } body; 442 }; 443 444 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a 445 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a 446 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a 447 448 struct bcm2835_mbox_tag_overscan { 449 struct bcm2835_mbox_tag_hdr tag_hdr; 450 union { 451 /* req not used for get */ 452 struct { 453 u32 top; 454 u32 bottom; 455 u32 left; 456 u32 right; 457 } req; 458 struct { 459 u32 top; 460 u32 bottom; 461 u32 left; 462 u32 right; 463 } resp; 464 } body; 465 }; 466 467 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b 468 469 struct bcm2835_mbox_tag_get_palette { 470 struct bcm2835_mbox_tag_hdr tag_hdr; 471 union { 472 struct { 473 } req; 474 struct { 475 u32 data[1024]; 476 } resp; 477 } body; 478 }; 479 480 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b 481 482 struct bcm2835_mbox_tag_test_palette { 483 struct bcm2835_mbox_tag_hdr tag_hdr; 484 union { 485 struct { 486 u32 offset; 487 u32 num_entries; 488 u32 data[256]; 489 } req; 490 struct { 491 u32 is_invalid; 492 } resp; 493 } body; 494 }; 495 496 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b 497 498 struct bcm2835_mbox_tag_set_palette { 499 struct bcm2835_mbox_tag_hdr tag_hdr; 500 union { 501 struct { 502 u32 offset; 503 u32 num_entries; 504 u32 data[256]; 505 } req; 506 struct { 507 u32 is_invalid; 508 } resp; 509 } body; 510 }; 511 512 #define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 513 514 struct bcm2835_mbox_tag_pci_dev_addr { 515 struct bcm2835_mbox_tag_hdr tag_hdr; 516 union { 517 struct { 518 u32 dev_addr; 519 } req; 520 struct { 521 } resp; 522 } body; 523 }; 524 525 /* 526 * Pass a raw u32 message to the VC, and receive a raw u32 back. 527 * 528 * Returns 0 for success, any other value for error. 529 */ 530 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); 531 532 /* 533 * Pass a complete property-style buffer to the VC, and wait until it has 534 * been processed. 535 * 536 * This function expects a pointer to the mbox_hdr structure in an attempt 537 * to ensure some degree of type safety. However, some number of tags and 538 * a termination value are expected to immediately follow the header in 539 * memory, as required by the property protocol. 540 * 541 * Each struct bcm2835_mbox_hdr passed must be allocated with 542 * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate. 543 * 544 * Returns 0 for success, any other value for error. 545 */ 546 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); 547 548 #endif 549