1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _MV_DDR_TOPOLOGY_H
7 #define _MV_DDR_TOPOLOGY_H
8 
9 #define MAX_CS_NUM	4
10 
11 #if defined(CONFIG_DDR4)
12 enum mv_ddr_speed_bin {
13 	SPEED_BIN_DDR_1600J,
14 	SPEED_BIN_DDR_1600K,
15 	SPEED_BIN_DDR_1600L,
16 	SPEED_BIN_DDR_1866L,
17 	SPEED_BIN_DDR_1866M,
18 	SPEED_BIN_DDR_1866N,
19 	SPEED_BIN_DDR_2133N,
20 	SPEED_BIN_DDR_2133P,
21 	SPEED_BIN_DDR_2133R,
22 	SPEED_BIN_DDR_2400P,
23 	SPEED_BIN_DDR_2400R,
24 	SPEED_BIN_DDR_2400T,
25 	SPEED_BIN_DDR_2400U,
26 	SPEED_BIN_DDR_2666T,
27 	SPEED_BIN_DDR_2666U,
28 	SPEED_BIN_DDR_2666V,
29 	SPEED_BIN_DDR_2666W,
30 	SPEED_BIN_DDR_2933V,
31 	SPEED_BIN_DDR_2933W,
32 	SPEED_BIN_DDR_2933Y,
33 	SPEED_BIN_DDR_2933AA,
34 	SPEED_BIN_DDR_3200W,
35 	SPEED_BIN_DDR_3200AA,
36 	SPEED_BIN_DDR_3200AC
37 };
38 
39 enum mv_ddr_freq {
40 	MV_DDR_FREQ_LOW_FREQ,
41 	MV_DDR_FREQ_650,
42 	MV_DDR_FREQ_667,
43 	MV_DDR_FREQ_800,
44 	MV_DDR_FREQ_933,
45 	MV_DDR_FREQ_1066,
46 	MV_DDR_FREQ_900,
47 	MV_DDR_FREQ_1000,
48 	MV_DDR_FREQ_1050,
49 	MV_DDR_FREQ_1200,
50 	MV_DDR_FREQ_1333,
51 	MV_DDR_FREQ_1466,
52 	MV_DDR_FREQ_1600,
53 	MV_DDR_FREQ_LAST,
54 	MV_DDR_FREQ_SAR
55 };
56 
57 enum mv_ddr_speed_bin_timing {
58 	SPEED_BIN_TRCD,
59 	SPEED_BIN_TRP,
60 	SPEED_BIN_TRAS,
61 	SPEED_BIN_TRC,
62 	SPEED_BIN_TRRD0_5K,
63 	SPEED_BIN_TRRD1K,
64 	SPEED_BIN_TRRD2K,
65 	SPEED_BIN_TRRDL0_5K,
66 	SPEED_BIN_TRRDL1K,
67 	SPEED_BIN_TRRDL2K,
68 	SPEED_BIN_TPD,
69 	SPEED_BIN_TFAW0_5K,
70 	SPEED_BIN_TFAW1K,
71 	SPEED_BIN_TFAW2K,
72 	SPEED_BIN_TWTR,
73 	SPEED_BIN_TWTRL,
74 	SPEED_BIN_TRTP,
75 	SPEED_BIN_TWR,
76 	SPEED_BIN_TMOD,
77 	SPEED_BIN_TXPDLL,
78 	SPEED_BIN_TXSDLL,
79 	SPEED_BIN_TCCDL
80 };
81 #else /* CONFIG_DDR3 */
82 enum mv_ddr_speed_bin {
83 	SPEED_BIN_DDR_800D,
84 	SPEED_BIN_DDR_800E,
85 	SPEED_BIN_DDR_1066E,
86 	SPEED_BIN_DDR_1066F,
87 	SPEED_BIN_DDR_1066G,
88 	SPEED_BIN_DDR_1333F,
89 	SPEED_BIN_DDR_1333G,
90 	SPEED_BIN_DDR_1333H,
91 	SPEED_BIN_DDR_1333J,
92 	SPEED_BIN_DDR_1600G,
93 	SPEED_BIN_DDR_1600H,
94 	SPEED_BIN_DDR_1600J,
95 	SPEED_BIN_DDR_1600K,
96 	SPEED_BIN_DDR_1866J,
97 	SPEED_BIN_DDR_1866K,
98 	SPEED_BIN_DDR_1866L,
99 	SPEED_BIN_DDR_1866M,
100 	SPEED_BIN_DDR_2133K,
101 	SPEED_BIN_DDR_2133L,
102 	SPEED_BIN_DDR_2133M,
103 	SPEED_BIN_DDR_2133N,
104 
105 	SPEED_BIN_DDR_1333H_EXT,
106 	SPEED_BIN_DDR_1600K_EXT,
107 	SPEED_BIN_DDR_1866M_EXT
108 };
109 
110 enum mv_ddr_freq {
111 	MV_DDR_FREQ_LOW_FREQ,
112 	MV_DDR_FREQ_400,
113 	MV_DDR_FREQ_533,
114 	MV_DDR_FREQ_667,
115 	MV_DDR_FREQ_800,
116 	MV_DDR_FREQ_933,
117 	MV_DDR_FREQ_1066,
118 	MV_DDR_FREQ_311,
119 	MV_DDR_FREQ_333,
120 	MV_DDR_FREQ_467,
121 	MV_DDR_FREQ_850,
122 	MV_DDR_FREQ_600,
123 	MV_DDR_FREQ_300,
124 	MV_DDR_FREQ_900,
125 	MV_DDR_FREQ_360,
126 	MV_DDR_FREQ_1000,
127 	MV_DDR_FREQ_LAST,
128 	MV_DDR_FREQ_SAR
129 };
130 
131 enum mv_ddr_speed_bin_timing {
132 	SPEED_BIN_TRCD,
133 	SPEED_BIN_TRP,
134 	SPEED_BIN_TRAS,
135 	SPEED_BIN_TRC,
136 	SPEED_BIN_TRRD1K,
137 	SPEED_BIN_TRRD2K,
138 	SPEED_BIN_TPD,
139 	SPEED_BIN_TFAW1K,
140 	SPEED_BIN_TFAW2K,
141 	SPEED_BIN_TWTR,
142 	SPEED_BIN_TRTP,
143 	SPEED_BIN_TWR,
144 	SPEED_BIN_TMOD,
145 	SPEED_BIN_TXPDLL,
146 	SPEED_BIN_TXSDLL
147 };
148 #endif /* CONFIG_DDR4 */
149 
150 /* ddr bus masks */
151 #define BUS_MASK_32BIT			0xf
152 #define BUS_MASK_32BIT_ECC		0x1f
153 #define BUS_MASK_16BIT			0x3
154 #define BUS_MASK_16BIT_ECC		0x13
155 #define BUS_MASK_16BIT_ECC_PUP3		0xb
156 #define MV_DDR_64BIT_BUS_MASK		0xff
157 #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK	0x1ff
158 #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK	0x10f
159 
160 #define MV_DDR_CS_BITMASK_1CS		0x1
161 #define MV_DDR_CS_BITMASK_2CS		0x3
162 
163 #define MV_DDR_ONE_SPHY_PER_DUNIT	1
164 #define MV_DDR_TWO_SPHY_PER_DUNIT	2
165 
166 /* source of ddr configuration data */
167 enum mv_ddr_cfg_src {
168 	MV_DDR_CFG_DEFAULT,	/* based on data in mv_ddr_topology_map structure */
169 	MV_DDR_CFG_SPD,		/* based on data in spd */
170 	MV_DDR_CFG_USER,	/* based on data from user */
171 	MV_DDR_CFG_STATIC,	/* based on data from user in register-value format */
172 	MV_DDR_CFG_LAST
173 };
174 
175 enum mv_ddr_temperature {
176 	MV_DDR_TEMP_LOW,
177 	MV_DDR_TEMP_NORMAL,
178 	MV_DDR_TEMP_HIGH
179 };
180 
181 enum mv_ddr_timing {
182 	MV_DDR_TIM_DEFAULT,
183 	MV_DDR_TIM_1T,
184 	MV_DDR_TIM_2T
185 };
186 
187 enum mv_ddr_timing_data {
188 	MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
189 	MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
190 	MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
191 	MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
192 	MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
193 	MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
194 	MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
195 	MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
196 	MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
197 	MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
198 	MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
199 	MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
200 	MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
201 	MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
202 	MV_DDR_TDATA_LAST
203 };
204 
205 enum mv_ddr_electrical_data {
206 	MV_DDR_CK_DLY,
207 	MV_DDR_PHY_REG3,
208 	MV_DDR_ZPRI_DATA,
209 	MV_DDR_ZNRI_DATA,
210 	MV_DDR_ZPRI_CTRL,
211 	MV_DDR_ZNRI_CTRL,
212 	MV_DDR_ZPODT_DATA,
213 	MV_DDR_ZNODT_DATA,
214 	MV_DDR_ZPODT_CTRL,
215 	MV_DDR_ZNODT_CTRL,
216 	MV_DDR_DIC,
217 	MV_DDR_ODT_CFG,
218 	MV_DDR_RTT_NOM,
219 	MV_DDR_RTT_WR,
220 	MV_DDR_RTT_PARK,
221 	MV_DDR_EDATA_LAST
222 };
223 
224 /* memory electrical configuration values */
225 enum mv_ddr_rtt_nom_park_evalue {
226 	MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,
227 	MV_DDR_RTT_NOM_PARK_RZQ_DIV4,	/* 60-Ohm; RZQ = 240-Ohm */
228 	MV_DDR_RTT_NOM_PARK_RZQ_DIV2,	/* 120-Ohm; RZQ = 240-Ohm */
229 	MV_DDR_RTT_NOM_PARK_RZQ_DIV6,	/* 40-Ohm; RZQ = 240-Ohm */
230 	MV_DDR_RTT_NOM_PARK_RZQ_DIV1,	/* 240-Ohm; RZQ = 240-Ohm */
231 	MV_DDR_RTT_NOM_PARK_RZQ_DIV5,	/* 48-Ohm; RZQ = 240-Ohm */
232 	MV_DDR_RTT_NOM_PARK_RZQ_DIV3,	/* 80-Ohm; RZQ = 240-Ohm */
233 	MV_DDR_RTT_NOM_PARK_RZQ_DIV7,	/* 34-Ohm; RZQ = 240-Ohm */
234 	MV_DDR_RTT_NOM_PARK_RZQ_LAST
235 };
236 
237 enum mv_ddr_rtt_wr_evalue {
238 	MV_DDR_RTT_WR_DYN_ODT_OFF,
239 	MV_DDR_RTT_WR_RZQ_DIV2,	/* 120-Ohm; RZQ = 240-Ohm */
240 	MV_DDR_RTT_WR_RZQ_DIV1,	/* 240-Ohm; RZQ = 240-Ohm */
241 	MV_DDR_RTT_WR_HIZ,
242 	MV_DDR_RTT_WR_RZQ_DIV3,	/* 80-Ohm; RZQ = 240-Ohm */
243 	MV_DDR_RTT_WR_RZQ_LAST
244 };
245 
246 enum mv_ddr_dic_evalue {
247 	MV_DDR_DIC_RZQ_DIV7,	/* 34-Ohm; RZQ = 240-Ohm */
248 	MV_DDR_DIC_RZQ_DIV5,	/* 48-Ohm; RZQ = 240-Ohm */
249 	MV_DDR_DIC_RZQ_LAST
250 };
251 
252 /* phy electrical configuration values */
253 enum mv_ddr_ohm_evalue {
254 	MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
255 	MV_DDR_OHM_30 = 30,
256 	MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
257 	MV_DDR_OHM_48 = 48,
258 	MV_DDR_OHM_60 = 60,
259 	MV_DDR_OHM_80 = 80,
260 	MV_DDR_OHM_120 = 120,
261 	MV_DDR_OHM_240 = 240,
262 	MV_DDR_OHM_LAST
263 };
264 
265 /* mac electrical configuration values */
266 enum mv_ddr_odt_cfg_evalue {
267 	MV_DDR_ODT_CFG_NORMAL,
268 	MV_DDR_ODT_CFG_ALWAYS_ON,
269 	MV_DDR_ODT_CFG_LAST
270 };
271 
272 enum mv_ddr_dev_width { /* sdram device width */
273 	MV_DDR_DEV_WIDTH_4BIT,
274 	MV_DDR_DEV_WIDTH_8BIT,
275 	MV_DDR_DEV_WIDTH_16BIT,
276 	MV_DDR_DEV_WIDTH_32BIT,
277 	MV_DDR_DEV_WIDTH_LAST
278 };
279 
280 enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */
281 	MV_DDR_DIE_CAP_256MBIT,
282 	MV_DDR_DIE_CAP_512MBIT = 0,
283 	MV_DDR_DIE_CAP_1GBIT,
284 	MV_DDR_DIE_CAP_2GBIT,
285 	MV_DDR_DIE_CAP_4GBIT,
286 	MV_DDR_DIE_CAP_8GBIT,
287 	MV_DDR_DIE_CAP_16GBIT,
288 	MV_DDR_DIE_CAP_32GBIT,
289 	MV_DDR_DIE_CAP_12GBIT,
290 	MV_DDR_DIE_CAP_24GBIT,
291 	MV_DDR_DIE_CAP_LAST
292 };
293 
294 enum mv_ddr_pkg_rank { /* number of package ranks per dimm */
295 	MV_DDR_PKG_RANK_1,
296 	MV_DDR_PKG_RANK_2,
297 	MV_DDR_PKG_RANK_3,
298 	MV_DDR_PKG_RANK_4,
299 	MV_DDR_PKG_RANK_5,
300 	MV_DDR_PKG_RANK_6,
301 	MV_DDR_PKG_RANK_7,
302 	MV_DDR_PKG_RANK_8,
303 	MV_DDR_PKG_RANK_LAST
304 };
305 
306 enum mv_ddr_pri_bus_width { /* number of primary bus width bits */
307 	MV_DDR_PRI_BUS_WIDTH_8,
308 	MV_DDR_PRI_BUS_WIDTH_16,
309 	MV_DDR_PRI_BUS_WIDTH_32,
310 	MV_DDR_PRI_BUS_WIDTH_64,
311 	MV_DDR_PRI_BUS_WIDTH_LAST
312 };
313 
314 enum mv_ddr_bus_width_ext { /* number of extension bus width bits */
315 	MV_DDR_BUS_WIDTH_EXT_0,
316 	MV_DDR_BUS_WIDTH_EXT_8,
317 	MV_DDR_BUS_WIDTH_EXT_LAST
318 };
319 
320 enum mv_ddr_die_count {
321 	MV_DDR_DIE_CNT_1,
322 	MV_DDR_DIE_CNT_2,
323 	MV_DDR_DIE_CNT_3,
324 	MV_DDR_DIE_CNT_4,
325 	MV_DDR_DIE_CNT_5,
326 	MV_DDR_DIE_CNT_6,
327 	MV_DDR_DIE_CNT_7,
328 	MV_DDR_DIE_CNT_8,
329 	MV_DDR_DIE_CNT_LAST
330 };
331 
332 #define IS_ACTIVE(mask, id) \
333 	((mask) & (1 << (id)))
334 
335 #define VALIDATE_ACTIVE(mask, id)		\
336 	{					\
337 	if (IS_ACTIVE(mask, id) == 0)		\
338 		continue;			\
339 	}
340 
341 #define IS_IF_ACTIVE(if_mask, if_id) \
342 	((if_mask) & (1 << (if_id)))
343 
344 #define VALIDATE_IF_ACTIVE(mask, id)		\
345 	{					\
346 	if (IS_IF_ACTIVE(mask, id) == 0)	\
347 		continue;			\
348 	}
349 
350 #define IS_BUS_ACTIVE(if_mask , if_id) \
351 	(((if_mask) >> (if_id)) & 1)
352 
353 #define VALIDATE_BUS_ACTIVE(mask, id)		\
354 	{					\
355 	if (IS_BUS_ACTIVE(mask, id) == 0)	\
356 		continue;			\
357 	}
358 
359 #define DDR3_IS_ECC_PUP3_MODE(if_mask)		\
360 	(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
361 
362 #define DDR3_IS_ECC_PUP4_MODE(if_mask)		\
363 	(((if_mask) == BUS_MASK_32BIT_ECC ||	\
364 	  (if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0)
365 
366 #define DDR3_IS_16BIT_DRAM_MODE(mask)		\
367 	(((mask) == BUS_MASK_16BIT ||		\
368 	  (mask) == BUS_MASK_16BIT_ECC ||	\
369 	  (mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
370 
371 #define DDR3_IS_ECC_PUP8_MODE(if_mask)				\
372 	(((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK ||	\
373 	  (if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
374 
375 #define MV_DDR_IS_64BIT_DRAM_MODE(mask)					\
376 	((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) ||	\
377 	 (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
378 
379 #define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys)		\
380 	(((sphys) == 9) &&					\
381 	(((mask) == BUS_MASK_32BIT) ||				\
382 	 ((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
383 
384 #define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys)		\
385 	(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) ||	\
386 	 DDR3_IS_16BIT_DRAM_MODE(mask))
387 
388 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
389 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
390 unsigned int mv_ddr_cwl_calc(unsigned int tclk);
391 int mv_ddr_topology_map_update(void);
392 unsigned short mv_ddr_bus_bit_mask_get(void);
393 unsigned int mv_ddr_if_bus_width_get(void);
394 unsigned int mv_ddr_cs_num_get(void);
395 int mv_ddr_is_ecc_ena(void);
396 int mv_ddr_ck_delay_get(void);
397 unsigned long long mv_ddr_mem_sz_per_cs_get(void);
398 unsigned long long mv_ddr_mem_sz_get(void);
399 unsigned int mv_ddr_rtt_nom_get(void);
400 unsigned int mv_ddr_rtt_park_get(void);
401 unsigned int mv_ddr_rtt_wr_get(void);
402 unsigned int mv_ddr_dic_get(void);
403 
404 #endif /* _MV_DDR_TOPOLOGY_H */
405