1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <config.h>
17
18 #include <dm/device.h>
19 #include <linux/bitops.h>
20 #include <linux/compat.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24 #include <asm/cache.h>
25
26 struct mtd_info;
27 struct nand_chip;
28 struct nand_flash_dev;
29 struct device_node;
30
31 /* Get the flash and manufacturer id and lookup if the type is supported. */
32 int nand_detect(struct nand_chip *chip, int *maf_id, int *dev_id,
33 struct nand_flash_dev *type);
34
35 /* Scan and identify a NAND device */
36 int nand_scan(struct mtd_info *mtd, int max_chips);
37 /*
38 * Separate phases of nand_scan(), allowing board driver to intervene
39 * and override command or ECC setup according to flash type.
40 */
41 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
42 struct nand_flash_dev *table);
43 int nand_scan_tail(struct mtd_info *mtd);
44
45 /* Free resources held by the NAND device */
46 void nand_release(struct mtd_info *mtd);
47
48 /* Internal helper for board drivers which need to override command function */
49 void nand_wait_ready(struct mtd_info *mtd);
50
51 /*
52 * This constant declares the max. oobsize / page, which
53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly.
55 */
56 #define NAND_MAX_OOBSIZE 1664
57 #define NAND_MAX_PAGESIZE 16384
58
59 /*
60 * Constants for hardware specific CLE/ALE/NCE function
61 *
62 * These are bits which can be or'ed to set/clear multiple
63 * bits in one go.
64 */
65 /* Select the chip by setting nCE to low */
66 #define NAND_NCE 0x01
67 /* Select the command latch by setting CLE to high */
68 #define NAND_CLE 0x02
69 /* Select the address latch by setting ALE to high */
70 #define NAND_ALE 0x04
71
72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE 0x80
75
76 /*
77 * Standard NAND flash commands
78 */
79 #define NAND_CMD_READ0 0
80 #define NAND_CMD_READ1 1
81 #define NAND_CMD_RNDOUT 5
82 #define NAND_CMD_PAGEPROG 0x10
83 #define NAND_CMD_READOOB 0x50
84 #define NAND_CMD_ERASE1 0x60
85 #define NAND_CMD_STATUS 0x70
86 #define NAND_CMD_SEQIN 0x80
87 #define NAND_CMD_RNDIN 0x85
88 #define NAND_CMD_READID 0x90
89 #define NAND_CMD_ERASE2 0xd0
90 #define NAND_CMD_PARAM 0xec
91 #define NAND_CMD_GET_FEATURES 0xee
92 #define NAND_CMD_SET_FEATURES 0xef
93 #define NAND_CMD_RESET 0xff
94
95 #define NAND_CMD_LOCK 0x2a
96 #define NAND_CMD_UNLOCK1 0x23
97 #define NAND_CMD_UNLOCK2 0x24
98
99 /* Extended commands for large page devices */
100 #define NAND_CMD_READSTART 0x30
101 #define NAND_CMD_RNDOUTSTART 0xE0
102 #define NAND_CMD_CACHEDPROG 0x15
103
104 /* Extended commands for AG-AND device */
105 /*
106 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
107 * there is no way to distinguish that from NAND_CMD_READ0
108 * until the remaining sequence of commands has been completed
109 * so add a high order bit and mask it off in the command.
110 */
111 #define NAND_CMD_DEPLETE1 0x100
112 #define NAND_CMD_DEPLETE2 0x38
113 #define NAND_CMD_STATUS_MULTI 0x71
114 #define NAND_CMD_STATUS_ERROR 0x72
115 /* multi-bank error status (banks 0-3) */
116 #define NAND_CMD_STATUS_ERROR0 0x73
117 #define NAND_CMD_STATUS_ERROR1 0x74
118 #define NAND_CMD_STATUS_ERROR2 0x75
119 #define NAND_CMD_STATUS_ERROR3 0x76
120 #define NAND_CMD_STATUS_RESET 0x7f
121 #define NAND_CMD_STATUS_CLEAR 0xff
122
123 #define NAND_CMD_NONE -1
124
125 /* Status bits */
126 #define NAND_STATUS_FAIL 0x01
127 #define NAND_STATUS_FAIL_N1 0x02
128 #define NAND_STATUS_TRUE_READY 0x20
129 #define NAND_STATUS_READY 0x40
130 #define NAND_STATUS_WP 0x80
131
132 #define NAND_DATA_IFACE_CHECK_ONLY -1
133
134 /*
135 * Constants for ECC_MODES
136 */
137 typedef enum {
138 NAND_ECC_NONE,
139 NAND_ECC_SOFT,
140 NAND_ECC_HW,
141 NAND_ECC_HW_SYNDROME,
142 NAND_ECC_HW_OOB_FIRST,
143 NAND_ECC_SOFT_BCH,
144 } nand_ecc_modes_t;
145
146 enum nand_ecc_algo {
147 NAND_ECC_UNKNOWN,
148 NAND_ECC_HAMMING,
149 NAND_ECC_BCH,
150 };
151
152 /*
153 * Constants for Hardware ECC
154 */
155 /* Reset Hardware ECC for read */
156 #define NAND_ECC_READ 0
157 /* Reset Hardware ECC for write */
158 #define NAND_ECC_WRITE 1
159 /* Enable Hardware ECC before syndrome is read back from flash */
160 #define NAND_ECC_READSYN 2
161
162 /*
163 * Enable generic NAND 'page erased' check. This check is only done when
164 * ecc.correct() returns -EBADMSG.
165 * Set this flag if your implementation does not fix bitflips in erased
166 * pages and you want to rely on the default implementation.
167 */
168 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
169 #define NAND_ECC_MAXIMIZE BIT(1)
170 /*
171 * If your controller already sends the required NAND commands when
172 * reading or writing a page, then the framework is not supposed to
173 * send READ0 and SEQIN/PAGEPROG respectively.
174 */
175 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
176
177 /* Bit mask for flags passed to do_nand_read_ecc */
178 #define NAND_GET_DEVICE 0x80
179
180
181 /*
182 * Option constants for bizarre disfunctionality and real
183 * features.
184 */
185 /* Buswidth is 16 bit */
186 #define NAND_BUSWIDTH_16 0x00000002
187 /* Device supports partial programming without padding */
188 #define NAND_NO_PADDING 0x00000004
189 /* Chip has cache program function */
190 #define NAND_CACHEPRG 0x00000008
191 /* Chip has copy back function */
192 #define NAND_COPYBACK 0x00000010
193 /*
194 * Chip requires ready check on read (for auto-incremented sequential read).
195 * True only for small page devices; large page devices do not support
196 * autoincrement.
197 */
198 #define NAND_NEED_READRDY 0x00000100
199
200 /* Chip does not allow subpage writes */
201 #define NAND_NO_SUBPAGE_WRITE 0x00000200
202
203 /* Device is one of 'new' xD cards that expose fake nand command set */
204 #define NAND_BROKEN_XD 0x00000400
205
206 /* Device behaves just like nand, but is readonly */
207 #define NAND_ROM 0x00000800
208
209 /* Device supports subpage reads */
210 #define NAND_SUBPAGE_READ 0x00001000
211
212 /*
213 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
214 * patterns.
215 */
216 #define NAND_NEED_SCRAMBLING 0x00002000
217
218 /* Device needs 3rd row address cycle */
219 #define NAND_ROW_ADDR_3 0x00004000
220
221 /* Options valid for Samsung large page devices */
222 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
223
224 /* Macros to identify the above */
225 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
226 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
227 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
228
229 /* Non chip related options */
230 /* This option skips the bbt scan during initialization. */
231 #define NAND_SKIP_BBTSCAN 0x00010000
232 /*
233 * This option is defined if the board driver allocates its own buffers
234 * (e.g. because it needs them DMA-coherent).
235 */
236 #define NAND_OWN_BUFFERS 0x00020000
237 /* Chip may not exist, so silence any errors in scan */
238 #define NAND_SCAN_SILENT_NODEV 0x00040000
239 /*
240 * Autodetect nand buswidth with readid/onfi.
241 * This suppose the driver will configure the hardware in 8 bits mode
242 * when calling nand_scan_ident, and update its configuration
243 * before calling nand_scan_tail.
244 */
245 #define NAND_BUSWIDTH_AUTO 0x00080000
246 /*
247 * This option could be defined by controller drivers to protect against
248 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
249 */
250 #define NAND_USE_BOUNCE_BUFFER 0x00100000
251
252 /* Options set by nand scan */
253 /* bbt has already been read */
254 #define NAND_BBT_SCANNED 0x40000000
255 /* Nand scan has allocated controller struct */
256 #define NAND_CONTROLLER_ALLOC 0x80000000
257
258 /* Cell info constants */
259 #define NAND_CI_CHIPNR_MSK 0x03
260 #define NAND_CI_CELLTYPE_MSK 0x0C
261 #define NAND_CI_CELLTYPE_SHIFT 2
262
263 /* ONFI features */
264 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
265 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
266
267 /* ONFI timing mode, used in both asynchronous and synchronous mode */
268 #define ONFI_TIMING_MODE_0 (1 << 0)
269 #define ONFI_TIMING_MODE_1 (1 << 1)
270 #define ONFI_TIMING_MODE_2 (1 << 2)
271 #define ONFI_TIMING_MODE_3 (1 << 3)
272 #define ONFI_TIMING_MODE_4 (1 << 4)
273 #define ONFI_TIMING_MODE_5 (1 << 5)
274 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
275
276 /* ONFI feature address */
277 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
278
279 /* Vendor-specific feature address (Micron) */
280 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
281
282 /* ONFI subfeature parameters length */
283 #define ONFI_SUBFEATURE_PARAM_LEN 4
284
285 /* ONFI optional commands SET/GET FEATURES supported? */
286 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
287
288 struct nand_onfi_params {
289 /* rev info and features block */
290 /* 'O' 'N' 'F' 'I' */
291 u8 sig[4];
292 __le16 revision;
293 __le16 features;
294 __le16 opt_cmd;
295 u8 reserved0[2];
296 __le16 ext_param_page_length; /* since ONFI 2.1 */
297 u8 num_of_param_pages; /* since ONFI 2.1 */
298 u8 reserved1[17];
299
300 /* manufacturer information block */
301 char manufacturer[12];
302 char model[20];
303 u8 jedec_id;
304 __le16 date_code;
305 u8 reserved2[13];
306
307 /* memory organization block */
308 __le32 byte_per_page;
309 __le16 spare_bytes_per_page;
310 __le32 data_bytes_per_ppage;
311 __le16 spare_bytes_per_ppage;
312 __le32 pages_per_block;
313 __le32 blocks_per_lun;
314 u8 lun_count;
315 u8 addr_cycles;
316 u8 bits_per_cell;
317 __le16 bb_per_lun;
318 __le16 block_endurance;
319 u8 guaranteed_good_blocks;
320 __le16 guaranteed_block_endurance;
321 u8 programs_per_page;
322 u8 ppage_attr;
323 u8 ecc_bits;
324 u8 interleaved_bits;
325 u8 interleaved_ops;
326 u8 reserved3[13];
327
328 /* electrical parameter block */
329 u8 io_pin_capacitance_max;
330 __le16 async_timing_mode;
331 __le16 program_cache_timing_mode;
332 __le16 t_prog;
333 __le16 t_bers;
334 __le16 t_r;
335 __le16 t_ccs;
336 __le16 src_sync_timing_mode;
337 u8 src_ssync_features;
338 __le16 clk_pin_capacitance_typ;
339 __le16 io_pin_capacitance_typ;
340 __le16 input_pin_capacitance_typ;
341 u8 input_pin_capacitance_max;
342 u8 driver_strength_support;
343 __le16 t_int_r;
344 __le16 t_adl;
345 u8 reserved4[8];
346
347 /* vendor */
348 __le16 vendor_revision;
349 u8 vendor[88];
350
351 __le16 crc;
352 } __packed;
353
354 #define ONFI_CRC_BASE 0x4F4E
355
356 /* Extended ECC information Block Definition (since ONFI 2.1) */
357 struct onfi_ext_ecc_info {
358 u8 ecc_bits;
359 u8 codeword_size;
360 __le16 bb_per_lun;
361 __le16 block_endurance;
362 u8 reserved[2];
363 } __packed;
364
365 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
366 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
367 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
368 struct onfi_ext_section {
369 u8 type;
370 u8 length;
371 } __packed;
372
373 #define ONFI_EXT_SECTION_MAX 8
374
375 /* Extended Parameter Page Definition (since ONFI 2.1) */
376 struct onfi_ext_param_page {
377 __le16 crc;
378 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
379 u8 reserved0[10];
380 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
381
382 /*
383 * The actual size of the Extended Parameter Page is in
384 * @ext_param_page_length of nand_onfi_params{}.
385 * The following are the variable length sections.
386 * So we do not add any fields below. Please see the ONFI spec.
387 */
388 } __packed;
389
390 struct jedec_ecc_info {
391 u8 ecc_bits;
392 u8 codeword_size;
393 __le16 bb_per_lun;
394 __le16 block_endurance;
395 u8 reserved[2];
396 } __packed;
397
398 /* JEDEC features */
399 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
400
401 struct nand_jedec_params {
402 /* rev info and features block */
403 /* 'J' 'E' 'S' 'D' */
404 u8 sig[4];
405 __le16 revision;
406 __le16 features;
407 u8 opt_cmd[3];
408 __le16 sec_cmd;
409 u8 num_of_param_pages;
410 u8 reserved0[18];
411
412 /* manufacturer information block */
413 char manufacturer[12];
414 char model[20];
415 u8 jedec_id[6];
416 u8 reserved1[10];
417
418 /* memory organization block */
419 __le32 byte_per_page;
420 __le16 spare_bytes_per_page;
421 u8 reserved2[6];
422 __le32 pages_per_block;
423 __le32 blocks_per_lun;
424 u8 lun_count;
425 u8 addr_cycles;
426 u8 bits_per_cell;
427 u8 programs_per_page;
428 u8 multi_plane_addr;
429 u8 multi_plane_op_attr;
430 u8 reserved3[38];
431
432 /* electrical parameter block */
433 __le16 async_sdr_speed_grade;
434 __le16 toggle_ddr_speed_grade;
435 __le16 sync_ddr_speed_grade;
436 u8 async_sdr_features;
437 u8 toggle_ddr_features;
438 u8 sync_ddr_features;
439 __le16 t_prog;
440 __le16 t_bers;
441 __le16 t_r;
442 __le16 t_r_multi_plane;
443 __le16 t_ccs;
444 __le16 io_pin_capacitance_typ;
445 __le16 input_pin_capacitance_typ;
446 __le16 clk_pin_capacitance_typ;
447 u8 driver_strength_support;
448 __le16 t_adl;
449 u8 reserved4[36];
450
451 /* ECC and endurance block */
452 u8 guaranteed_good_blocks;
453 __le16 guaranteed_block_endurance;
454 struct jedec_ecc_info ecc_info[4];
455 u8 reserved5[29];
456
457 /* reserved */
458 u8 reserved6[148];
459
460 /* vendor */
461 __le16 vendor_rev_num;
462 u8 reserved7[88];
463
464 /* CRC for Parameter Page */
465 __le16 crc;
466 } __packed;
467
468 /**
469 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
470 * @lock: protection lock
471 * @active: the mtd device which holds the controller currently
472 * @wq: wait queue to sleep on if a NAND operation is in
473 * progress used instead of the per chip wait queue
474 * when a hw controller is available.
475 */
476 struct nand_hw_control {
477 spinlock_t lock;
478 struct nand_chip *active;
479 };
480
nand_hw_control_init(struct nand_hw_control * nfc)481 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
482 {
483 nfc->active = NULL;
484 spin_lock_init(&nfc->lock);
485 init_waitqueue_head(&nfc->wq);
486 }
487
488 /* The maximum expected count of bytes in the NAND ID sequence */
489 #define NAND_MAX_ID_LEN 8
490
491 /**
492 * struct nand_id - NAND id structure
493 * @data: buffer containing the id bytes.
494 * @len: ID length.
495 */
496 struct nand_id {
497 u8 data[NAND_MAX_ID_LEN];
498 int len;
499 };
500
501 /**
502 * struct nand_ecc_step_info - ECC step information of ECC engine
503 * @stepsize: data bytes per ECC step
504 * @strengths: array of supported strengths
505 * @nstrengths: number of supported strengths
506 */
507 struct nand_ecc_step_info {
508 int stepsize;
509 const int *strengths;
510 int nstrengths;
511 };
512
513 /**
514 * struct nand_ecc_caps - capability of ECC engine
515 * @stepinfos: array of ECC step information
516 * @nstepinfos: number of ECC step information
517 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
518 */
519 struct nand_ecc_caps {
520 const struct nand_ecc_step_info *stepinfos;
521 int nstepinfos;
522 int (*calc_ecc_bytes)(int step_size, int strength);
523 };
524
525 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
526 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
527 static const int __name##_strengths[] = { __VA_ARGS__ }; \
528 static const struct nand_ecc_step_info __name##_stepinfo = { \
529 .stepsize = __step, \
530 .strengths = __name##_strengths, \
531 .nstrengths = ARRAY_SIZE(__name##_strengths), \
532 }; \
533 static const struct nand_ecc_caps __name = { \
534 .stepinfos = &__name##_stepinfo, \
535 .nstepinfos = 1, \
536 .calc_ecc_bytes = __calc, \
537 }
538
539 /**
540 * struct nand_ecc_ctrl - Control structure for ECC
541 * @mode: ECC mode
542 * @algo: ECC algorithm
543 * @steps: number of ECC steps per page
544 * @size: data bytes per ECC step
545 * @bytes: ECC bytes per step
546 * @strength: max number of correctible bits per ECC step
547 * @total: total number of ECC bytes per page
548 * @prepad: padding information for syndrome based ECC generators
549 * @postpad: padding information for syndrome based ECC generators
550 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
551 * @layout: ECC layout control struct pointer
552 * @priv: pointer to private ECC control data
553 * @hwctl: function to control hardware ECC generator. Must only
554 * be provided if an hardware ECC is available
555 * @calculate: function for ECC calculation or readback from ECC hardware
556 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
557 * Should return a positive number representing the number of
558 * corrected bitflips, -EBADMSG if the number of bitflips exceed
559 * ECC strength, or any other error code if the error is not
560 * directly related to correction.
561 * If -EBADMSG is returned the input buffers should be left
562 * untouched.
563 * @read_page_raw: function to read a raw page without ECC. This function
564 * should hide the specific layout used by the ECC
565 * controller and always return contiguous in-band and
566 * out-of-band data even if they're not stored
567 * contiguously on the NAND chip (e.g.
568 * NAND_ECC_HW_SYNDROME interleaves in-band and
569 * out-of-band data).
570 * @write_page_raw: function to write a raw page without ECC. This function
571 * should hide the specific layout used by the ECC
572 * controller and consider the passed data as contiguous
573 * in-band and out-of-band data. ECC controller is
574 * responsible for doing the appropriate transformations
575 * to adapt to its specific layout (e.g.
576 * NAND_ECC_HW_SYNDROME interleaves in-band and
577 * out-of-band data).
578 * @read_page: function to read a page according to the ECC generator
579 * requirements; returns maximum number of bitflips corrected in
580 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
581 * @read_subpage: function to read parts of the page covered by ECC;
582 * returns same as read_page()
583 * @write_subpage: function to write parts of the page covered by ECC.
584 * @write_page: function to write a page according to the ECC generator
585 * requirements.
586 * @write_oob_raw: function to write chip OOB data without ECC
587 * @read_oob_raw: function to read chip OOB data without ECC
588 * @read_oob: function to read chip OOB data
589 * @write_oob: function to write chip OOB data
590 */
591 struct nand_ecc_ctrl {
592 nand_ecc_modes_t mode;
593 enum nand_ecc_algo algo;
594 int steps;
595 int size;
596 int bytes;
597 int total;
598 int strength;
599 int prepad;
600 int postpad;
601 unsigned int options;
602 struct nand_ecclayout *layout;
603 void *priv;
604 void (*hwctl)(struct mtd_info *mtd, int mode);
605 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
606 uint8_t *ecc_code);
607 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
608 uint8_t *calc_ecc);
609 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
610 uint8_t *buf, int oob_required, int page);
611 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
612 const uint8_t *buf, int oob_required, int page);
613 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
614 uint8_t *buf, int oob_required, int page);
615 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
616 uint32_t offs, uint32_t len, uint8_t *buf, int page);
617 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
618 uint32_t offset, uint32_t data_len,
619 const uint8_t *data_buf, int oob_required, int page);
620 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
621 const uint8_t *buf, int oob_required, int page);
622 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
623 int page);
624 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
625 int page);
626 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
627 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
628 int page);
629 };
630
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)631 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
632 {
633 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
634 }
635
636 /**
637 * struct nand_buffers - buffer structure for read/write
638 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
639 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
640 * @databuf: buffer pointer for data, size is (page size + oobsize).
641 *
642 * Do not change the order of buffers. databuf and oobrbuf must be in
643 * consecutive order.
644 */
645 struct nand_buffers {
646 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
647 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
648 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
649 ARCH_DMA_MINALIGN)];
650 };
651
652 /**
653 * struct nand_sdr_timings - SDR NAND chip timings
654 *
655 * This struct defines the timing requirements of a SDR NAND chip.
656 * These information can be found in every NAND datasheets and the timings
657 * meaning are described in the ONFI specifications:
658 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
659 * Parameters)
660 *
661 * All these timings are expressed in picoseconds.
662 *
663 * @tBERS_max: Block erase time
664 * @tCCS_min: Change column setup time
665 * @tPROG_max: Page program time
666 * @tR_max: Page read time
667 * @tALH_min: ALE hold time
668 * @tADL_min: ALE to data loading time
669 * @tALS_min: ALE setup time
670 * @tAR_min: ALE to RE# delay
671 * @tCEA_max: CE# access time
672 * @tCEH_min: CE# high hold time
673 * @tCH_min: CE# hold time
674 * @tCHZ_max: CE# high to output hi-Z
675 * @tCLH_min: CLE hold time
676 * @tCLR_min: CLE to RE# delay
677 * @tCLS_min: CLE setup time
678 * @tCOH_min: CE# high to output hold
679 * @tCS_min: CE# setup time
680 * @tDH_min: Data hold time
681 * @tDS_min: Data setup time
682 * @tFEAT_max: Busy time for Set Features and Get Features
683 * @tIR_min: Output hi-Z to RE# low
684 * @tITC_max: Interface and Timing Mode Change time
685 * @tRC_min: RE# cycle time
686 * @tREA_max: RE# access time
687 * @tREH_min: RE# high hold time
688 * @tRHOH_min: RE# high to output hold
689 * @tRHW_min: RE# high to WE# low
690 * @tRHZ_max: RE# high to output hi-Z
691 * @tRLOH_min: RE# low to output hold
692 * @tRP_min: RE# pulse width
693 * @tRR_min: Ready to RE# low (data only)
694 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
695 * rising edge of R/B#.
696 * @tWB_max: WE# high to SR[6] low
697 * @tWC_min: WE# cycle time
698 * @tWH_min: WE# high hold time
699 * @tWHR_min: WE# high to RE# low
700 * @tWP_min: WE# pulse width
701 * @tWW_min: WP# transition to WE# low
702 */
703 struct nand_sdr_timings {
704 u64 tBERS_max;
705 u32 tCCS_min;
706 u64 tPROG_max;
707 u64 tR_max;
708 u32 tALH_min;
709 u32 tADL_min;
710 u32 tALS_min;
711 u32 tAR_min;
712 u32 tCEA_max;
713 u32 tCEH_min;
714 u32 tCH_min;
715 u32 tCHZ_max;
716 u32 tCLH_min;
717 u32 tCLR_min;
718 u32 tCLS_min;
719 u32 tCOH_min;
720 u32 tCS_min;
721 u32 tDH_min;
722 u32 tDS_min;
723 u32 tFEAT_max;
724 u32 tIR_min;
725 u32 tITC_max;
726 u32 tRC_min;
727 u32 tREA_max;
728 u32 tREH_min;
729 u32 tRHOH_min;
730 u32 tRHW_min;
731 u32 tRHZ_max;
732 u32 tRLOH_min;
733 u32 tRP_min;
734 u32 tRR_min;
735 u64 tRST_max;
736 u32 tWB_max;
737 u32 tWC_min;
738 u32 tWH_min;
739 u32 tWHR_min;
740 u32 tWP_min;
741 u32 tWW_min;
742 };
743
744 /**
745 * enum nand_data_interface_type - NAND interface timing type
746 * @NAND_SDR_IFACE: Single Data Rate interface
747 */
748 enum nand_data_interface_type {
749 NAND_SDR_IFACE,
750 };
751
752 /**
753 * struct nand_data_interface - NAND interface timing
754 * @type: type of the timing
755 * @timings: The timing, type according to @type
756 */
757 struct nand_data_interface {
758 enum nand_data_interface_type type;
759 union {
760 struct nand_sdr_timings sdr;
761 } timings;
762 };
763
764 /**
765 * nand_get_sdr_timings - get SDR timing from data interface
766 * @conf: The data interface
767 */
768 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)769 nand_get_sdr_timings(const struct nand_data_interface *conf)
770 {
771 if (conf->type != NAND_SDR_IFACE)
772 return ERR_PTR(-EINVAL);
773
774 return &conf->timings.sdr;
775 }
776
777 /**
778 * struct nand_manufacturer_ops - NAND Manufacturer operations
779 * @detect: detect the NAND memory organization and capabilities
780 * @init: initialize all vendor specific fields (like the ->read_retry()
781 * implementation) if any.
782 */
783 struct nand_manufacturer_ops {
784 void (*detect)(struct nand_chip *chip);
785 int (*init)(struct nand_chip *chip);
786 };
787
788 /**
789 * struct nand_chip - NAND Private Flash Chip Data
790 * @mtd: MTD device registered to the MTD framework
791 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
792 * flash device
793 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
794 * flash device.
795 * @flash_node: [BOARDSPECIFIC] device node describing this instance
796 * @read_byte: [REPLACEABLE] read one byte from the chip
797 * @read_word: [REPLACEABLE] read one word from the chip
798 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
799 * low 8 I/O lines
800 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
801 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
802 * @select_chip: [REPLACEABLE] select chip nr
803 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
804 * @block_markbad: [REPLACEABLE] mark a block bad
805 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
806 * ALE/CLE/nCE. Also used to write command and address
807 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
808 * device ready/busy line. If set to NULL no access to
809 * ready/busy is available and the ready/busy information
810 * is read from the chip status register.
811 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
812 * commands to the chip.
813 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
814 * ready.
815 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
816 * setting the read-retry mode. Mostly needed for MLC NAND.
817 * @ecc: [BOARDSPECIFIC] ECC control structure
818 * @buffers: buffer structure for read/write
819 * @buf_align: minimum buffer alignment required by a platform
820 * @hwcontrol: platform-specific hardware control structure
821 * @erase: [REPLACEABLE] erase function
822 * @scan_bbt: [REPLACEABLE] function to scan bad block table
823 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
824 * data from array to read regs (tR).
825 * @state: [INTERN] the current state of the NAND device
826 * @oob_poi: "poison value buffer," used for laying out OOB data
827 * before writing
828 * @page_shift: [INTERN] number of address bits in a page (column
829 * address bits).
830 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
831 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
832 * @chip_shift: [INTERN] number of address bits in one chip
833 * @options: [BOARDSPECIFIC] various chip options. They can partly
834 * be set to inform nand_scan about special functionality.
835 * See the defines for further explanation.
836 * @bbt_options: [INTERN] bad block specific options. All options used
837 * here must come from bbm.h. By default, these options
838 * will be copied to the appropriate nand_bbt_descr's.
839 * @badblockpos: [INTERN] position of the bad block marker in the oob
840 * area.
841 * @badblockbits: [INTERN] minimum number of set bits in a good block's
842 * bad block marker position; i.e., BBM == 11110111b is
843 * not bad when badblockbits == 7
844 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
845 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
846 * Minimum amount of bit errors per @ecc_step_ds guaranteed
847 * to be correctable. If unknown, set to zero.
848 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
849 * also from the datasheet. It is the recommended ECC step
850 * size, if known; if unknown, set to zero.
851 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
852 * set to the actually used ONFI mode if the chip is
853 * ONFI compliant or deduced from the datasheet if
854 * the NAND chip is not ONFI compliant.
855 * @numchips: [INTERN] number of physical chips
856 * @chipsize: [INTERN] the size of one chip for multichip arrays
857 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
858 * @pagebuf: [INTERN] holds the pagenumber which is currently in
859 * data_buf.
860 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
861 * currently in data_buf.
862 * @subpagesize: [INTERN] holds the subpagesize
863 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
864 * non 0 if ONFI supported.
865 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
866 * non 0 if JEDEC supported.
867 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
868 * supported, 0 otherwise.
869 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
870 * supported, 0 otherwise.
871 * @read_retries: [INTERN] the number of read retry modes supported
872 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
873 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
874 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
875 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
876 * means the configuration should not be applied but
877 * only checked.
878 * @bbt: [INTERN] bad block table pointer
879 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
880 * lookup.
881 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
882 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
883 * bad block scan.
884 * @controller: [REPLACEABLE] a pointer to a hardware controller
885 * structure which is shared among multiple independent
886 * devices.
887 * @priv: [OPTIONAL] pointer to private chip data
888 * @write_page: [REPLACEABLE] High-level page write function
889 * @manufacturer: [INTERN] Contains manufacturer information
890 */
891
892 struct nand_chip {
893 struct mtd_info mtd;
894 struct nand_id id;
895
896 void __iomem *IO_ADDR_R;
897 void __iomem *IO_ADDR_W;
898
899 ofnode flash_node;
900
901 uint8_t (*read_byte)(struct mtd_info *mtd);
902 u16 (*read_word)(struct mtd_info *mtd);
903 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
904 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
905 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
906 void (*select_chip)(struct mtd_info *mtd, int chip);
907 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
908 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
909 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
910 int (*dev_ready)(struct mtd_info *mtd);
911 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
912 int page_addr);
913 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
914 int (*erase)(struct mtd_info *mtd, int page);
915 int (*scan_bbt)(struct mtd_info *mtd);
916 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
917 uint32_t offset, int data_len, const uint8_t *buf,
918 int oob_required, int page, int raw);
919 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
920 int feature_addr, uint8_t *subfeature_para);
921 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
922 int feature_addr, uint8_t *subfeature_para);
923 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
924 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
925 const struct nand_data_interface *conf);
926
927
928 int chip_delay;
929 unsigned int options;
930 unsigned int bbt_options;
931
932 int page_shift;
933 int phys_erase_shift;
934 int bbt_erase_shift;
935 int chip_shift;
936 int numchips;
937 uint64_t chipsize;
938 int pagemask;
939 int pagebuf;
940 unsigned int pagebuf_bitflips;
941 int subpagesize;
942 uint8_t bits_per_cell;
943 uint16_t ecc_strength_ds;
944 uint16_t ecc_step_ds;
945 int onfi_timing_mode_default;
946 int badblockpos;
947 int badblockbits;
948
949 int onfi_version;
950 int jedec_version;
951 struct nand_onfi_params onfi_params;
952 struct nand_jedec_params jedec_params;
953
954 struct nand_data_interface *data_interface;
955
956 int read_retries;
957
958 flstate_t state;
959
960 uint8_t *oob_poi;
961 struct nand_hw_control *controller;
962 struct nand_ecclayout *ecclayout;
963
964 struct nand_ecc_ctrl ecc;
965 struct nand_buffers *buffers;
966 unsigned long buf_align;
967 struct nand_hw_control hwcontrol;
968
969 uint8_t *bbt;
970 struct nand_bbt_descr *bbt_td;
971 struct nand_bbt_descr *bbt_md;
972
973 struct nand_bbt_descr *badblock_pattern;
974
975 void *priv;
976
977 struct {
978 const struct nand_manufacturer *desc;
979 void *priv;
980 } manufacturer;
981 };
982
nand_set_flash_node(struct nand_chip * chip,ofnode node)983 static inline void nand_set_flash_node(struct nand_chip *chip,
984 ofnode node)
985 {
986 chip->flash_node = node;
987 }
988
nand_get_flash_node(struct nand_chip * chip)989 static inline ofnode nand_get_flash_node(struct nand_chip *chip)
990 {
991 return chip->flash_node;
992 }
993
mtd_to_nand(struct mtd_info * mtd)994 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
995 {
996 return container_of(mtd, struct nand_chip, mtd);
997 }
998
nand_to_mtd(struct nand_chip * chip)999 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1000 {
1001 return &chip->mtd;
1002 }
1003
nand_get_controller_data(struct nand_chip * chip)1004 static inline void *nand_get_controller_data(struct nand_chip *chip)
1005 {
1006 return chip->priv;
1007 }
1008
nand_set_controller_data(struct nand_chip * chip,void * priv)1009 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1010 {
1011 chip->priv = priv;
1012 }
1013
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1014 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1015 void *priv)
1016 {
1017 chip->manufacturer.priv = priv;
1018 }
1019
nand_get_manufacturer_data(struct nand_chip * chip)1020 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1021 {
1022 return chip->manufacturer.priv;
1023 }
1024
1025 /*
1026 * NAND Flash Manufacturer ID Codes
1027 */
1028 #define NAND_MFR_TOSHIBA 0x98
1029 #define NAND_MFR_SAMSUNG 0xec
1030 #define NAND_MFR_FUJITSU 0x04
1031 #define NAND_MFR_NATIONAL 0x8f
1032 #define NAND_MFR_RENESAS 0x07
1033 #define NAND_MFR_STMICRO 0x20
1034 #define NAND_MFR_HYNIX 0xad
1035 #define NAND_MFR_MICRON 0x2c
1036 #define NAND_MFR_AMD 0x01
1037 #define NAND_MFR_MACRONIX 0xc2
1038 #define NAND_MFR_EON 0x92
1039 #define NAND_MFR_SANDISK 0x45
1040 #define NAND_MFR_INTEL 0x89
1041 #define NAND_MFR_ATO 0x9b
1042
1043 /* The maximum expected count of bytes in the NAND ID sequence */
1044 #define NAND_MAX_ID_LEN 8
1045
1046 /*
1047 * A helper for defining older NAND chips where the second ID byte fully
1048 * defined the chip, including the geometry (chip size, eraseblock size, page
1049 * size). All these chips have 512 bytes NAND page size.
1050 */
1051 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1052 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1053 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1054
1055 /*
1056 * A helper for defining newer chips which report their page size and
1057 * eraseblock size via the extended ID bytes.
1058 *
1059 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1060 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1061 * device ID now only represented a particular total chip size (and voltage,
1062 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1063 * using the same device ID.
1064 */
1065 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1066 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1067 .options = (opts) }
1068
1069 #define NAND_ECC_INFO(_strength, _step) \
1070 { .strength_ds = (_strength), .step_ds = (_step) }
1071 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1072 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1073
1074 /**
1075 * struct nand_flash_dev - NAND Flash Device ID Structure
1076 * @name: a human-readable name of the NAND chip
1077 * @dev_id: the device ID (the second byte of the full chip ID array)
1078 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1079 * memory address as @id[0])
1080 * @dev_id: device ID part of the full chip ID array (refers the same memory
1081 * address as @id[1])
1082 * @id: full device ID array
1083 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1084 * well as the eraseblock size) is determined from the extended NAND
1085 * chip ID array)
1086 * @chipsize: total chip size in MiB
1087 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1088 * @options: stores various chip bit options
1089 * @id_len: The valid length of the @id.
1090 * @oobsize: OOB size
1091 * @ecc: ECC correctability and step information from the datasheet.
1092 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1093 * @ecc_strength_ds in nand_chip{}.
1094 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1095 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1096 * For example, the "4bit ECC for each 512Byte" can be set with
1097 * NAND_ECC_INFO(4, 512).
1098 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1099 * reset. Should be deduced from timings described
1100 * in the datasheet.
1101 *
1102 */
1103 struct nand_flash_dev {
1104 char *name;
1105 union {
1106 struct {
1107 uint8_t mfr_id;
1108 uint8_t dev_id;
1109 };
1110 uint8_t id[NAND_MAX_ID_LEN];
1111 };
1112 unsigned int pagesize;
1113 unsigned int chipsize;
1114 unsigned int erasesize;
1115 unsigned int options;
1116 uint16_t id_len;
1117 uint16_t oobsize;
1118 struct {
1119 uint16_t strength_ds;
1120 uint16_t step_ds;
1121 } ecc;
1122 int onfi_timing_mode_default;
1123 };
1124
1125 /**
1126 * struct nand_manufacturer - NAND Flash Manufacturer ID Structure
1127 * @name: Manufacturer name
1128 * @id: manufacturer ID code of device.
1129 * @ops: manufacturer operations
1130 */
1131 struct nand_manufacturer {
1132 int id;
1133 char *name;
1134 const struct nand_manufacturer_ops *ops;
1135 };
1136
1137 extern struct nand_flash_dev nand_flash_ids[];
1138 extern struct nand_manufacturer nand_manuf_ids[];
1139
1140 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1141 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1142 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1143 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1144 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1145 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1146
1147 int nand_default_bbt(struct mtd_info *mtd);
1148 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1149 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1150 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1151 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1152 int allowbbt);
1153 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1154 size_t *retlen, uint8_t *buf);
1155
1156 /*
1157 * Constants for oob configuration
1158 */
1159 #define NAND_SMALL_BADBLOCK_POS 5
1160 #define NAND_LARGE_BADBLOCK_POS 0
1161
1162 /**
1163 * struct platform_nand_chip - chip level device structure
1164 * @nr_chips: max. number of chips to scan for
1165 * @chip_offset: chip number offset
1166 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1167 * @partitions: mtd partition list
1168 * @chip_delay: R/B delay value in us
1169 * @options: Option flags, e.g. 16bit buswidth
1170 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1171 * @part_probe_types: NULL-terminated array of probe types
1172 */
1173 struct platform_nand_chip {
1174 int nr_chips;
1175 int chip_offset;
1176 int nr_partitions;
1177 struct mtd_partition *partitions;
1178 int chip_delay;
1179 unsigned int options;
1180 unsigned int bbt_options;
1181 const char **part_probe_types;
1182 };
1183
1184 /* Keep gcc happy */
1185 struct platform_device;
1186
1187 /**
1188 * struct platform_nand_ctrl - controller level device structure
1189 * @probe: platform specific function to probe/setup hardware
1190 * @remove: platform specific function to remove/teardown hardware
1191 * @hwcontrol: platform specific hardware control structure
1192 * @dev_ready: platform specific function to read ready/busy pin
1193 * @select_chip: platform specific chip select function
1194 * @cmd_ctrl: platform specific function for controlling
1195 * ALE/CLE/nCE. Also used to write command and address
1196 * @write_buf: platform specific function for write buffer
1197 * @read_buf: platform specific function for read buffer
1198 * @read_byte: platform specific function to read one byte from chip
1199 * @priv: private data to transport driver specific settings
1200 *
1201 * All fields are optional and depend on the hardware driver requirements
1202 */
1203 struct platform_nand_ctrl {
1204 int (*probe)(struct platform_device *pdev);
1205 void (*remove)(struct platform_device *pdev);
1206 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1207 int (*dev_ready)(struct mtd_info *mtd);
1208 void (*select_chip)(struct mtd_info *mtd, int chip);
1209 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1210 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1211 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1212 unsigned char (*read_byte)(struct mtd_info *mtd);
1213 void *priv;
1214 };
1215
1216 /**
1217 * struct platform_nand_data - container structure for platform-specific data
1218 * @chip: chip level chip structure
1219 * @ctrl: controller level device structure
1220 */
1221 struct platform_nand_data {
1222 struct platform_nand_chip chip;
1223 struct platform_nand_ctrl ctrl;
1224 };
1225
1226 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1227 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1228 static inline int onfi_feature(struct nand_chip *chip)
1229 {
1230 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1231 }
1232
1233 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1234 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1235 {
1236 if (!chip->onfi_version)
1237 return ONFI_TIMING_MODE_UNKNOWN;
1238 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1239 }
1240
1241 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1242 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1243 {
1244 if (!chip->onfi_version)
1245 return ONFI_TIMING_MODE_UNKNOWN;
1246 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1247 }
1248 #else
onfi_feature(struct nand_chip * chip)1249 static inline int onfi_feature(struct nand_chip *chip)
1250 {
1251 return 0;
1252 }
1253
onfi_get_async_timing_mode(struct nand_chip * chip)1254 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1255 {
1256 return ONFI_TIMING_MODE_UNKNOWN;
1257 }
1258
onfi_get_sync_timing_mode(struct nand_chip * chip)1259 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1260 {
1261 return ONFI_TIMING_MODE_UNKNOWN;
1262 }
1263 #endif
1264
1265 int onfi_init_data_interface(struct nand_chip *chip,
1266 struct nand_data_interface *iface,
1267 enum nand_data_interface_type type,
1268 int timing_mode);
1269
1270 /*
1271 * Check if it is a SLC nand.
1272 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1273 * We do not distinguish the MLC and TLC now.
1274 */
nand_is_slc(struct nand_chip * chip)1275 static inline bool nand_is_slc(struct nand_chip *chip)
1276 {
1277 return chip->bits_per_cell == 1;
1278 }
1279
1280 /**
1281 * Check if the opcode's address should be sent only on the lower 8 bits
1282 * @command: opcode to check
1283 */
nand_opcode_8bits(unsigned int command)1284 static inline int nand_opcode_8bits(unsigned int command)
1285 {
1286 switch (command) {
1287 case NAND_CMD_READID:
1288 case NAND_CMD_PARAM:
1289 case NAND_CMD_GET_FEATURES:
1290 case NAND_CMD_SET_FEATURES:
1291 return 1;
1292 default:
1293 break;
1294 }
1295 return 0;
1296 }
1297
1298 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1299 static inline int jedec_feature(struct nand_chip *chip)
1300 {
1301 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1302 : 0;
1303 }
1304
1305 /* Standard NAND functions from nand_base.c */
1306 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1307 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1308 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1309 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1310 uint8_t nand_read_byte(struct mtd_info *mtd);
1311
1312 /* get timing characteristics from ONFI timing mode. */
1313 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1314 /* get data interface from ONFI timing mode 0, used after reset. */
1315 const struct nand_data_interface *nand_get_default_data_interface(void);
1316
1317 int nand_check_erased_ecc_chunk(void *data, int datalen,
1318 void *ecc, int ecclen,
1319 void *extraoob, int extraooblen,
1320 int threshold);
1321
1322 int nand_check_ecc_caps(struct nand_chip *chip,
1323 const struct nand_ecc_caps *caps, int oobavail);
1324
1325 int nand_match_ecc_req(struct nand_chip *chip,
1326 const struct nand_ecc_caps *caps, int oobavail);
1327
1328 int nand_maximize_ecc(struct nand_chip *chip,
1329 const struct nand_ecc_caps *caps, int oobavail);
1330
1331 /* Reset and initialize a NAND device */
1332 int nand_reset(struct nand_chip *chip, int chipnr);
1333
1334 /* NAND operation helpers */
1335 int nand_reset_op(struct nand_chip *chip);
1336 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1337 unsigned int len);
1338 int nand_status_op(struct nand_chip *chip, u8 *status);
1339 int nand_exit_status_op(struct nand_chip *chip);
1340 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1341 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1342 unsigned int offset_in_page, void *buf, unsigned int len);
1343 int nand_change_read_column_op(struct nand_chip *chip,
1344 unsigned int offset_in_page, void *buf,
1345 unsigned int len, bool force_8bit);
1346 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1347 unsigned int offset_in_page, void *buf, unsigned int len);
1348 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1349 unsigned int offset_in_page, const void *buf,
1350 unsigned int len);
1351 int nand_prog_page_end_op(struct nand_chip *chip);
1352 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1353 unsigned int offset_in_page, const void *buf,
1354 unsigned int len);
1355 int nand_change_write_column_op(struct nand_chip *chip,
1356 unsigned int offset_in_page, const void *buf,
1357 unsigned int len, bool force_8bit);
1358 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1359 bool force_8bit);
1360 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1361 unsigned int len, bool force_8bit);
1362
1363 /* Default extended ID decoding function */
1364 void nand_decode_ext_id(struct nand_chip *chip);
1365
1366 #endif /* __LINUX_MTD_RAWNAND_H */
1367