1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Nexell Co., Ltd.
4 *
5 * Author: junghyun, kim <jhkim@nexell.co.kr>
6 *
7 * Copyright (C) 2020 Stefan Bosch <stefan_b@posteo.net>
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <command.h>
13 #include <dm.h>
14 #include <mapmem.h>
15 #include <malloc.h>
16 #include <linux/compat.h>
17 #include <linux/err.h>
18 #include <video.h> /* For struct video_uc_plat */
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <asm/arch/display.h>
22 #include <asm/arch/display_dev.h>
23 #include "videomodes.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)
28 static struct nx_display_dev *dp_dev;
29 #endif
30
31 static char *const dp_dev_str[] = {
32 [DP_DEVICE_RESCONV] = "RESCONV",
33 [DP_DEVICE_RGBLCD] = "LCD",
34 [DP_DEVICE_HDMI] = "HDMI",
35 [DP_DEVICE_MIPI] = "MiPi",
36 [DP_DEVICE_LVDS] = "LVDS",
37 [DP_DEVICE_CVBS] = "TVOUT",
38 [DP_DEVICE_DP0] = "DP0",
39 [DP_DEVICE_DP1] = "DP1",
40 };
41
42 #if CONFIG_IS_ENABLED(OF_CONTROL)
nx_display_parse_dp_sync(ofnode node,struct dp_sync_info * sync)43 static void nx_display_parse_dp_sync(ofnode node, struct dp_sync_info *sync)
44 {
45 sync->h_active_len = ofnode_read_s32_default(node, "h_active_len", 0);
46 sync->h_sync_width = ofnode_read_s32_default(node, "h_sync_width", 0);
47 sync->h_back_porch = ofnode_read_s32_default(node, "h_back_porch", 0);
48 sync->h_front_porch = ofnode_read_s32_default(node, "h_front_porch", 0);
49 sync->h_sync_invert = ofnode_read_s32_default(node, "h_sync_invert", 0);
50 sync->v_active_len = ofnode_read_s32_default(node, "v_active_len", 0);
51 sync->v_sync_width = ofnode_read_s32_default(node, "v_sync_width", 0);
52 sync->v_back_porch = ofnode_read_s32_default(node, "v_back_porch", 0);
53 sync->v_front_porch = ofnode_read_s32_default(node, "v_front_porch", 0);
54 sync->v_sync_invert = ofnode_read_s32_default(node, "v_sync_invert", 0);
55 sync->pixel_clock_hz = ofnode_read_s32_default(node, "pixel_clock_hz", 0);
56
57 debug("DP: sync ->\n");
58 debug("ha:%d, hs:%d, hb:%d, hf:%d, hi:%d\n",
59 sync->h_active_len, sync->h_sync_width,
60 sync->h_back_porch, sync->h_front_porch, sync->h_sync_invert);
61 debug("va:%d, vs:%d, vb:%d, vf:%d, vi:%d\n",
62 sync->v_active_len, sync->v_sync_width,
63 sync->v_back_porch, sync->v_front_porch, sync->v_sync_invert);
64 }
65
nx_display_parse_dp_ctrl(ofnode node,struct dp_ctrl_info * ctrl)66 static void nx_display_parse_dp_ctrl(ofnode node, struct dp_ctrl_info *ctrl)
67 {
68 /* clock gen */
69 ctrl->clk_src_lv0 = ofnode_read_s32_default(node, "clk_src_lv0", 0);
70 ctrl->clk_div_lv0 = ofnode_read_s32_default(node, "clk_div_lv0", 0);
71 ctrl->clk_src_lv1 = ofnode_read_s32_default(node, "clk_src_lv1", 0);
72 ctrl->clk_div_lv1 = ofnode_read_s32_default(node, "clk_div_lv1", 0);
73
74 /* scan format */
75 ctrl->interlace = ofnode_read_s32_default(node, "interlace", 0);
76
77 /* syncgen format */
78 ctrl->out_format = ofnode_read_s32_default(node, "out_format", 0);
79 ctrl->invert_field = ofnode_read_s32_default(node, "invert_field", 0);
80 ctrl->swap_RB = ofnode_read_s32_default(node, "swap_RB", 0);
81 ctrl->yc_order = ofnode_read_s32_default(node, "yc_order", 0);
82
83 /* extern sync delay */
84 ctrl->delay_mask = ofnode_read_s32_default(node, "delay_mask", 0);
85 ctrl->d_rgb_pvd = ofnode_read_s32_default(node, "d_rgb_pvd", 0);
86 ctrl->d_hsync_cp1 = ofnode_read_s32_default(node, "d_hsync_cp1", 0);
87 ctrl->d_vsync_fram = ofnode_read_s32_default(node, "d_vsync_fram", 0);
88 ctrl->d_de_cp2 = ofnode_read_s32_default(node, "d_de_cp2", 0);
89
90 /* extern sync delay */
91 ctrl->vs_start_offset =
92 ofnode_read_s32_default(node, "vs_start_offset", 0);
93 ctrl->vs_end_offset = ofnode_read_s32_default(node, "vs_end_offset", 0);
94 ctrl->ev_start_offset =
95 ofnode_read_s32_default(node, "ev_start_offset", 0);
96 ctrl->ev_end_offset = ofnode_read_s32_default(node, "ev_end_offset", 0);
97
98 /* pad clock seletor */
99 ctrl->vck_select = ofnode_read_s32_default(node, "vck_select", 0);
100 ctrl->clk_inv_lv0 = ofnode_read_s32_default(node, "clk_inv_lv0", 0);
101 ctrl->clk_delay_lv0 = ofnode_read_s32_default(node, "clk_delay_lv0", 0);
102 ctrl->clk_inv_lv1 = ofnode_read_s32_default(node, "clk_inv_lv1", 0);
103 ctrl->clk_delay_lv1 = ofnode_read_s32_default(node, "clk_delay_lv1", 0);
104 ctrl->clk_sel_div1 = ofnode_read_s32_default(node, "clk_sel_div1", 0);
105
106 debug("DP: ctrl [%s] ->\n",
107 ctrl->interlace ? "Interlace" : " Progressive");
108 debug("cs0:%d, cd0:%d, cs1:%d, cd1:%d\n",
109 ctrl->clk_src_lv0, ctrl->clk_div_lv0,
110 ctrl->clk_src_lv1, ctrl->clk_div_lv1);
111 debug("fmt:0x%x, inv:%d, swap:%d, yb:0x%x\n",
112 ctrl->out_format, ctrl->invert_field,
113 ctrl->swap_RB, ctrl->yc_order);
114 debug("dm:0x%x, drp:%d, dhs:%d, dvs:%d, dde:0x%x\n",
115 ctrl->delay_mask, ctrl->d_rgb_pvd,
116 ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2);
117 debug("vss:%d, vse:%d, evs:%d, eve:%d\n",
118 ctrl->vs_start_offset, ctrl->vs_end_offset,
119 ctrl->ev_start_offset, ctrl->ev_end_offset);
120 debug("sel:%d, i0:%d, d0:%d, i1:%d, d1:%d, s1:%d\n",
121 ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0,
122 ctrl->clk_inv_lv1, ctrl->clk_delay_lv1, ctrl->clk_sel_div1);
123 }
124
nx_display_parse_dp_top_layer(ofnode node,struct dp_plane_top * top)125 static void nx_display_parse_dp_top_layer(ofnode node, struct dp_plane_top *top)
126 {
127 top->screen_width = ofnode_read_s32_default(node, "screen_width", 0);
128 top->screen_height = ofnode_read_s32_default(node, "screen_height", 0);
129 top->video_prior = ofnode_read_s32_default(node, "video_prior", 0);
130 top->interlace = ofnode_read_s32_default(node, "interlace", 0);
131 top->back_color = ofnode_read_s32_default(node, "back_color", 0);
132 top->plane_num = DP_PLANS_NUM;
133
134 debug("DP: top [%s] ->\n",
135 top->interlace ? "Interlace" : " Progressive");
136 debug("w:%d, h:%d, prior:%d, bg:0x%x\n",
137 top->screen_width, top->screen_height,
138 top->video_prior, top->back_color);
139 }
140
nx_display_parse_dp_layer(ofnode node,struct dp_plane_info * plane)141 static void nx_display_parse_dp_layer(ofnode node, struct dp_plane_info *plane)
142 {
143 plane->left = ofnode_read_s32_default(node, "left", 0);
144 plane->width = ofnode_read_s32_default(node, "width", 0);
145 plane->top = ofnode_read_s32_default(node, "top", 0);
146 plane->height = ofnode_read_s32_default(node, "height", 0);
147 plane->pixel_byte = ofnode_read_s32_default(node, "pixel_byte", 0);
148 plane->format = ofnode_read_s32_default(node, "format", 0);
149 plane->alpha_on = ofnode_read_s32_default(node, "alpha_on", 0);
150 plane->alpha_depth = ofnode_read_s32_default(node, "alpha", 0);
151 plane->tp_on = ofnode_read_s32_default(node, "tp_on", 0);
152 plane->tp_color = ofnode_read_s32_default(node, "tp_color", 0);
153
154 /* enable layer */
155 if (plane->fb_base)
156 plane->enable = 1;
157 else
158 plane->enable = 0;
159
160 if (plane->fb_base == 0) {
161 printf("fail : dp plane.%d invalid fb base [0x%x] ->\n",
162 plane->layer, plane->fb_base);
163 return;
164 }
165
166 debug("DP: plane.%d [0x%x] ->\n", plane->layer, plane->fb_base);
167 debug("f:0x%x, l:%d, t:%d, %d * %d, bpp:%d, a:%d(%d), t:%d(0x%x)\n",
168 plane->format, plane->left, plane->top, plane->width,
169 plane->height, plane->pixel_byte, plane->alpha_on,
170 plane->alpha_depth, plane->tp_on, plane->tp_color);
171 }
172
nx_display_parse_dp_planes(ofnode node,struct nx_display_dev * dp,struct video_uc_plat * plat)173 static void nx_display_parse_dp_planes(ofnode node,
174 struct nx_display_dev *dp,
175 struct video_uc_plat *plat)
176 {
177 const char *name;
178 ofnode subnode;
179
180 ofnode_for_each_subnode(subnode, node) {
181 name = ofnode_get_name(subnode);
182
183 if (strcmp(name, "layer_top") == 0)
184 nx_display_parse_dp_top_layer(subnode, &dp->top);
185
186 /*
187 * TODO: Is it sure that only one layer is used? Otherwise
188 * fb_base must be different?
189 */
190 if (strcmp(name, "layer_0") == 0) {
191 dp->planes[0].fb_base =
192 (uint)map_sysmem(plat->base, plat->size);
193 debug("%s(): dp->planes[0].fb_base == 0x%x\n", __func__,
194 (uint)dp->planes[0].fb_base);
195 nx_display_parse_dp_layer(subnode, &dp->planes[0]);
196 }
197
198 if (strcmp(name, "layer_1") == 0) {
199 dp->planes[1].fb_base =
200 (uint)map_sysmem(plat->base, plat->size);
201 debug("%s(): dp->planes[1].fb_base == 0x%x\n", __func__,
202 (uint)dp->planes[1].fb_base);
203 nx_display_parse_dp_layer(subnode, &dp->planes[1]);
204 }
205
206 if (strcmp(name, "layer_2") == 0) {
207 dp->planes[2].fb_base =
208 (uint)map_sysmem(plat->base, plat->size);
209 debug("%s(): dp->planes[2].fb_base == 0x%x\n", __func__,
210 (uint)dp->planes[2].fb_base);
211 nx_display_parse_dp_layer(subnode, &dp->planes[2]);
212 }
213 }
214 }
215
nx_display_parse_dp_lvds(ofnode node,struct nx_display_dev * dp)216 static int nx_display_parse_dp_lvds(ofnode node, struct nx_display_dev *dp)
217 {
218 struct dp_lvds_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
219
220 if (!dev) {
221 printf("failed to allocate display LVDS object.\n");
222 return -ENOMEM;
223 }
224
225 dp->device = dev;
226
227 dev->lvds_format = ofnode_read_s32_default(node, "format", 0);
228 dev->pol_inv_hs = ofnode_read_s32_default(node, "pol_inv_hs", 0);
229 dev->pol_inv_vs = ofnode_read_s32_default(node, "pol_inv_vs", 0);
230 dev->pol_inv_de = ofnode_read_s32_default(node, "pol_inv_de", 0);
231 dev->pol_inv_ck = ofnode_read_s32_default(node, "pol_inv_ck", 0);
232 dev->voltage_level = ofnode_read_s32_default(node, "voltage_level", 0);
233
234 if (!dev->voltage_level)
235 dev->voltage_level = DEF_VOLTAGE_LEVEL;
236
237 debug("DP: LVDS -> %s, voltage LV:0x%x\n",
238 dev->lvds_format == DP_LVDS_FORMAT_VESA ? "VESA" :
239 dev->lvds_format == DP_LVDS_FORMAT_JEIDA ? "JEIDA" : "LOC",
240 dev->voltage_level);
241 debug("pol inv hs:%d, vs:%d, de:%d, ck:%d\n",
242 dev->pol_inv_hs, dev->pol_inv_vs,
243 dev->pol_inv_de, dev->pol_inv_ck);
244
245 return 0;
246 }
247
nx_display_parse_dp_rgb(ofnode node,struct nx_display_dev * dp)248 static int nx_display_parse_dp_rgb(ofnode node, struct nx_display_dev *dp)
249 {
250 struct dp_rgb_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
251
252 if (!dev) {
253 printf("failed to allocate display RGB LCD object.\n");
254 return -ENOMEM;
255 }
256 dp->device = dev;
257
258 dev->lcd_mpu_type = ofnode_read_s32_default(node, "lcd_mpu_type", 0);
259
260 debug("DP: RGB -> MPU[%s]\n", dev->lcd_mpu_type ? "O" : "X");
261 return 0;
262 }
263
nx_display_parse_dp_mipi(ofnode node,struct nx_display_dev * dp)264 static int nx_display_parse_dp_mipi(ofnode node, struct nx_display_dev *dp)
265 {
266 struct dp_mipi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
267
268 if (!dev) {
269 printf("failed to allocate display MiPi object.\n");
270 return -ENOMEM;
271 }
272 dp->device = dev;
273
274 dev->lp_bitrate = ofnode_read_s32_default(node, "lp_bitrate", 0);
275 dev->hs_bitrate = ofnode_read_s32_default(node, "hs_bitrate", 0);
276 dev->lpm_trans = 1;
277 dev->command_mode = 0;
278
279 debug("DP: MIPI ->\n");
280 debug("lp:%dmhz, hs:%dmhz\n", dev->lp_bitrate, dev->hs_bitrate);
281
282 return 0;
283 }
284
nx_display_parse_dp_hdmi(ofnode node,struct nx_display_dev * dp)285 static int nx_display_parse_dp_hdmi(ofnode node, struct nx_display_dev *dp)
286 {
287 struct dp_hdmi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
288
289 if (!dev) {
290 printf("failed to allocate display HDMI object.\n");
291 return -ENOMEM;
292 }
293 dp->device = dev;
294
295 dev->preset = ofnode_read_s32_default(node, "preset", 0);
296
297 debug("DP: HDMI -> %d\n", dev->preset);
298
299 return 0;
300 }
301
nx_display_parse_dp_lcds(ofnode node,const char * type,struct nx_display_dev * dp)302 static int nx_display_parse_dp_lcds(ofnode node, const char *type,
303 struct nx_display_dev *dp)
304 {
305 if (strcmp(type, "lvds") == 0) {
306 dp->dev_type = DP_DEVICE_LVDS;
307 return nx_display_parse_dp_lvds(node, dp);
308 } else if (strcmp(type, "rgb") == 0) {
309 dp->dev_type = DP_DEVICE_RGBLCD;
310 return nx_display_parse_dp_rgb(node, dp);
311 } else if (strcmp(type, "mipi") == 0) {
312 dp->dev_type = DP_DEVICE_MIPI;
313 return nx_display_parse_dp_mipi(node, dp);
314 } else if (strcmp(type, "hdmi") == 0) {
315 dp->dev_type = DP_DEVICE_HDMI;
316 return nx_display_parse_dp_hdmi(node, dp);
317 }
318
319 printf("%s: node %s unknown display type\n", __func__,
320 ofnode_get_name(node));
321 return -EINVAL;
322
323 return 0;
324 }
325
326 #define DT_SYNC (1 << 0)
327 #define DT_CTRL (1 << 1)
328 #define DT_PLANES (1 << 2)
329 #define DT_DEVICE (1 << 3)
330
nx_display_parse_dt(struct udevice * dev,struct nx_display_dev * dp,struct video_uc_plat * plat)331 static int nx_display_parse_dt(struct udevice *dev,
332 struct nx_display_dev *dp,
333 struct video_uc_plat *plat)
334 {
335 const char *name, *dtype;
336 int ret = 0;
337 unsigned int dt_status = 0;
338 ofnode subnode;
339
340 if (!dev)
341 return -ENODEV;
342
343 dp->module = dev_read_s32_default(dev, "module", -1);
344 if (dp->module == -1)
345 dp->module = dev_read_s32_default(dev, "index", 0);
346
347 dtype = dev_read_string(dev, "lcd-type");
348
349 ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
350 name = ofnode_get_name(subnode);
351
352 if (strcmp("dp-sync", name) == 0) {
353 dt_status |= DT_SYNC;
354 nx_display_parse_dp_sync(subnode, &dp->sync);
355 }
356
357 if (strcmp("dp-ctrl", name) == 0) {
358 dt_status |= DT_CTRL;
359 nx_display_parse_dp_ctrl(subnode, &dp->ctrl);
360 }
361
362 if (strcmp("dp-planes", name) == 0) {
363 dt_status |= DT_PLANES;
364 nx_display_parse_dp_planes(subnode, dp, plat);
365 }
366
367 if (strcmp("dp-device", name) == 0) {
368 dt_status |= DT_DEVICE;
369 ret = nx_display_parse_dp_lcds(subnode, dtype, dp);
370 }
371 }
372
373 if (dt_status != (DT_SYNC | DT_CTRL | DT_PLANES | DT_DEVICE)) {
374 printf("Not enough DT config for display [0x%x]\n", dt_status);
375 return -ENODEV;
376 }
377
378 return ret;
379 }
380 #endif
381
nx_display_fixup_dp(struct nx_display_dev * dp)382 __weak int nx_display_fixup_dp(struct nx_display_dev *dp)
383 {
384 return 0;
385 }
386
nx_display_setup(void)387 static struct nx_display_dev *nx_display_setup(void)
388 {
389 struct nx_display_dev *dp;
390 int i, ret;
391 int node = 0;
392 struct video_uc_plat *plat = NULL;
393
394 struct udevice *dev;
395
396 /* call driver probe */
397 debug("DT: uclass device call...\n");
398
399 ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
400 if (ret) {
401 debug("%s(): uclass_get_device(UCLASS_VIDEO, 0, &dev) != 0 --> return NULL\n",
402 __func__);
403 return NULL;
404 }
405 plat = dev_get_uclass_plat(dev);
406 if (!dev) {
407 debug("%s(): dev_get_uclass_plat(dev) == NULL --> return NULL\n",
408 __func__);
409 return NULL;
410 }
411 dp = dev_get_priv(dev);
412 if (!dp) {
413 debug("%s(): dev_get_priv(dev) == NULL --> return NULL\n",
414 __func__);
415 return NULL;
416 }
417 node = dev_ofnode(dev).of_offset;
418
419 if (CONFIG_IS_ENABLED(OF_CONTROL)) {
420 ret = nx_display_parse_dt(dev, dp, plat);
421 if (ret)
422 goto err_setup;
423 }
424
425 nx_display_fixup_dp(dp);
426
427 for (i = 0; dp->top.plane_num > i; i++) {
428 dp->planes[i].layer = i;
429 if (dp->planes[i].enable && !dp->fb_plane) {
430 dp->fb_plane = &dp->planes[i];
431 dp->fb_addr = dp->fb_plane->fb_base;
432 dp->depth = dp->fb_plane->pixel_byte;
433 }
434 }
435
436 switch (dp->dev_type) {
437 #ifdef CONFIG_VIDEO_NX_RGB
438 case DP_DEVICE_RGBLCD:
439 nx_rgb_display(dp->module,
440 &dp->sync, &dp->ctrl, &dp->top,
441 dp->planes, (struct dp_rgb_dev *)dp->device);
442 break;
443 #endif
444 #ifdef CONFIG_VIDEO_NX_LVDS
445 case DP_DEVICE_LVDS:
446 nx_lvds_display(dp->module,
447 &dp->sync, &dp->ctrl, &dp->top,
448 dp->planes, (struct dp_lvds_dev *)dp->device);
449 break;
450 #endif
451 #ifdef CONFIG_VIDEO_NX_MIPI
452 case DP_DEVICE_MIPI:
453 nx_mipi_display(dp->module,
454 &dp->sync, &dp->ctrl, &dp->top,
455 dp->planes, (struct dp_mipi_dev *)dp->device);
456 break;
457 #endif
458 #ifdef CONFIG_VIDEO_NX_HDMI
459 case DP_DEVICE_HDMI:
460 nx_hdmi_display(dp->module,
461 &dp->sync, &dp->ctrl, &dp->top,
462 dp->planes, (struct dp_hdmi_dev *)dp->device);
463 break;
464 #endif
465 default:
466 printf("fail : not support lcd type %d !!!\n", dp->dev_type);
467 goto err_setup;
468 };
469
470 printf("LCD: [%s] dp.%d.%d %dx%d %dbpp FB:0x%08x\n",
471 dp_dev_str[dp->dev_type], dp->module, dp->fb_plane->layer,
472 dp->fb_plane->width, dp->fb_plane->height, dp->depth * 8,
473 dp->fb_addr);
474
475 return dp;
476
477 err_setup:
478 kfree(dp);
479
480 return NULL;
481 }
482
nx_display_probe(struct udevice * dev)483 static int nx_display_probe(struct udevice *dev)
484 {
485 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
486 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
487 struct nx_display_plat *plat = dev_get_plat(dev);
488 char addr[64];
489
490 debug("%s()\n", __func__);
491
492 if (!dev)
493 return -EINVAL;
494
495 if (!uc_plat) {
496 debug("%s(): video_uc_plat *plat == NULL --> return -EINVAL\n",
497 __func__);
498 return -EINVAL;
499 }
500
501 if (!uc_priv) {
502 debug("%s(): video_priv *uc_priv == NULL --> return -EINVAL\n",
503 __func__);
504 return -EINVAL;
505 }
506
507 if (!plat) {
508 debug("%s(): nx_display_plat *plat == NULL --> return -EINVAL\n",
509 __func__);
510 return -EINVAL;
511 }
512
513 struct nx_display_dev *dp;
514
515 dp = nx_display_setup();
516 if (!dp) {
517 debug("%s(): nx_display_setup() == 0 --> return -EINVAL\n",
518 __func__);
519 return -EINVAL;
520 }
521
522 switch (dp->depth) {
523 case 2:
524 uc_priv->bpix = VIDEO_BPP16;
525 break;
526 case 3:
527 /* There is no VIDEO_BPP24 because these values are of
528 * type video_log2_bpp
529 */
530 case 4:
531 uc_priv->bpix = VIDEO_BPP32;
532 break;
533 default:
534 printf("fail : not support LCD bit per pixel %d\n",
535 dp->depth * 8);
536 return -EINVAL;
537 }
538
539 uc_priv->xsize = dp->fb_plane->width;
540 uc_priv->ysize = dp->fb_plane->height;
541 uc_priv->rot = 0;
542
543 /*
544 * set environment variable "fb_addr" (frame buffer address), required
545 * for splash image, which is not set if CONFIG_VIDEO is enabled).
546 */
547 sprintf(addr, "0x%x", dp->fb_addr);
548 debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr);
549 env_set("fb_addr", addr);
550
551 return 0;
552 }
553
nx_display_bind(struct udevice * dev)554 static int nx_display_bind(struct udevice *dev)
555 {
556 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
557
558 debug("%s()\n", __func__);
559
560 /* Datasheet S5p4418:
561 * Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI)
562 * Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01
563 * "#define CFG_FB_ADDR 0x77000000" and next address is
564 * "#define BMP_LOAD_ADDR 0x78000000"
565 */
566 plat->size = 0x1000000;
567
568 return 0;
569 }
570
571 static const struct udevice_id nx_display_ids[] = {
572 {.compatible = "nexell,nexell-display", },
573 {}
574 };
575
576 U_BOOT_DRIVER(nexell_display) = {
577 .name = "nexell-display",
578 .id = UCLASS_VIDEO,
579 .of_match = nx_display_ids,
580 .plat_auto = sizeof(struct nx_display_plat),
581 .bind = nx_display_bind,
582 .probe = nx_display_probe,
583 .priv_auto = sizeof(struct nx_display_dev),
584 };
585