1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <mtd.h>
11 #include <linux/bitops.h>
12 #include <linux/mtd/cfi.h>
13 #include <linux/mtd/mtd.h>
14 #include <spi-mem.h>
15
16 /*
17 * Manufacturer IDs
18 *
19 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
20 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
21 */
22 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
23 #define SNOR_MFR_GIGADEVICE 0xc8
24 #define SNOR_MFR_INTEL CFI_MFR_INTEL
25 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
26 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
27 #define SNOR_MFR_ISSI CFI_MFR_PMC
28 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
29 #define SNOR_MFR_SPANSION CFI_MFR_AMD
30 #define SNOR_MFR_SST CFI_MFR_SST
31 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
32 #define SNOR_MFR_CYPRESS 0x34
33
34 /*
35 * Note on opcode nomenclature: some opcodes have a format like
36 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
37 * of I/O lines used for the opcode, address, and data (respectively). The
38 * FUNCTION has an optional suffix of '4', to represent an opcode which
39 * requires a 4-byte (32-bit) address.
40 */
41
42 /* Flash opcodes. */
43 #define SPINOR_OP_WREN 0x06 /* Write enable */
44 #define SPINOR_OP_RDSR 0x05 /* Read status register */
45 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
46 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
47 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
48 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
49 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
50 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
51 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
52 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
53 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
54 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
55 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
56 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
57 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
58 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
59 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
60 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
61 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
62 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
63 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
64 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
65 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
66 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
67 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
68 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
69 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
70 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
71 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
72 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
73 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
74 #define SPINOR_OP_SRST 0x99 /* Software Reset */
75
76 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
77 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
78 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
79 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
80 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
81 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
82 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
83 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
84 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
85 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
86 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
87 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
88 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
89 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
90 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
91 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
92 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
93
94 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
95 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
96 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
97 #define SPINOR_OP_READ_1_4_4_DTR 0xed
98
99 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
100 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
101 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
102
103 /* Used for SST flashes only. */
104 #define SPINOR_OP_BP 0x02 /* Byte program */
105 #define SPINOR_OP_WRDI 0x04 /* Write disable */
106 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
107
108 /* Used for SST26* flashes only. */
109 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
110 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
111
112 /* Used for S3AN flashes only */
113 #define SPINOR_OP_XSE 0x50 /* Sector erase */
114 #define SPINOR_OP_XPP 0x82 /* Page program */
115 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
116
117 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
118 #define XSR_RDY BIT(7) /* Ready */
119
120 /* Used for Macronix and Winbond flashes. */
121 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
122 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
123 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
124 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
125 #define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
126 #define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
127 #define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
128 #define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
129 #define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
130 #define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */
131 #define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */
132 #define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
133
134 /* Used for Spansion flashes only. */
135 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
136 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
137 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
138 #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
139 #define SPINOR_OP_RDAR 0x65 /* Read any register */
140 #define SPINOR_OP_WRAR 0x71 /* Write any register */
141 #define SPINOR_REG_ADDR_STR1V 0x00800000
142 #define SPINOR_REG_ADDR_CFR1V 0x00800002
143 #define SPINOR_REG_ADDR_CFR3V 0x00800004
144 #define SPINOR_REG_ADDR_ARCFN 0x00000006
145 #define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
146 #define CFR3V_PGMBUF BIT(4) /* Program buffer size */
147
148 /* Used for Micron flashes only. */
149 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
150 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
151 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
152 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
153 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
154 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
155 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
156 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */
157
158 /* Status Register bits. */
159 #define SR_WIP BIT(0) /* Write in progress */
160 #define SR_WEL BIT(1) /* Write enable latch */
161 /* meaning of other SR_* bits may differ between vendors */
162 #define SR_BP0 BIT(2) /* Block protect 0 */
163 #define SR_BP1 BIT(3) /* Block protect 1 */
164 #define SR_BP2 BIT(4) /* Block protect 2 */
165 #define SR_TB BIT(5) /* Top/Bottom protect */
166 #define SR_SRWD BIT(7) /* SR write protect */
167 /* Spansion/Cypress specific status bits */
168 #define SR_E_ERR BIT(5)
169 #define SR_P_ERR BIT(6)
170
171 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
172
173 /* Enhanced Volatile Configuration Register bits */
174 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
175
176 /* Flag Status Register bits */
177 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
178 #define FSR_E_ERR BIT(5) /* Erase operation status */
179 #define FSR_P_ERR BIT(4) /* Program operation status */
180 #define FSR_PT_ERR BIT(1) /* Protection error bit */
181
182 /* Configuration Register bits. */
183 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
184
185 /* Status Register 2 bits. */
186 #define SR2_QUAD_EN_BIT7 BIT(7)
187
188 /* For Cypress flash. */
189 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
190 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
191 #define SPINOR_OP_S28_SE_4K 0x21
192 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
193 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
194 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
195 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
196 #define SPINOR_REG_CYPRESS_CFR3_UNISECT BIT(3) /* Uniform sector mode */
197 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006
198 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
199 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
200 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
201 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \
202 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
203 SPINOR_REG_CYPRESS_CFR5_OPI)
204 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
205
206 /* Supported SPI protocols */
207 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
208 #define SNOR_PROTO_INST_SHIFT 16
209 #define SNOR_PROTO_INST(_nbits) \
210 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
211 SNOR_PROTO_INST_MASK)
212
213 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
214 #define SNOR_PROTO_ADDR_SHIFT 8
215 #define SNOR_PROTO_ADDR(_nbits) \
216 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
217 SNOR_PROTO_ADDR_MASK)
218
219 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
220 #define SNOR_PROTO_DATA_SHIFT 0
221 #define SNOR_PROTO_DATA(_nbits) \
222 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
223 SNOR_PROTO_DATA_MASK)
224
225 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
226
227 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
228 (SNOR_PROTO_INST(_inst_nbits) | \
229 SNOR_PROTO_ADDR(_addr_nbits) | \
230 SNOR_PROTO_DATA(_data_nbits))
231 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
232 (SNOR_PROTO_IS_DTR | \
233 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
234
235 enum spi_nor_protocol {
236 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
237 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
238 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
239 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
240 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
241 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
242 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
243 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
244 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
245 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
246
247 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
248 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
249 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
250 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
251 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
252 };
253
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)254 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
255 {
256 return !!(proto & SNOR_PROTO_IS_DTR);
257 }
258
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)259 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
260 {
261 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
262 SNOR_PROTO_INST_SHIFT;
263 }
264
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)265 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
266 {
267 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
268 SNOR_PROTO_ADDR_SHIFT;
269 }
270
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)271 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
272 {
273 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
274 SNOR_PROTO_DATA_SHIFT;
275 }
276
spi_nor_get_protocol_width(enum spi_nor_protocol proto)277 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
278 {
279 return spi_nor_get_protocol_data_nbits(proto);
280 }
281
282 #define SPI_NOR_MAX_CMD_SIZE 8
283 enum spi_nor_ops {
284 SPI_NOR_OPS_READ = 0,
285 SPI_NOR_OPS_WRITE,
286 SPI_NOR_OPS_ERASE,
287 SPI_NOR_OPS_LOCK,
288 SPI_NOR_OPS_UNLOCK,
289 };
290
291 enum spi_nor_option_flags {
292 SNOR_F_USE_FSR = BIT(0),
293 SNOR_F_HAS_SR_TB = BIT(1),
294 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
295 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
296 SNOR_F_READY_XSR_RDY = BIT(4),
297 SNOR_F_USE_CLSR = BIT(5),
298 SNOR_F_BROKEN_RESET = BIT(6),
299 SNOR_F_SOFT_RESET = BIT(7),
300 SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
301 };
302
303 struct spi_nor;
304
305 /**
306 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
307 * supported by the SPI controller (bus master).
308 * @mask: the bitmask listing all the supported hw capabilies
309 */
310 struct spi_nor_hwcaps {
311 u32 mask;
312 };
313
314 /*
315 *(Fast) Read capabilities.
316 * MUST be ordered by priority: the higher bit position, the higher priority.
317 * As a matter of performances, it is relevant to use Octo SPI protocols first,
318 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
319 * (Slow) Read.
320 */
321 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
322 #define SNOR_HWCAPS_READ BIT(0)
323 #define SNOR_HWCAPS_READ_FAST BIT(1)
324 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
325
326 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
327 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
328 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
329 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
330 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
331
332 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
333 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
334 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
335 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
336 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
337
338 #define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
339 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
340 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
341 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
342 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
343 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
344
345 /*
346 * Page Program capabilities.
347 * MUST be ordered by priority: the higher bit position, the higher priority.
348 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
349 * legacy SPI 1-1-1 protocol.
350 * Note that Dual Page Programs are not supported because there is no existing
351 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
352 * implements such commands.
353 */
354 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
355 #define SNOR_HWCAPS_PP BIT(16)
356
357 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
358 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
359 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
360 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
361
362 #define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
363 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
364 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
365 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
366 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
367
368 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
369 SNOR_HWCAPS_READ_4_4_4 | \
370 SNOR_HWCAPS_READ_8_8_8 | \
371 SNOR_HWCAPS_PP_4_4_4 | \
372 SNOR_HWCAPS_PP_8_8_8)
373
374 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
375 SNOR_HWCAPS_PP_8_8_8_DTR)
376
377 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
378 SNOR_HWCAPS_READ_1_2_2_DTR | \
379 SNOR_HWCAPS_READ_1_4_4_DTR | \
380 SNOR_HWCAPS_READ_1_8_8_DTR)
381
382 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
383 SNOR_HWCAPS_PP_MASK)
384
385 struct spi_nor_read_command {
386 u8 num_mode_clocks;
387 u8 num_wait_states;
388 u8 opcode;
389 enum spi_nor_protocol proto;
390 };
391
392 struct spi_nor_pp_command {
393 u8 opcode;
394 enum spi_nor_protocol proto;
395 };
396
397 enum spi_nor_read_command_index {
398 SNOR_CMD_READ,
399 SNOR_CMD_READ_FAST,
400 SNOR_CMD_READ_1_1_1_DTR,
401
402 /* Dual SPI */
403 SNOR_CMD_READ_1_1_2,
404 SNOR_CMD_READ_1_2_2,
405 SNOR_CMD_READ_2_2_2,
406 SNOR_CMD_READ_1_2_2_DTR,
407
408 /* Quad SPI */
409 SNOR_CMD_READ_1_1_4,
410 SNOR_CMD_READ_1_4_4,
411 SNOR_CMD_READ_4_4_4,
412 SNOR_CMD_READ_1_4_4_DTR,
413
414 /* Octo SPI */
415 SNOR_CMD_READ_1_1_8,
416 SNOR_CMD_READ_1_8_8,
417 SNOR_CMD_READ_8_8_8,
418 SNOR_CMD_READ_1_8_8_DTR,
419 SNOR_CMD_READ_8_8_8_DTR,
420
421 SNOR_CMD_READ_MAX
422 };
423
424 enum spi_nor_pp_command_index {
425 SNOR_CMD_PP,
426
427 /* Quad SPI */
428 SNOR_CMD_PP_1_1_4,
429 SNOR_CMD_PP_1_4_4,
430 SNOR_CMD_PP_4_4_4,
431
432 /* Octo SPI */
433 SNOR_CMD_PP_1_1_8,
434 SNOR_CMD_PP_1_8_8,
435 SNOR_CMD_PP_8_8_8,
436 SNOR_CMD_PP_8_8_8_DTR,
437
438 SNOR_CMD_PP_MAX
439 };
440
441 struct spi_nor_flash_parameter {
442 u64 size;
443 u32 page_size;
444 u8 rdsr_dummy;
445 u8 rdsr_addr_nbytes;
446
447 struct spi_nor_hwcaps hwcaps;
448 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
449 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
450
451 int (*quad_enable)(struct spi_nor *nor);
452 };
453
454 /**
455 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
456 * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy
457 * SPI mode
458 * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
459 * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode
460 * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode
461 * combine to form a 16-bit opcode.
462 */
463 enum spi_nor_cmd_ext {
464 SPI_NOR_EXT_NONE = 0,
465 SPI_NOR_EXT_REPEAT,
466 SPI_NOR_EXT_INVERT,
467 SPI_NOR_EXT_HEX,
468 };
469
470 /**
471 * struct flash_info - Forward declaration of a structure used internally by
472 * spi_nor_scan()
473 */
474 struct flash_info;
475
476 /*
477 * TODO: Remove, once all users of spi_flash interface are moved to MTD
478 *
479 struct spi_flash {
480 * Defined below (keep this text to enable searching for spi_flash decl)
481 * }
482 */
483 #ifndef DT_PLAT_C
484 #define spi_flash spi_nor
485 #endif
486
487 /**
488 * struct spi_nor - Structure for defining a the SPI NOR layer
489 * @mtd: point to a mtd_info structure
490 * @lock: the lock for the read/write/erase/lock/unlock operations
491 * @dev: point to a spi device, or a spi nor controller device.
492 * @info: spi-nor part JDEC MFR id and other info
493 * @manufacturer_sfdp: manufacturer specific SFDP table
494 * @page_size: the page size of the SPI NOR
495 * @addr_width: number of address bytes
496 * @erase_opcode: the opcode for erasing a sector
497 * @read_opcode: the read opcode
498 * @read_dummy: the dummy needed by the read operation
499 * @program_opcode: the program opcode
500 * @rdsr_dummy dummy cycles needed for Read Status Register command.
501 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
502 * command.
503 * @addr_mode_nbytes: number of address bytes of current address mode. Useful
504 * when the flash operates with 4B opcodes but needs the
505 * internal address mode for opcodes that don't have a 4B
506 * opcode correspondent.
507 * @bank_read_cmd: Bank read cmd
508 * @bank_write_cmd: Bank write cmd
509 * @bank_curr: Current flash bank
510 * @sst_write_second: used by the SST write operation
511 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
512 * @read_proto: the SPI protocol for read operations
513 * @write_proto: the SPI protocol for write operations
514 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
515 * @cmd_buf: used by the write_reg
516 * @cmd_ext_type: the command opcode extension for DTR mode.
517 * @fixups: flash-specific fixup hooks.
518 * @prepare: [OPTIONAL] do some preparations for the
519 * read/write/erase/lock/unlock operations
520 * @unprepare: [OPTIONAL] do some post work after the
521 * read/write/erase/lock/unlock operations
522 * @read_reg: [DRIVER-SPECIFIC] read out the register
523 * @write_reg: [DRIVER-SPECIFIC] write data to the register
524 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
525 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
526 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
527 * at the offset @offs; if not provided by the driver,
528 * spi-nor will send the erase opcode via write_reg()
529 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
530 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
531 * @flash_is_unlocked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
532 * completely unlocked
533 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
534 * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
535 * @ready: [FLASH-SPECIFIC] check if the flash is ready
536 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
537 * @priv: the private data
538 */
539 struct spi_nor {
540 struct mtd_info mtd;
541 struct udevice *dev;
542 struct spi_slave *spi;
543 const struct flash_info *info;
544 u8 *manufacturer_sfdp;
545 u32 page_size;
546 u8 addr_width;
547 u8 erase_opcode;
548 u8 read_opcode;
549 u8 read_dummy;
550 u8 program_opcode;
551 u8 rdsr_dummy;
552 u8 rdsr_addr_nbytes;
553 u8 addr_mode_nbytes;
554 #ifdef CONFIG_SPI_FLASH_BAR
555 u8 bank_read_cmd;
556 u8 bank_write_cmd;
557 u8 bank_curr;
558 #endif
559 enum spi_nor_protocol read_proto;
560 enum spi_nor_protocol write_proto;
561 enum spi_nor_protocol reg_proto;
562 bool sst_write_second;
563 u32 flags;
564 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
565 enum spi_nor_cmd_ext cmd_ext_type;
566 struct spi_nor_fixups *fixups;
567
568 int (*setup)(struct spi_nor *nor, const struct flash_info *info,
569 const struct spi_nor_flash_parameter *params);
570 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
571 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
572 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
573 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
574
575 ssize_t (*read)(struct spi_nor *nor, loff_t from,
576 size_t len, u_char *read_buf);
577 ssize_t (*write)(struct spi_nor *nor, loff_t to,
578 size_t len, const u_char *write_buf);
579 int (*erase)(struct spi_nor *nor, loff_t offs);
580
581 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
582 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
583 int (*flash_is_unlocked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
584 int (*quad_enable)(struct spi_nor *nor);
585 int (*octal_dtr_enable)(struct spi_nor *nor);
586 int (*ready)(struct spi_nor *nor);
587
588 struct {
589 struct spi_mem_dirmap_desc *rdesc;
590 struct spi_mem_dirmap_desc *wdesc;
591 } dirmap;
592
593 void *priv;
594 char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
595 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
596 const char *name;
597 u32 size;
598 u32 sector_size;
599 u32 erase_size;
600 };
601
602 #ifndef __UBOOT__
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)603 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
604 const struct device_node *np)
605 {
606 mtd_set_of_node(&nor->mtd, np);
607 }
608
609 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)610 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
611 {
612 return mtd_get_of_node(&nor->mtd);
613 }
614 #endif /* __UBOOT__ */
615
616 /**
617 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
618 * @nor: pointer to a 'struct spi_nor'
619 * @op: pointer to the 'struct spi_mem_op' whose properties
620 * need to be initialized.
621 * @proto: the protocol from which the properties need to be set.
622 */
623 void spi_nor_setup_op(const struct spi_nor *nor,
624 struct spi_mem_op *op,
625 const enum spi_nor_protocol proto);
626
627 /**
628 * spi_nor_scan() - scan the SPI NOR
629 * @nor: the spi_nor structure
630 *
631 * The drivers can use this function to scan the SPI NOR.
632 * In the scanning, it will try to get all the necessary information to
633 * fill the mtd_info{} and the spi_nor{}.
634 *
635 * Return: 0 for success, others for failure.
636 */
637 int spi_nor_scan(struct spi_nor *nor);
638
639 #if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
spi_nor_remove(struct spi_nor * nor)640 static inline int spi_nor_remove(struct spi_nor *nor)
641 {
642 return 0;
643 }
644 #else
645 /**
646 * spi_nor_remove() - perform cleanup before booting to the next stage
647 * @nor: the spi_nor structure
648 *
649 * Return: 0 for success, -errno for failure.
650 */
651 int spi_nor_remove(struct spi_nor *nor);
652 #endif
653
654 #endif
655