1config ARCH_LS1021A
2	bool
3	select FSL_DEVICE_DISABLE
4	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
5	select LS102XA_STREAM_ID
6	select SYS_FSL_DDR_BE if SYS_FSL_DDR
7	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
8	select SYS_FSL_IFC_BE
9	select SYS_FSL_ERRATUM_A008378
10	select SYS_FSL_ERRATUM_A008407
11	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
12	select SYS_FSL_ERRATUM_A008997 if USB
13	select SYS_FSL_ERRATUM_A009008 if USB
14	select SYS_FSL_ERRATUM_A009663
15	select SYS_FSL_ERRATUM_A009798 if USB
16	select SYS_FSL_ERRATUM_A009942
17	select SYS_FSL_ERRATUM_A010315
18	select SYS_FSL_ESDHC_BE
19	select SYS_FSL_HAS_CCI400
20	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
21	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
22	select SYS_FSL_HAS_SEC
23	select SYS_FSL_SEC_COMPAT_5
24	select SYS_FSL_SEC_LE
25	select SYS_FSL_SRDS_1
26	select SYS_HAS_SERDES
27	select SYS_I2C_MXC
28	imply CMD_PCI
29	imply SCSI
30	imply SCSI_AHCI
31
32menu "LS102xA architecture"
33	depends on ARCH_LS1021A
34
35config FSL_DEVICE_DISABLE
36	bool
37
38config LS1_DEEP_SLEEP
39	bool "Deep sleep"
40
41config LS102XA_STREAM_ID
42	bool
43
44config MAX_CPUS
45	int "Maximum number of CPUs permitted for LS102xA"
46	default 2
47	help
48	  Set this number to the maximum number of possible CPUs in the SoC.
49	  SoCs may have multiple clusters with each cluster may have multiple
50	  ports. If some ports are reserved but higher ports are used for
51	  cores, count the reserved ports. This will allocate enough memory
52	  in spin table to properly handle all cores.
53
54config PEN_ADDR_BIG_ENDIAN
55	bool
56
57config SYS_CCI400_OFFSET
58	hex "Offset for CCI400 base"
59	depends on SYS_FSL_HAS_CCI400
60	default 0x180000
61	help
62	  Offset for CCI400 base.
63	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
64
65config SYS_FSL_ERRATUM_A008850
66	bool
67	help
68	  Workaround for DDR erratum A008850
69
70config SYS_FSL_ERRATUM_A008997
71	bool
72	help
73	  Workaround for USB PHY erratum A008997
74
75config SYS_FSL_ERRATUM_A009007
76	bool
77	help
78	  Workaround for USB PHY erratum A009007
79
80config SYS_FSL_ERRATUM_A009008
81	bool
82	help
83	  Workaround for USB PHY erratum A009008
84
85config SYS_FSL_ERRATUM_A009798
86	bool
87	help
88	  Workaround for USB PHY erratum A009798
89
90config SYS_FSL_ERRATUM_A010315
91	bool "Workaround for PCIe erratum A010315"
92
93config SYS_FSL_HAS_CCI400
94	bool
95
96config SYS_FSL_ERRATUM_A008407
97	bool
98
99config SYS_FSL_QSPI_SKIP_CLKSEL
100	bool "Skip setting QSPI clock during SoC init"
101	default 0
102	help
103	   To improve startup times when booting from QSPI flash, the QSPI
104	   frequency can be set very early in the boot process. If this option
105	   is enabled, the QSPI frequency will not be changed by U-Boot during
106	   SoC initialization.
107
108endmenu
109