1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2003 Motorola Inc.
6 * Xianghua Xiao, (X.Xiao@motorola.com)
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 */
11
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <clock_legacy.h>
15 #include <ppc_asm.tmpl>
16 #include <asm/global_data.h>
17 #include <linux/compiler.h>
18 #include <asm/processor.h>
19 #include <asm/io.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 /* --------------------------------------------------------------- */
24
get_sys_info(sys_info_t * sys_info)25 void get_sys_info(sys_info_t *sys_info)
26 {
27 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
28 #ifdef CONFIG_FSL_CORENET
29 volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
30 unsigned int cpu;
31 #ifdef CONFIG_HETROGENOUS_CLUSTERS
32 unsigned int dsp_cpu;
33 uint rcw_tmp1, rcw_tmp2;
34 #endif
35 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
36 int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
37 #endif
38 __maybe_unused u32 svr;
39
40 const u8 core_cplx_PLL[16] = {
41 [ 0] = 0, /* CC1 PPL / 1 */
42 [ 1] = 0, /* CC1 PPL / 2 */
43 [ 2] = 0, /* CC1 PPL / 4 */
44 [ 4] = 1, /* CC2 PPL / 1 */
45 [ 5] = 1, /* CC2 PPL / 2 */
46 [ 6] = 1, /* CC2 PPL / 4 */
47 [ 8] = 2, /* CC3 PPL / 1 */
48 [ 9] = 2, /* CC3 PPL / 2 */
49 [10] = 2, /* CC3 PPL / 4 */
50 [12] = 3, /* CC4 PPL / 1 */
51 [13] = 3, /* CC4 PPL / 2 */
52 [14] = 3, /* CC4 PPL / 4 */
53 };
54
55 const u8 core_cplx_pll_div[16] = {
56 [ 0] = 1, /* CC1 PPL / 1 */
57 [ 1] = 2, /* CC1 PPL / 2 */
58 [ 2] = 4, /* CC1 PPL / 4 */
59 [ 4] = 1, /* CC2 PPL / 1 */
60 [ 5] = 2, /* CC2 PPL / 2 */
61 [ 6] = 4, /* CC2 PPL / 4 */
62 [ 8] = 1, /* CC3 PPL / 1 */
63 [ 9] = 2, /* CC3 PPL / 2 */
64 [10] = 4, /* CC3 PPL / 4 */
65 [12] = 1, /* CC4 PPL / 1 */
66 [13] = 2, /* CC4 PPL / 2 */
67 [14] = 4, /* CC4 PPL / 4 */
68 };
69 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
70 #if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
71 uint rcw_tmp;
72 #endif
73 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
74 unsigned long sysclk = get_board_sys_clk();
75 uint mem_pll_rat;
76
77 sys_info->freq_systembus = sysclk;
78 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
79 uint ddr_refclk_sel;
80 unsigned int porsr1_sys_clk;
81 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
82 & FSL_DCFG_PORSR1_SYSCLK_MASK;
83 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
84 sys_info->diff_sysclk = 1;
85 else
86 sys_info->diff_sysclk = 0;
87
88 /*
89 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
90 * are driven by separate DDR Refclock or single source
91 * differential clock.
92 */
93 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
94 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
95 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
96 /*
97 * For single source clocking, both ddrclock and sysclock
98 * are driven by differential sysclock.
99 */
100 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
101 sys_info->freq_ddrbus = get_board_sys_clk();
102 else
103 #endif
104 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
105 sys_info->freq_ddrbus = get_board_ddr_clk();
106 #else
107 sys_info->freq_ddrbus = sysclk;
108 #endif
109
110 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
111 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
112 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
113 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
114 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
115 if (mem_pll_rat == 0) {
116 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
117 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
118 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
119 }
120 #endif
121 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
122 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
123 * it uses 6.
124 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
125 */
126 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
127 svr = get_svr();
128 switch (SVR_SOC_VER(svr)) {
129 case SVR_T4240:
130 case SVR_T4160:
131 case SVR_T4120:
132 case SVR_T4080:
133 if (SVR_MAJ(svr) >= 2)
134 mem_pll_rat *= 2;
135 break;
136 case SVR_T2080:
137 case SVR_T2081:
138 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
139 mem_pll_rat *= 2;
140 break;
141 default:
142 break;
143 }
144 #endif
145 if (mem_pll_rat > 2)
146 sys_info->freq_ddrbus *= mem_pll_rat;
147 else
148 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
149
150 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
151 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
152 if (ratio[i] > 4)
153 freq_c_pll[i] = sysclk * ratio[i];
154 else
155 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
156 }
157
158 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
159 /*
160 * As per CHASSIS2 architeture total 12 clusters are posible and
161 * Each cluster has up to 4 cores, sharing the same PLL selection.
162 * The cluster clock assignment is SoC defined.
163 *
164 * Total 4 clock groups are possible with 3 PLLs each.
165 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
166 * clock group B has 3, 4, 6 and so on.
167 *
168 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
169 * depends upon the SoC architeture. Same applies to other
170 * clock groups and clusters.
171 *
172 */
173 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
174 int cluster = fsl_qoriq_core_to_cluster(cpu);
175 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
176 & 0xf;
177 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
178 cplx_pll += cc_group[cluster] - 1;
179 sys_info->freq_processor[cpu] =
180 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
181 }
182
183 #ifdef CONFIG_HETROGENOUS_CLUSTERS
184 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
185 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
186 u32 c_pll_sel = (in_be32
187 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
188 & 0xf;
189 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
190 cplx_pll += cc_group[dsp_cluster] - 1;
191 sys_info->freq_processor_dsp[dsp_cpu] =
192 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
193 }
194 #endif
195
196 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
197 defined(CONFIG_ARCH_T2080)
198 #define FM1_CLK_SEL 0xe0000000
199 #define FM1_CLK_SHIFT 29
200 #elif defined(CONFIG_ARCH_T1024)
201 #define FM1_CLK_SEL 0x00000007
202 #define FM1_CLK_SHIFT 0
203 #else
204 #define PME_CLK_SEL 0xe0000000
205 #define PME_CLK_SHIFT 29
206 #define FM1_CLK_SEL 0x1c000000
207 #define FM1_CLK_SHIFT 26
208 #endif
209 #if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
210 #if defined(CONFIG_ARCH_T1024)
211 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
212 #else
213 rcw_tmp = in_be32(&gur->rcwsr[7]);
214 #endif
215 #endif
216
217 #ifdef CONFIG_SYS_DPAA_PME
218 #ifndef CFG_PME_PLAT_CLK_DIV
219 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
220 case 1:
221 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
222 break;
223 case 2:
224 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2;
225 break;
226 case 3:
227 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3;
228 break;
229 case 4:
230 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4;
231 break;
232 case 6:
233 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2;
234 break;
235 case 7:
236 sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3;
237 break;
238 default:
239 printf("Error: Unknown PME clock select!\n");
240 case 0:
241 sys_info->freq_pme = sys_info->freq_systembus / 2;
242 break;
243
244 }
245 #else
246 sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
247
248 #endif
249 #endif
250
251 #ifdef CONFIG_SYS_DPAA_QBMAN
252 #ifndef CFG_QBMAN_CLK_DIV
253 #define CFG_QBMAN_CLK_DIV 2
254 #endif
255 sys_info->freq_qman = sys_info->freq_systembus / CFG_QBMAN_CLK_DIV;
256 #endif
257
258 #if defined(CONFIG_SYS_MAPLE)
259 #define CPRI_CLK_SEL 0x1C000000
260 #define CPRI_CLK_SHIFT 26
261 #define CPRI_ALT_CLK_SEL 0x00007000
262 #define CPRI_ALT_CLK_SHIFT 12
263
264 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
265 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
266 /* For MAPLE and CPRI frequency */
267 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
268 case 1:
269 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
270 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
271 break;
272 case 2:
273 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
274 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
275 break;
276 case 3:
277 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
278 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
279 break;
280 case 4:
281 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
282 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
283 break;
284 case 5:
285 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
286 >> CPRI_ALT_CLK_SHIFT) == 6) {
287 sys_info->freq_maple =
288 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
289 sys_info->freq_cpri =
290 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
291 }
292 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
293 >> CPRI_ALT_CLK_SHIFT) == 7) {
294 sys_info->freq_maple =
295 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
296 sys_info->freq_cpri =
297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
298 }
299 break;
300 case 6:
301 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
302 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
303 break;
304 case 7:
305 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
306 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
307 break;
308 default:
309 printf("Error: Unknown MAPLE/CPRI clock select!\n");
310 }
311
312 /* For MAPLE ULB and eTVPE frequencies */
313 #define ULB_CLK_SEL 0x00000038
314 #define ULB_CLK_SHIFT 3
315 #define ETVPE_CLK_SEL 0x00000007
316 #define ETVPE_CLK_SHIFT 0
317
318 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
319 case 1:
320 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
321 break;
322 case 2:
323 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
324 break;
325 case 3:
326 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
327 break;
328 case 4:
329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
330 break;
331 case 5:
332 sys_info->freq_maple_ulb = sys_info->freq_systembus;
333 break;
334 case 6:
335 sys_info->freq_maple_ulb =
336 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
337 break;
338 case 7:
339 sys_info->freq_maple_ulb =
340 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
341 break;
342 default:
343 printf("Error: Unknown MAPLE ULB clock select!\n");
344 }
345
346 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
347 case 1:
348 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
349 break;
350 case 2:
351 sys_info->freq_maple_etvpe =
352 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
353 break;
354 case 3:
355 sys_info->freq_maple_etvpe =
356 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
357 break;
358 case 4:
359 sys_info->freq_maple_etvpe =
360 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
361 break;
362 case 5:
363 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
364 break;
365 case 6:
366 sys_info->freq_maple_etvpe =
367 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
368 break;
369 case 7:
370 sys_info->freq_maple_etvpe =
371 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
372 break;
373 default:
374 printf("Error: Unknown MAPLE eTVPE clock select!\n");
375 }
376
377 #endif
378
379 #ifdef CONFIG_SYS_DPAA_FMAN
380 #ifndef CFG_FM_PLAT_CLK_DIV
381 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
382 case 1:
383 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
384 break;
385 case 2:
386 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2;
387 break;
388 case 3:
389 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3;
390 break;
391 case 4:
392 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4;
393 break;
394 case 5:
395 sys_info->freq_fman[0] = sys_info->freq_systembus;
396 break;
397 case 6:
398 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2;
399 break;
400 case 7:
401 sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3;
402 break;
403 default:
404 printf("Error: Unknown FMan1 clock select!\n");
405 case 0:
406 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
407 break;
408 }
409 #if (CFG_SYS_NUM_FMAN) == 2
410 #ifdef CFG_SYS_FM2_CLK
411 #define FM2_CLK_SEL 0x00000038
412 #define FM2_CLK_SHIFT 3
413 rcw_tmp = in_be32(&gur->rcwsr[15]);
414 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
415 case 1:
416 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1];
417 break;
418 case 2:
419 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2;
420 break;
421 case 3:
422 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3;
423 break;
424 case 4:
425 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4;
426 break;
427 case 5:
428 sys_info->freq_fman[1] = sys_info->freq_systembus;
429 break;
430 case 6:
431 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2;
432 break;
433 case 7:
434 sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3;
435 break;
436 default:
437 printf("Error: Unknown FMan2 clock select!\n");
438 case 0:
439 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
440 break;
441 }
442 #endif
443 #endif /* CFG_SYS_NUM_FMAN == 2 */
444 #else
445 sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK;
446 #endif
447 #endif
448
449 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
450
451 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
452 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
453 & 0xf;
454 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
455
456 sys_info->freq_processor[cpu] =
457 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
458 }
459 #define PME_CLK_SEL 0x80000000
460 #define FM1_CLK_SEL 0x40000000
461 #define FM2_CLK_SEL 0x20000000
462 #define HWA_ASYNC_DIV 0x04000000
463 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
464 #define HWA_CC_PLL 1
465 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
466 #define HWA_CC_PLL 2
467 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
468 #define HWA_CC_PLL 2
469 #else
470 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
471 #endif
472 rcw_tmp = in_be32(&gur->rcwsr[7]);
473
474 #ifdef CONFIG_SYS_DPAA_PME
475 if (rcw_tmp & PME_CLK_SEL) {
476 if (rcw_tmp & HWA_ASYNC_DIV)
477 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
478 else
479 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
480 } else {
481 sys_info->freq_pme = sys_info->freq_systembus / 2;
482 }
483 #endif
484
485 #ifdef CONFIG_SYS_DPAA_FMAN
486 if (rcw_tmp & FM1_CLK_SEL) {
487 if (rcw_tmp & HWA_ASYNC_DIV)
488 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
489 else
490 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
491 } else {
492 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
493 }
494 #if (CFG_SYS_NUM_FMAN) == 2
495 if (rcw_tmp & FM2_CLK_SEL) {
496 if (rcw_tmp & HWA_ASYNC_DIV)
497 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
498 else
499 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
500 } else {
501 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
502 }
503 #endif
504 #endif
505
506 #ifdef CONFIG_SYS_DPAA_QBMAN
507 sys_info->freq_qman = sys_info->freq_systembus / 2;
508 #endif
509
510 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
511
512 #ifdef CONFIG_U_QE
513 sys_info->freq_qe = sys_info->freq_systembus / 2;
514 #endif
515
516 #else /* CONFIG_FSL_CORENET */
517 uint plat_ratio, e500_ratio, half_freq_systembus;
518 int i;
519 #ifdef CONFIG_QE
520 __maybe_unused u32 qe_ratio;
521 #endif
522
523 plat_ratio = (gur->porpllsr) & 0x0000003e;
524 plat_ratio >>= 1;
525 sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
526
527 /* Divide before multiply to avoid integer
528 * overflow for processor speeds above 2GHz */
529 half_freq_systembus = sys_info->freq_systembus/2;
530 for (i = 0; i < cpu_numcores(); i++) {
531 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
532 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
533 }
534
535 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
536 sys_info->freq_ddrbus = sys_info->freq_systembus;
537
538 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
539 {
540 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
541 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
542 if (ddr_ratio != 0x7)
543 sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
544 }
545 #endif
546
547 #ifdef CONFIG_QE
548 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
549 sys_info->freq_qe = sys_info->freq_systembus;
550 #else
551 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
552 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
553 sys_info->freq_qe = qe_ratio * get_board_sys_clk();
554 #endif
555 #endif
556
557 #ifdef CONFIG_SYS_DPAA_FMAN
558 sys_info->freq_fman[0] = sys_info->freq_systembus;
559 #endif
560
561 #endif /* CONFIG_FSL_CORENET */
562
563 #if defined(CONFIG_FSL_LBC)
564 sys_info->freq_localbus = sys_info->freq_systembus /
565 CONFIG_SYS_FSL_LBC_CLK_DIV;
566 #endif
567
568 #if defined(CONFIG_FSL_IFC)
569 sys_info->freq_localbus = sys_info->freq_systembus /
570 CONFIG_SYS_FSL_IFC_CLK_DIV;
571 #endif
572 }
573
get_clocks(void)574 int get_clocks(void)
575 {
576 sys_info_t sys_info;
577 #ifdef CONFIG_ARCH_MPC8544
578 volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
579 #endif
580 get_sys_info (&sys_info);
581 gd->cpu_clk = sys_info.freq_processor[0];
582 gd->bus_clk = sys_info.freq_systembus;
583 gd->mem_clk = sys_info.freq_ddrbus;
584 gd->arch.lbc_clk = sys_info.freq_localbus;
585
586 #ifdef CONFIG_QE
587 gd->arch.qe_clk = sys_info.freq_qe;
588 gd->arch.brg_clk = gd->arch.qe_clk / 2;
589 #endif
590 /*
591 * The base clock for I2C depends on the actual SOC. Unfortunately,
592 * there is no pattern that can be used to determine the frequency, so
593 * the only choice is to look up the actual SOC number and use the value
594 * for that SOC. This information is taken from application note
595 * AN2919.
596 */
597 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
598 gd->arch.i2c1_clk = sys_info.freq_systembus;
599 #elif defined(CONFIG_ARCH_MPC8544)
600 /*
601 * On the 8544, the I2C clock is the same as the SEC clock. This can be
602 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
603 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
604 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
605 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
606 */
607 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
608 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
609 else
610 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
611 #else
612 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
613 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
614 #endif
615 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
616
617 #if defined(CONFIG_FSL_ESDHC)
618 #if defined(CONFIG_ARCH_P1010)
619 gd->arch.sdhc_clk = gd->bus_clk;
620 #else
621 gd->arch.sdhc_clk = gd->bus_clk / 2;
622 #endif
623 #endif /* defined(CONFIG_FSL_ESDHC) */
624
625 if(gd->cpu_clk != 0) return (0);
626 else return (1);
627 }
628
629
630 /********************************************
631 * get_bus_freq
632 * return system bus freq in Hz
633 *********************************************/
get_bus_freq(ulong dummy)634 ulong get_bus_freq(ulong dummy)
635 {
636 return gd->bus_clk;
637 }
638
639 /********************************************
640 * get_ddr_freq
641 * return ddr bus freq in Hz
642 *********************************************/
get_ddr_freq(ulong dummy)643 ulong get_ddr_freq (ulong dummy)
644 {
645 return gd->mem_clk;
646 }
647