1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 */ 5 6 /* Tegra clock control functions */ 7 8 #ifndef _TEGRA_CLOCK_H_ 9 #define _TEGRA_CLOCK_H_ 10 11 struct udevice; 12 13 /* Set of oscillator frequencies supported in the internal API. */ 14 enum clock_osc_freq { 15 /* All in MHz, so 13_0 is 13.0MHz */ 16 CLOCK_OSC_FREQ_13_0 = 0, 17 CLOCK_OSC_FREQ_16_8, 18 CLOCK_OSC_FREQ_19_2 = 4, 19 CLOCK_OSC_FREQ_38_4, 20 CLOCK_OSC_FREQ_12_0 = 8, 21 CLOCK_OSC_FREQ_48_0, 22 CLOCK_OSC_FREQ_26_0 = 12, 23 24 CLOCK_OSC_FREQ_COUNT, 25 }; 26 27 /* 28 * Note that no Tegra clock register actually uses all of bits 31:28 as 29 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 30 * those cases, nothing is stored in the bits about the mux field, so it's 31 * safe to pretend that the mux field extends all the way to the end of the 32 * register. As such, the U-Boot clock driver is currently a bit lazy, and 33 * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps 34 * them all together and pretends they're all 31:28. 35 */ 36 enum { 37 MASK_BITS_31_30, 38 MASK_BITS_31_29, 39 MASK_BITS_31_28, 40 }; 41 42 #include <asm/arch/clock-tables.h> 43 /* PLL stabilization delay in usec */ 44 #define CLOCK_PLL_STABLE_DELAY_US 300 45 46 /* return the current oscillator clock frequency */ 47 enum clock_osc_freq clock_get_osc_freq(void); 48 49 /* return the clk_m frequency */ 50 unsigned int clk_m_get_rate(unsigned int parent_rate); 51 52 /** 53 * Start PLL using the provided configuration parameters. 54 * 55 * @param id clock id 56 * @param divm input divider 57 * @param divn feedback divider 58 * @param divp post divider 2^n 59 * @param cpcon charge pump setup control 60 * @param lfcon loop filter setup control 61 * 62 * @returns monotonic time in us that the PLL will be stable 63 */ 64 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 65 u32 divp, u32 cpcon, u32 lfcon); 66 67 /** 68 * Set PLL output frequency 69 * 70 * @param clkid clock id 71 * @param pllout pll output id 72 * @param rate desired output rate 73 * 74 * Return: 0 if ok, -1 on error (invalid clock id or no suitable divider) 75 */ 76 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 77 unsigned rate); 78 79 /** 80 * Read low-level parameters of a PLL. 81 * 82 * @param id clock id to read (note: USB is not supported) 83 * @param divm returns input divider 84 * @param divn returns feedback divider 85 * @param divp returns post divider 2^n 86 * @param cpcon returns charge pump setup control 87 * @param lfcon returns loop filter setup control 88 * 89 * @returns 0 if ok, -1 on error (invalid clock id) 90 */ 91 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 92 u32 *divp, u32 *cpcon, u32 *lfcon); 93 94 /* 95 * Enable a clock 96 * 97 * @param id clock id 98 */ 99 void clock_enable(enum periph_id clkid); 100 101 /* 102 * Disable a clock 103 * 104 * @param id clock id 105 */ 106 void clock_disable(enum periph_id clkid); 107 108 /* 109 * Set whether a clock is enabled or disabled. 110 * 111 * @param id clock id 112 * @param enable 1 to enable, 0 to disable 113 */ 114 void clock_set_enable(enum periph_id clkid, int enable); 115 116 /** 117 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 118 * it out of reset and waits for th delay again. 119 * 120 * @param periph_id peripheral to reset 121 * @param us_delay time to delay in microseconds 122 */ 123 void reset_periph(enum periph_id periph_id, int us_delay); 124 125 /** 126 * Put a peripheral into or out of reset. 127 * 128 * @param periph_id peripheral to reset 129 * @param enable 1 to put into reset, 0 to take out of reset 130 */ 131 void reset_set_enable(enum periph_id periph_id, int enable); 132 133 134 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 135 enum crc_reset_id { 136 /* Things we can hold in reset for each CPU */ 137 crc_rst_cpu = 1, 138 crc_rst_de = 1 << 4, /* What is de? */ 139 crc_rst_watchdog = 1 << 8, 140 crc_rst_debug = 1 << 12, 141 }; 142 143 /** 144 * Put parts of the CPU complex into or out of reset.\ 145 * 146 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 147 * @param which which parts of the complex to affect (OR of crc_reset_id) 148 * @param reset 1 to assert reset, 0 to de-assert 149 */ 150 void reset_cmplx_set_enable(int cpu, int which, int reset); 151 152 /** 153 * Set the source for a peripheral clock. This plus the divisor sets the 154 * clock rate. You need to look up the datasheet to see the meaning of the 155 * source parameter as it changes for each peripheral. 156 * 157 * Warning: This function is only for use pre-relocation. Please use 158 * clock_start_periph_pll() instead. 159 * 160 * @param periph_id peripheral to adjust 161 * @param source source clock (0, 1, 2 or 3) 162 */ 163 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 164 165 /** 166 * This function is similar to clock_ll_set_source() except that it can be 167 * used for clocks with more than 2 mux bits. 168 * 169 * @param periph_id peripheral to adjust 170 * @param mux_bits number of mux bits for the clock 171 * @param source source clock (0-15 depending on mux_bits) 172 */ 173 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 174 unsigned source); 175 176 /** 177 * Set the source and divisor for a peripheral clock. This sets the 178 * clock rate. You need to look up the datasheet to see the meaning of the 179 * source parameter as it changes for each peripheral. 180 * 181 * Warning: This function is only for use pre-relocation. Please use 182 * clock_start_periph_pll() instead. 183 * 184 * @param periph_id peripheral to adjust 185 * @param source source clock (0, 1, 2 or 3) 186 * @param divisor divisor value to use 187 */ 188 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 189 unsigned divisor); 190 191 /** 192 * Returns the current parent clock ID of a given peripheral. This can be 193 * useful in order to call clock_*_periph_*() from generic code that has no 194 * specific knowledge of system-level clock tree structure. 195 * 196 * @param periph_id peripheral to query 197 * Return: clock ID of the peripheral's current parent clock 198 */ 199 enum clock_id clock_get_periph_parent(enum periph_id periph_id); 200 201 /** 202 * Start a peripheral PLL clock at the given rate. This also resets the 203 * peripheral. 204 * 205 * @param periph_id peripheral to start 206 * @param parent PLL id of required parent clock 207 * @param rate Required clock rate in Hz 208 * Return: rate selected in Hz, or -1U if something went wrong 209 */ 210 unsigned clock_start_periph_pll(enum periph_id periph_id, 211 enum clock_id parent, unsigned rate); 212 213 /** 214 * Returns the rate of a peripheral clock in Hz. Since the caller almost 215 * certainly knows the parent clock (having just set it) we require that 216 * this be passed in so we don't need to work it out. 217 * 218 * @param periph_id peripheral to start 219 * @param parent PLL id of parent clock (used to calculate rate, you 220 * must know this!) 221 * Return: clock rate of peripheral in Hz 222 */ 223 unsigned long clock_get_periph_rate(enum periph_id periph_id, 224 enum clock_id parent); 225 226 /** 227 * Adjust peripheral PLL clock to the given rate. This does not reset the 228 * peripheral. If a second stage divisor is not available, pass NULL for 229 * extra_div. If it is available, then this parameter will return the 230 * divisor selected (which will be a power of 2 from 1 to 256). 231 * 232 * @param periph_id peripheral to start 233 * @param parent PLL id of required parent clock 234 * @param rate Required clock rate in Hz 235 * @param extra_div value for the second-stage divisor (NULL if one is 236 not available) 237 * Return: rate selected in Hz, or -1U if something went wrong 238 */ 239 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 240 enum clock_id parent, unsigned rate, int *extra_div); 241 242 /** 243 * Returns the clock rate of a specified clock, in Hz. 244 * 245 * @param parent PLL id of clock to check 246 * Return: rate of clock in Hz 247 */ 248 unsigned clock_get_rate(enum clock_id clkid); 249 250 /** 251 * Start up a UART using low-level calls 252 * 253 * Prior to relocation clock_start_periph_pll() cannot be called. This 254 * function provides a way to set up a UART using low-level calls which 255 * do not require BSS. 256 * 257 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 258 */ 259 void clock_ll_start_uart(enum periph_id periph_id); 260 261 /** 262 * Decode a peripheral ID from a device tree node. 263 * 264 * This works by looking up the peripheral's 'clocks' node and reading out 265 * the second cell, which is the clock number / peripheral ID. 266 * 267 * @param blob FDT blob to use 268 * @param node Node to look at 269 * Return: peripheral ID, or PERIPH_ID_NONE if none 270 */ 271 int clock_decode_periph_id(struct udevice *dev); 272 273 /** 274 * Get periph clock id and its parent from device tree. 275 * 276 * This works by looking up the peripheral's 'clocks' node and reading out 277 * the second and fourth cells, which are the peripheral and PLL clock numbers. 278 * 279 * @param dev udevice associated with FDT node 280 * @param clk_id pointer to int array of 2 values 281 * first is periph clock, second is 282 * its PLL parent according to FDT. 283 */ 284 int clock_decode_pair(struct udevice *dev, int *clk_id); 285 286 /** 287 * Checks if the oscillator bypass is enabled (XOBP bit) 288 * 289 * Return: 1 if bypass is enabled, 0 if not 290 */ 291 int clock_get_osc_bypass(void); 292 293 /* 294 * Checks that clocks are valid and prints a warning if not 295 * 296 * Return: 0 if ok, -1 on error 297 */ 298 int clock_verify(void); 299 300 /* Initialize the clocks */ 301 void clock_init(void); 302 303 /* Initialize the PLLs */ 304 void clock_early_init(void); 305 306 /* @return true if hardware indicates that clock_early_init() was called */ 307 bool clock_early_init_done(void); 308 309 /* Returns a pointer to the clock source register for a peripheral */ 310 u32 *get_periph_source_reg(enum periph_id periph_id); 311 312 /* Returns a pointer to the given 'simple' PLL */ 313 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); 314 315 /* 316 * Given a peripheral ID, determine where the mux bits are in the peripheral 317 * clock's register, the number of divider bits the clock has, and the SoC- 318 * specific clock type. 319 * 320 * This is an internal API between the core Tegra clock code and the SoC- 321 * specific clock code. 322 * 323 * @param periph_id peripheral to query 324 * @param mux_bits Set to number of bits in mux register 325 * @param divider_bits Set to the relevant MASK_BITS_* value 326 * @param type Set to the SoC-specific clock type 327 * Return: 0 on success, -1 on error 328 */ 329 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 330 int *divider_bits, int *type); 331 332 /* 333 * Given a peripheral ID and clock source mux value, determine the clock_id 334 * of that peripheral's parent. 335 * 336 * This is an internal API between the core Tegra clock code and the SoC- 337 * specific clock code. 338 * 339 * @param periph_id peripheral to query 340 * @param source raw clock source mux value 341 * Return: the CLOCK_ID_* value @source represents 342 */ 343 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); 344 345 /** 346 * Given a peripheral ID and the required source clock, this returns which 347 * value should be programmed into the source mux for that peripheral. 348 * 349 * There is special code here to handle the one source type with 5 sources. 350 * 351 * @param periph_id peripheral to start 352 * @param source PLL id of required parent clock 353 * @param mux_bits Set to number of bits in mux register: 2 or 4 354 * @param divider_bits Set to number of divider bits (8 or 16) 355 * Return: mux value (0-4, or -1 if not found) 356 */ 357 int get_periph_clock_source(enum periph_id periph_id, 358 enum clock_id parent, int *mux_bits, int *divider_bits); 359 360 /* 361 * Convert a device tree clock ID to our peripheral ID. They are mostly 362 * the same but we are very cautious so we check that a valid clock ID is 363 * provided. 364 * 365 * @param clk_id Clock ID according to tegra30 device tree binding 366 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 367 */ 368 enum periph_id clk_id_to_periph_id(int clk_id); 369 370 /* 371 * Convert a device tree clock ID to our PLL ID. 372 * 373 * @param clk_id Clock ID according to tegra device tree binding 374 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid 375 */ 376 enum clock_id clk_id_to_pll_id(int clk_id); 377 378 /** 379 * Set the output frequency you want for each PLL clock. 380 * PLL output frequencies are programmed by setting their N, M and P values. 381 * The governing equations are: 382 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 383 * where Fo is the output frequency from the PLL. 384 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 385 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 386 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 387 * 388 * @param n PLL feedback divider(DIVN) 389 * @param m PLL input divider(DIVN) 390 * @param p post divider(DIVP) 391 * @param cpcon base PLL charge pump(CPCON) 392 * Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot 393 * be overridden), 1 if PLL is already correct 394 */ 395 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 396 397 /* return 1 if a peripheral ID is in range */ 398 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 399 (id) < CLOCK_TYPE_COUNT) 400 401 /* return 1 if a periphc_internal_id is in range */ 402 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 403 (id) < PERIPHC_COUNT) 404 405 /* SoC-specific TSC init */ 406 void arch_timer_init(void); 407 408 void tegra30_set_up_pllp(void); 409 410 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ 411 #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) 412 413 struct clk_pll_info { 414 u32 m_shift:5; /* DIVM_SHIFT */ 415 u32 n_shift:5; /* DIVN_SHIFT */ 416 u32 p_shift:5; /* DIVP_SHIFT */ 417 u32 kcp_shift:5; /* KCP/cpcon SHIFT */ 418 u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ 419 u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ 420 u32 rsvd:1; 421 u32 m_mask:10; /* DIVM_MASK */ 422 u32 n_mask:12; /* DIVN_MASK */ 423 u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ 424 u32 kcp_mask:10; /* KCP/CPCON MASK */ 425 u32 kvco_mask:10; /* KVCO/LFCON MASK */ 426 u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ 427 u32 rsvd2:6; 428 }; 429 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; 430 431 struct periph_clk_init { 432 enum periph_id periph_id; 433 enum clock_id parent_clock_id; 434 }; 435 extern struct periph_clk_init periph_clk_init_table[]; 436 437 /** 438 * Enable output clock for external peripherals 439 * 440 * @param clk_id Clock ID to output (1, 2 or 3) 441 * Return: 0 if OK. -ve on error 442 */ 443 int clock_external_output(int clk_id); 444 445 #endif /* _TEGRA_CLOCK_H_ */ 446