1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 7 #define __ASM_ARCH_LS102XA_IMMAP_H_ 8 #include <fsl_immap.h> 9 10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14 #define IS_SVR_REV(svr, maj, min) \ 15 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) 16 17 #define SOC_VER_SLS1020 0x00 18 #define SOC_VER_LS1020 0x10 19 #define SOC_VER_LS1021 0x11 20 #define SOC_VER_LS1022 0x12 21 22 #define SOC_MAJOR_VER_1_0 0x1 23 #define SOC_MAJOR_VER_2_0 0x2 24 25 #define CCSR_BRR_OFFSET 0xe4 26 #define CCSR_SCRATCHRW1_OFFSET 0x200 27 28 #define RCWSR0_SYS_PLL_RAT_SHIFT 25 29 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 30 #define RCWSR0_MEM_PLL_RAT_SHIFT 16 31 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 32 33 #define RCWSR4_SRDS1_PRTCL_SHIFT 24 34 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 35 36 #define TIMER_COMP_VAL 0xffffffffffffffffull 37 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 38 #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 39 40 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 41 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 42 43 #define DCFG_DCSR_PORCR1 0 44 45 #ifndef CFG_SYS_CCSRBAR 46 #define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR 47 #endif 48 49 #ifndef CFG_SYS_CCSRBAR_PHYS_HIGH 50 #ifdef CONFIG_PHYS_64BIT 51 #define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf 52 #else 53 #define CFG_SYS_CCSRBAR_PHYS_HIGH 0 54 #endif 55 #endif 56 57 #ifndef CFG_SYS_CCSRBAR_PHYS_LOW 58 #define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR 59 #endif 60 61 #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 62 CFG_SYS_CCSRBAR_PHYS_LOW) 63 64 struct sys_info { 65 unsigned long freq_processor[CONFIG_MAX_CPUS]; 66 unsigned long freq_systembus; 67 unsigned long freq_ddrbus; 68 unsigned long freq_localbus; 69 }; 70 71 #define CCSR_DEVDISR1_QE 0x00000001 72 73 /* Device Configuration and Pin Control */ 74 struct ccsr_gur { 75 u32 porsr1; /* POR status 1 */ 76 u32 porsr2; /* POR status 2 */ 77 u8 res_008[0x20-0x8]; 78 u32 gpporcr1; /* General-purpose POR configuration */ 79 u32 gpporcr2; 80 u32 dcfg_fusesr; /* Fuse status register */ 81 u8 res_02c[0x70-0x2c]; 82 u32 devdisr; /* Device disable control */ 83 u32 devdisr2; /* Device disable control 2 */ 84 u32 devdisr3; /* Device disable control 3 */ 85 u32 devdisr4; /* Device disable control 4 */ 86 u32 devdisr5; /* Device disable control 5 */ 87 u8 res_084[0x94-0x84]; 88 u32 coredisru; /* uppper portion for support of 64 cores */ 89 u32 coredisrl; /* lower portion for support of 64 cores */ 90 u8 res_09c[0xa4-0x9c]; 91 u32 svr; /* System version */ 92 u8 res_0a8[0xb0-0xa8]; 93 u32 rstcr; /* Reset control */ 94 u32 rstrqpblsr; /* Reset request preboot loader status */ 95 u8 res_0b8[0xc0-0xb8]; 96 u32 rstrqmr1; /* Reset request mask */ 97 u8 res_0c4[0xc8-0xc4]; 98 u32 rstrqsr1; /* Reset request status */ 99 u8 res_0cc[0xd4-0xcc]; 100 u32 rstrqwdtmrl; /* Reset request WDT mask */ 101 u8 res_0d8[0xdc-0xd8]; 102 u32 rstrqwdtsrl; /* Reset request WDT status */ 103 u8 res_0e0[0xe4-0xe0]; 104 u32 brrl; /* Boot release */ 105 u8 res_0e8[0x100-0xe8]; 106 u32 rcwsr[16]; /* Reset control word status */ 107 #define RCW_SB_EN_REG_INDEX 7 108 #define RCW_SB_EN_MASK 0x00200000 109 u8 res_140[0x200-0x140]; 110 u32 scratchrw[4]; /* Scratch Read/Write */ 111 u8 res_210[0x300-0x210]; 112 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 113 u8 res_310[0x400-0x310]; 114 u32 crstsr; 115 u8 res_404[0x550-0x404]; 116 u32 sataliodnr; 117 u8 res_554[0x604-0x554]; 118 u32 pamubypenr; 119 u32 dmacr1; 120 u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 121 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 122 struct { 123 u32 upper; 124 u32 lower; 125 } tp_cluster[1]; /* Core Cluster n Topology Register */ 126 u8 res_848[0xe60-0x848]; 127 u32 ddrclkdr; 128 u8 res_e60[0xe68-0xe64]; 129 u32 ifcclkdr; 130 u8 res_e68[0xe80-0xe6c]; 131 u32 sdhcpcr; 132 }; 133 134 #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 135 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 136 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 137 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 138 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 139 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 140 #define SCFG_QSPI_CLKSEL 0x50100000 141 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 142 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 143 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 144 #define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 145 #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 146 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 147 #define SCFG_ENDIANCR_LE 0x80000000 148 #define SCFG_DPSLPCR_WDRR_EN 0x00000001 149 #define SCFG_PMCINTECR_LPUART 0x40000000 150 #define SCFG_PMCINTECR_FTM 0x20000000 151 #define SCFG_PMCINTECR_GPIO 0x10000000 152 #define SCFG_PMCINTECR_IRQ0 0x08000000 153 #define SCFG_PMCINTECR_IRQ1 0x04000000 154 #define SCFG_PMCINTECR_ETSECRXG0 0x00800000 155 #define SCFG_PMCINTECR_ETSECRXG1 0x00400000 156 #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 157 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 158 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 159 160 #define SCFG_BASE 0x01570000 161 #define SCFG_USB3PRM1CR 0x070 162 #define SCFG_USB_TXVREFTUNE 0x9 163 #define SCFG_USB_SQRXTUNE_MASK 0x7 164 #define SCFG_USB3PRM2CR 0x074 165 #define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 166 #define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 167 168 #define USB_PHY_BASE 0x08510000 169 #define USB_PHY_RX_OVRD_IN_HI 0x200c 170 #define USB_PHY_RX_EQ_VAL_1 0x0000 171 #define USB_PHY_RX_EQ_VAL_2 0x8000 172 #define USB_PHY_RX_EQ_VAL_3 0x8004 173 #define USB_PHY_RX_EQ_VAL_4 0x800C 174 175 /* Supplemental Configuration Unit */ 176 struct ccsr_scfg { 177 u32 dpslpcr; 178 u32 resv0[2]; 179 u32 etsecclkdpslpcr; 180 u32 resv1[5]; 181 u32 fuseovrdcr; 182 u32 pixclkcr; 183 u32 resv2[5]; 184 u32 spimsicr; 185 u32 resv3[6]; 186 u32 pex1pmwrcr; 187 u32 pex1pmrdsr; 188 u32 resv4[3]; 189 u32 usb3prm1cr; 190 u32 usb4prm2cr; 191 u32 pex1rdmsgpldlsbsr; 192 u32 pex1rdmsgpldmsbsr; 193 u32 pex2rdmsgpldlsbsr; 194 u32 pex2rdmsgpldmsbsr; 195 u32 pex1rdmmsgrqsr; 196 u32 pex2rdmmsgrqsr; 197 u32 spimsiclrcr; 198 u32 pexmscportsr[2]; 199 u32 pex2pmwrcr; 200 u32 resv5[24]; 201 u32 mac1_streamid; 202 u32 mac2_streamid; 203 u32 mac3_streamid; 204 u32 pex1_streamid; 205 u32 pex2_streamid; 206 u32 dma_streamid; 207 u32 sata_streamid; 208 u32 usb3_streamid; 209 u32 qe_streamid; 210 u32 sdhc_streamid; 211 u32 adma_streamid; 212 u32 letechsftrstcr; 213 u32 core0_sft_rst; 214 u32 core1_sft_rst; 215 u32 resv6[1]; 216 u32 usb_hi_addr; 217 u32 etsecclkadjcr; 218 u32 sai_clk; 219 u32 resv7[1]; 220 u32 dcu_streamid; 221 u32 usb2_streamid; 222 u32 ftm_reset; 223 u32 altcbar; 224 u32 qspi_cfg; 225 u32 pmcintecr; 226 u32 pmcintlecr; 227 u32 pmcintsr; 228 u32 qos1; 229 u32 qos2; 230 u32 qos3; 231 u32 cci_cfg; 232 u32 endiancr; 233 u32 etsecdmamcr; 234 u32 usb3prm3cr; 235 u32 resv9[1]; 236 u32 debug_streamid; 237 u32 resv10[5]; 238 u32 snpcnfgcr; 239 u32 hrstcr; 240 u32 intpcr; 241 u32 resv12[20]; 242 u32 scfgrevcr; 243 u32 coresrencr; 244 u32 pex2pmrdsr; 245 u32 eddrtqcfg; 246 u32 ddrc2cr; 247 u32 ddrc3cr; 248 u32 ddrc4cr; 249 u32 ddrgcr; 250 u32 resv13[120]; 251 u32 qeioclkcr; 252 u32 etsecmcr; 253 u32 sdhciovserlcr; 254 u32 resv14[61]; 255 u32 sparecr[8]; 256 u32 resv15[248]; 257 u32 core0sftrstsr; 258 u32 clusterpmcr; 259 }; 260 261 /* Clocking */ 262 struct ccsr_clk { 263 struct { 264 u32 clkcncsr; /* core cluster n clock control status */ 265 u8 res_004[0x1c]; 266 } clkcsr[2]; 267 u8 res_040[0x7c0]; /* 0x100 */ 268 struct { 269 u32 pllcngsr; 270 u8 res_804[0x1c]; 271 } pllcgsr[2]; 272 u8 res_840[0x1c0]; 273 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 274 u8 res_a04[0x1fc]; 275 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 276 u8 res_c04[0x1c]; 277 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 278 u8 res_c24[0x3dc]; 279 }; 280 281 /* System Counter */ 282 struct sctr_regs { 283 u32 cntcr; 284 u32 cntsr; 285 u32 cntcv1; 286 u32 cntcv2; 287 u32 resv1[4]; 288 u32 cntfid0; 289 u32 cntfid1; 290 u32 resv2[1002]; 291 u32 counterid[12]; 292 }; 293 294 #define MAX_SERDES 1 295 #define SRDS_MAX_LANES 4 296 #define SRDS_MAX_BANK 2 297 298 #define SRDS_RSTCTL_RST 0x80000000 299 #define SRDS_RSTCTL_RSTDONE 0x40000000 300 #define SRDS_RSTCTL_RSTERR 0x20000000 301 #define SRDS_RSTCTL_SWRST 0x10000000 302 #define SRDS_RSTCTL_SDEN 0x00000020 303 #define SRDS_RSTCTL_SDRST_B 0x00000040 304 #define SRDS_RSTCTL_PLLRST_B 0x00000080 305 #define SRDS_PLLCR0_POFF 0x80000000 306 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 307 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 308 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 309 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 310 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 311 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 312 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 313 #define SRDS_PLLCR0_PLL_LCK 0x00800000 314 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 315 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 316 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 317 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 318 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 319 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 320 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 321 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 322 323 struct ccsr_serdes { 324 struct { 325 u32 rstctl; /* Reset Control Register */ 326 327 u32 pllcr0; /* PLL Control Register 0 */ 328 329 u32 pllcr1; /* PLL Control Register 1 */ 330 u32 res_0c; /* 0x00c */ 331 u32 pllcr3; 332 u32 pllcr4; 333 u8 res_18[0x20-0x18]; 334 } bank[2]; 335 u8 res_40[0x90-0x40]; 336 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 337 u8 res_94[0xa0-0x94]; 338 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 339 u8 res_a4[0xb0-0xa4]; 340 u32 srdsgr0; /* 0xb0 General Register 0 */ 341 u8 res_b4[0xe0-0xb4]; 342 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 343 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 344 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 345 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 346 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 347 u8 res_f4[0x100-0xf4]; 348 struct { 349 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 350 u8 res_104[0x120-0x104]; 351 } srdslnpssr[4]; 352 u8 res_180[0x300-0x180]; 353 u32 srdspexeqcr; 354 u32 srdspexeqpcr[11]; 355 u8 res_330[0x400-0x330]; 356 u32 srdspexapcr; 357 u8 res_404[0x440-0x404]; 358 u32 srdspexbpcr; 359 u8 res_444[0x800-0x444]; 360 struct { 361 u32 gcr0; /* 0x800 General Control Register 0 */ 362 u32 gcr1; /* 0x804 General Control Register 1 */ 363 u32 gcr2; /* 0x808 General Control Register 2 */ 364 u32 sscr0; 365 u32 recr0; /* 0x810 Receive Equalization Control */ 366 u32 recr1; 367 u32 tecr0; /* 0x818 Transmit Equalization Control */ 368 u32 sscr1; 369 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 370 u8 res_824[0x83c-0x824]; 371 u32 tcsr3; 372 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 373 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 374 }; 375 376 #define RCPM_POWMGTCSR 0x130 377 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 378 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 379 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 380 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 381 #define RCPM_IPPDEXPCR0 0x140 382 #define RCPM_IPPDEXPCR0_ETSEC 0x80000000 383 #define RCPM_IPPDEXPCR0_GPIO 0x00000040 384 #define RCPM_IPPDEXPCR1 0x144 385 #define RCPM_IPPDEXPCR1_LPUART 0x40000000 386 #define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 387 #define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 388 #define RCPM_NFIQOUTR 0x15c 389 #define RCPM_NIRQOUTR 0x16c 390 #define RCPM_DSIMSKR 0x18c 391 #define RCPM_CLPCL10SETR 0x1c4 392 #define RCPM_CLPCL10SETR_C0 0x00000001 393 394 struct ccsr_rcpm { 395 u8 rev1[0x4c]; 396 u32 twaitsr; 397 u8 rev2[0xe0]; 398 u32 powmgtcsr; 399 u8 rev3[0xc]; 400 u32 ippdexpcr0; 401 u32 ippdexpcr1; 402 u8 rev4[0x14]; 403 u32 nfiqoutr; 404 u8 rev5[0xc]; 405 u32 nirqoutr; 406 u8 rev6[0x1c]; 407 u32 dsimskr; 408 u8 rev7[0x34]; 409 u32 clpcl10setr; 410 }; 411 412 uint get_svr(void); 413 414 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 415