1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 7 #define __ARCH_FSL_LSCH2_IMMAP_H__ 8 9 #include <fsl_immap.h> 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define CFG_SYS_DCSRBAR 0x20000000 15 #define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000) 16 17 #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18 #define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 20 #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 21 #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22 #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 23 #define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 24 #define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25 #define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 26 #define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 27 #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 28 #define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 29 #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 30 #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 31 #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 32 #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 33 #define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 34 #define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 35 #define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 36 #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 37 #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 38 #define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 39 #define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 40 41 #define CFG_SYS_BMAN_NUM_PORTALS 10 42 #define CFG_SYS_BMAN_MEM_BASE 0x508000000 43 #define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 44 CFG_SYS_BMAN_MEM_BASE) 45 #define CFG_SYS_BMAN_MEM_SIZE 0x08000000 46 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000 47 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000 48 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 49 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 50 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 51 CFG_SYS_BMAN_CENA_SIZE) 52 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 53 #define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80 54 #define CFG_SYS_QMAN_NUM_PORTALS 10 55 #define CFG_SYS_QMAN_MEM_BASE 0x500000000 56 #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE 57 #define CFG_SYS_QMAN_MEM_SIZE 0x08000000 58 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000 59 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 60 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 61 CFG_SYS_QMAN_CENA_SIZE) 62 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 63 #define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680 64 65 #define CFG_SYS_FSL_TIMER_ADDR 0x02b00000 66 67 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 68 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 69 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 70 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 71 72 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 73 74 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 75 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 76 77 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 78 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 79 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 80 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 81 82 #define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) 83 84 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 85 86 #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) 87 88 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 89 90 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) 91 #define QMAN_CQSIDR_REG 0x20a80 92 93 #define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 94 #define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 95 #define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 96 /* LUT registers */ 97 #ifdef CONFIG_ARCH_LS1012A 98 #define PCIE_LUT_BASE 0xC0000 99 #else 100 #define PCIE_LUT_BASE 0x10000 101 #endif 102 #define PCIE_LUT_LCTRL0 0x7F8 103 #define PCIE_LUT_DBG 0x7FC 104 105 /* TZ Address Space Controller Definitions */ 106 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 107 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 108 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 109 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 110 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 111 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 112 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 113 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 114 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 115 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 116 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 117 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 118 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 119 120 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 121 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 122 #define TP_ITYP_TYPE_ARM 0x0 123 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 124 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 125 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 126 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 127 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 128 #define TY_ITYP_VER_A7 0x1 129 #define TY_ITYP_VER_A53 0x2 130 #define TY_ITYP_VER_A57 0x3 131 #define TY_ITYP_VER_A72 0x4 132 133 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 134 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 135 #define TP_INIT_PER_CLUSTER 4 136 137 #ifndef CFG_SYS_CCSRBAR 138 #define CFG_SYS_CCSRBAR 0x01000000 139 #endif 140 141 #ifndef CFG_SYS_CCSRBAR_PHYS_HIGH 142 #define CFG_SYS_CCSRBAR_PHYS_HIGH 0 143 #endif 144 145 #ifndef CFG_SYS_CCSRBAR_PHYS_LOW 146 #define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000 147 #endif 148 149 #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 150 CFG_SYS_CCSRBAR_PHYS_LOW) 151 152 struct sys_info { 153 unsigned long freq_processor[CONFIG_MAX_CPUS]; 154 /* frequency of platform PLL */ 155 unsigned long freq_systembus; 156 unsigned long freq_ddrbus; 157 unsigned long freq_localbus; 158 unsigned long freq_cga_m2; 159 #ifdef CONFIG_SYS_DPAA_FMAN 160 unsigned long freq_fman[CFG_SYS_NUM_FMAN]; 161 #endif 162 unsigned long freq_qman; 163 }; 164 165 #define CFG_SYS_FSL_FM1_OFFSET 0xa00000 166 167 #define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 168 #define CFG_SYS_FSL_FM1_ADDR \ 169 (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET) 170 #define CFG_SYS_FSL_FM1_DTSEC1_ADDR \ 171 (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET) 172 173 #define CFG_SYS_FSL_SEC_OFFSET 0x700000ull 174 #define CFG_SYS_FSL_JR0_OFFSET 0x710000ull 175 #define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET 176 #define FSL_SEC_JR1_OFFSET 0x720000ull 177 #define FSL_SEC_JR2_OFFSET 0x730000ull 178 #define FSL_SEC_JR3_OFFSET 0x740000ull 179 #define CFG_SYS_FSL_SEC_ADDR \ 180 (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) 181 #define CFG_SYS_FSL_JR0_ADDR \ 182 (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) 183 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) 184 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) 185 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) 186 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) 187 188 /* Device Configuration and Pin Control */ 189 #define DCFG_DCSR_PORCR1 0x0 190 #define DCFG_DCSR_ECCCR2 0x524 191 #define DISABLE_PFE_ECC BIT(13) 192 193 struct ccsr_gur { 194 u32 porsr1; /* POR status 1 */ 195 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 196 u32 porsr2; /* POR status 2 */ 197 u8 res_008[0x20-0x8]; 198 u32 gpporcr1; /* General-purpose POR configuration */ 199 u32 gpporcr2; 200 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 201 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 202 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 203 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 204 u32 dcfg_fusesr; /* Fuse status register */ 205 u8 res_02c[0x70-0x2c]; 206 u32 devdisr; /* Device disable control */ 207 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 208 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 209 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 210 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 211 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 212 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 213 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 214 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 215 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 216 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 217 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 218 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 219 u32 devdisr2; /* Device disable control 2 */ 220 u32 devdisr3; /* Device disable control 3 */ 221 u32 devdisr4; /* Device disable control 4 */ 222 u32 devdisr5; /* Device disable control 5 */ 223 u32 devdisr6; /* Device disable control 6 */ 224 u32 devdisr7; /* Device disable control 7 */ 225 u8 res_08c[0x94-0x8c]; 226 u32 coredisru; /* uppper portion for support of 64 cores */ 227 u32 coredisrl; /* lower portion for support of 64 cores */ 228 u8 res_09c[0xa0-0x9c]; 229 u32 pvr; /* Processor version */ 230 u32 svr; /* System version */ 231 u32 mvr; /* Manufacturing version */ 232 u8 res_0ac[0xb0-0xac]; 233 u32 rstcr; /* Reset control */ 234 u32 rstrqpblsr; /* Reset request preboot loader status */ 235 u8 res_0b8[0xc0-0xb8]; 236 u32 rstrqmr1; /* Reset request mask */ 237 u8 res_0c4[0xc8-0xc4]; 238 u32 rstrqsr1; /* Reset request status */ 239 u8 res_0cc[0xd4-0xcc]; 240 u32 rstrqwdtmrl; /* Reset request WDT mask */ 241 u8 res_0d8[0xdc-0xd8]; 242 u32 rstrqwdtsrl; /* Reset request WDT status */ 243 u8 res_0e0[0xe4-0xe0]; 244 u32 brrl; /* Boot release */ 245 u8 res_0e8[0x100-0xe8]; 246 u32 rcwsr[16]; /* Reset control word status */ 247 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 248 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 249 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 250 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 251 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 252 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 253 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 254 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 255 #define RCW_SB_EN_REG_INDEX 7 256 #define RCW_SB_EN_MASK 0x00200000 257 258 u8 res_140[0x200-0x140]; 259 u32 scratchrw[4]; /* Scratch Read/Write */ 260 u8 res_210[0x300-0x210]; 261 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 262 u8 res_310[0x400-0x310]; 263 u32 crstsr[12]; 264 u8 res_430[0x500-0x430]; 265 266 /* PCI Express n Logical I/O Device Number register */ 267 u32 dcfg_ccsr_pex1liodnr; 268 u32 dcfg_ccsr_pex2liodnr; 269 u32 dcfg_ccsr_pex3liodnr; 270 u32 dcfg_ccsr_pex4liodnr; 271 /* RIO n Logical I/O Device Number register */ 272 u32 dcfg_ccsr_rio1liodnr; 273 u32 dcfg_ccsr_rio2liodnr; 274 u32 dcfg_ccsr_rio3liodnr; 275 u32 dcfg_ccsr_rio4liodnr; 276 /* USB Logical I/O Device Number register */ 277 u32 dcfg_ccsr_usb1liodnr; 278 u32 dcfg_ccsr_usb2liodnr; 279 u32 dcfg_ccsr_usb3liodnr; 280 u32 dcfg_ccsr_usb4liodnr; 281 /* SD/MMC Logical I/O Device Number register */ 282 u32 dcfg_ccsr_sdmmc1liodnr; 283 u32 dcfg_ccsr_sdmmc2liodnr; 284 u32 dcfg_ccsr_sdmmc3liodnr; 285 u32 dcfg_ccsr_sdmmc4liodnr; 286 /* RIO Message Unit Logical I/O Device Number register */ 287 u32 dcfg_ccsr_riomaintliodnr; 288 289 u8 res_544[0x550-0x544]; 290 u32 sataliodnr[4]; 291 u8 res_560[0x570-0x560]; 292 293 u32 dcfg_ccsr_misc1liodnr; 294 u32 dcfg_ccsr_misc2liodnr; 295 u32 dcfg_ccsr_misc3liodnr; 296 u32 dcfg_ccsr_misc4liodnr; 297 u32 dcfg_ccsr_dma1liodnr; 298 u32 dcfg_ccsr_dma2liodnr; 299 u32 dcfg_ccsr_dma3liodnr; 300 u32 dcfg_ccsr_dma4liodnr; 301 u32 dcfg_ccsr_spare1liodnr; 302 u32 dcfg_ccsr_spare2liodnr; 303 u32 dcfg_ccsr_spare3liodnr; 304 u32 dcfg_ccsr_spare4liodnr; 305 u8 res_5a0[0x600-0x5a0]; 306 u32 dcfg_ccsr_pblsr; 307 308 u32 pamubypenr; 309 u32 dmacr1; 310 311 u8 res_60c[0x610-0x60c]; 312 u32 dcfg_ccsr_gensr1; 313 u32 dcfg_ccsr_gensr2; 314 u32 dcfg_ccsr_gensr3; 315 u32 dcfg_ccsr_gensr4; 316 u32 dcfg_ccsr_gencr1; 317 u32 dcfg_ccsr_gencr2; 318 u32 dcfg_ccsr_gencr3; 319 u32 dcfg_ccsr_gencr4; 320 u32 dcfg_ccsr_gencr5; 321 u32 dcfg_ccsr_gencr6; 322 u32 dcfg_ccsr_gencr7; 323 u8 res_63c[0x658-0x63c]; 324 u32 dcfg_ccsr_cgensr1; 325 u32 dcfg_ccsr_cgensr0; 326 u8 res_660[0x678-0x660]; 327 u32 dcfg_ccsr_cgencr1; 328 329 u32 dcfg_ccsr_cgencr0; 330 u8 res_680[0x700-0x680]; 331 u32 dcfg_ccsr_sriopstecr; 332 u32 dcfg_ccsr_dcsrcr; 333 334 u8 res_708[0x740-0x708]; /* add more registers when needed */ 335 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 336 struct { 337 u32 upper; 338 u32 lower; 339 } tp_cluster[16]; 340 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 341 u32 dcfg_ccsr_qmbm_warmrst; 342 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 343 u32 dcfg_ccsr_reserved0; 344 u32 dcfg_ccsr_reserved1; 345 }; 346 347 #define SCFG_QSPI_CLKSEL 0x40100000 348 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 349 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 350 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 351 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 352 #define SCFG_USBPWRFAULT_SHARED 0x00000001 353 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 354 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 355 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 356 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 357 358 #define SCFG_BASE 0x01570000 359 #define SCFG_USB3PRM1CR_USB1 0x070 360 #define SCFG_USB3PRM2CR_USB1 0x074 361 #define SCFG_USB3PRM1CR_USB2 0x07C 362 #define SCFG_USB3PRM2CR_USB2 0x080 363 #define SCFG_USB3PRM1CR_USB3 0x088 364 #define SCFG_USB3PRM2CR_USB3 0x08c 365 #define SCFG_USB_TXVREFTUNE 0x9 366 #define SCFG_USB_SQRXTUNE_MASK 0x7 367 #define SCFG_USB_PCSTXSWINGFULL 0x47 368 #define SCFG_USB_PHY1 0x084F0000 369 #define SCFG_USB_PHY2 0x08500000 370 #define SCFG_USB_PHY3 0x08510000 371 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 372 #define USB_PHY_RX_EQ_VAL_1 0x0000 373 #define USB_PHY_RX_EQ_VAL_2 0x0080 374 #define USB_PHY_RX_EQ_VAL_3 0x0380 375 #define USB_PHY_RX_EQ_VAL_4 0x0b80 376 377 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 378 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 379 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 380 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 381 #define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 382 #define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 383 #define SCFG_SNPCNFGCR_EDMASNP 0x00020000 384 #define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 385 #define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 386 #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 387 #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 388 389 /* RGMIIPCR bit definitions*/ 390 #define SCFG_RGMIIPCR_EN_AUTO BIT(3) 391 #define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 392 #define SCFG_RGMIIPCR_SETSP_100M 0 393 #define SCFG_RGMIIPCR_SETSP_10M BIT(1) 394 #define SCFG_RGMIIPCR_SETFD BIT(0) 395 396 /* PFEASBCR bit definitions */ 397 #define SCFG_PFEASBCR_ARCACHE0 BIT(31) 398 #define SCFG_PFEASBCR_AWCACHE0 BIT(30) 399 #define SCFG_PFEASBCR_ARCACHE1 BIT(29) 400 #define SCFG_PFEASBCR_AWCACHE1 BIT(28) 401 #define SCFG_PFEASBCR_ARSNP BIT(27) 402 #define SCFG_PFEASBCR_AWSNP BIT(26) 403 404 /* WR_QoS1 PFE bit definitions */ 405 #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 406 #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 407 408 /* RD_QoS1 PFE bit definitions */ 409 #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 410 #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 411 412 /* Supplemental Configuration Unit */ 413 struct ccsr_scfg { 414 u8 res_000[0x100-0x000]; 415 u32 usb2_icid; 416 u32 usb3_icid; 417 u8 res_108[0x114-0x108]; 418 u32 dma_icid; 419 u32 sata_icid; 420 u32 usb1_icid; 421 u32 qe_icid; 422 u32 sdhc_icid; 423 u32 edma_icid; 424 u32 etr_icid; 425 u32 core_sft_rst[4]; 426 u8 res_140[0x158-0x140]; 427 u32 altcbar; 428 u32 qspi_cfg; 429 u8 res_160[0x164 - 0x160]; 430 u32 wr_qos1; 431 u32 wr_qos2; 432 u32 rd_qos1; 433 u32 rd_qos2; 434 u8 res_174[0x180 - 0x174]; 435 u32 dmamcr; 436 u8 res_184[0x188-0x184]; 437 u32 gic_align; 438 u32 debug_icid; 439 u8 res_190[0x1a4-0x190]; 440 u32 snpcnfgcr; 441 u8 res_1a8[0x1ac-0x1a8]; 442 u32 intpcr; 443 u8 res_1b0[0x204-0x1b0]; 444 u32 coresrencr; 445 u8 res_208[0x220-0x208]; 446 u32 rvbar0_0; 447 u32 rvbar0_1; 448 u32 rvbar1_0; 449 u32 rvbar1_1; 450 u32 rvbar2_0; 451 u32 rvbar2_1; 452 u32 rvbar3_0; 453 u32 rvbar3_1; 454 u32 lpmcsr; 455 u8 res_244[0x400-0x244]; 456 u32 qspidqscr; 457 u32 ecgtxcmcr; 458 u32 sdhciovselcr; 459 u32 rcwpmuxcr0; 460 u32 usbdrvvbus_selcr; 461 u32 usbpwrfault_selcr; 462 u32 usb_refclk_selcr1; 463 u32 usb_refclk_selcr2; 464 u32 usb_refclk_selcr3; 465 u8 res_424[0x434 - 0x424]; 466 u32 rgmiipcr; 467 u32 res_438; 468 u32 rgmiipsr; 469 u32 pfepfcssr1; 470 u32 pfeintencr1; 471 u32 pfepfcssr2; 472 u32 pfeintencr2; 473 u32 pfeerrcr; 474 u32 pfeeerrintencr; 475 u32 pfeasbcr; 476 u32 pfebsbcr; 477 u8 res_460[0x484 - 0x460]; 478 u32 mdioselcr; 479 u8 res_468[0x600 - 0x488]; 480 u32 scratchrw[4]; 481 u8 res_610[0x680-0x610]; 482 u32 corebcr; 483 u8 res_684[0x1000-0x684]; 484 u32 pex1msiir; 485 u32 pex1msir; 486 u8 res_1008[0x2000-0x1008]; 487 u32 pex2; 488 u32 pex2msir; 489 u8 res_2008[0x3000-0x2008]; 490 u32 pex3msiir; 491 u32 pex3msir; 492 }; 493 494 /* Clocking */ 495 struct ccsr_clk { 496 struct { 497 u32 clkcncsr; /* core cluster n clock control status */ 498 u8 res_004[0x0c]; 499 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 500 u8 res_014[0x0c]; 501 } clkcsr[4]; 502 u8 res_040[0x780]; /* 0x100 */ 503 struct { 504 u32 pllcngsr; 505 u8 res_804[0x1c]; 506 } pllcgsr[2]; 507 u8 res_840[0x1c0]; 508 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 509 u8 res_a04[0x1fc]; 510 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 511 u8 res_c04[0x1c]; 512 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 513 u8 res_c24[0x3dc]; 514 }; 515 516 /* System Counter */ 517 struct sctr_regs { 518 u32 cntcr; 519 u32 cntsr; 520 u32 cntcv1; 521 u32 cntcv2; 522 u32 resv1[4]; 523 u32 cntfid0; 524 u32 cntfid1; 525 u32 resv2[1002]; 526 u32 counterid[12]; 527 }; 528 529 #define SRDS_MAX_LANES 4 530 struct ccsr_serdes { 531 struct { 532 u32 rstctl; /* Reset Control Register */ 533 #define SRDS_RSTCTL_RST 0x80000000 534 #define SRDS_RSTCTL_RSTDONE 0x40000000 535 #define SRDS_RSTCTL_RSTERR 0x20000000 536 #define SRDS_RSTCTL_SWRST 0x10000000 537 #define SRDS_RSTCTL_SDEN 0x00000020 538 #define SRDS_RSTCTL_SDRST_B 0x00000040 539 #define SRDS_RSTCTL_PLLRST_B 0x00000080 540 u32 pllcr0; /* PLL Control Register 0 */ 541 #define SRDS_PLLCR0_POFF 0x80000000 542 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 543 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 544 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 545 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 546 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 547 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 548 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 549 #define SRDS_PLLCR0_PLL_LCK 0x00800000 550 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 551 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 552 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 553 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 554 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 555 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 556 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 557 u32 pllcr1; /* PLL Control Register 1 */ 558 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 559 u32 res_0c; /* 0x00c */ 560 u32 pllcr3; 561 u32 pllcr4; 562 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 563 u8 res_1c[0x20-0x1c]; 564 } bank[2]; 565 u8 res_40[0x90-0x40]; 566 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 567 u8 res_94[0xa0-0x94]; 568 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 569 u8 res_a4[0xb0-0xa4]; 570 u32 srdsgr0; /* 0xb0 General Register 0 */ 571 u8 res_b4[0x100-0xb4]; 572 struct { 573 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 574 u8 res_104[0x120-0x104]; 575 } lnpssr[4]; /* Lane A, B, C, D */ 576 u8 res_180[0x200-0x180]; 577 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 578 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 579 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 580 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 581 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 582 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 583 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 584 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 585 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 586 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 587 u32 srdspccra; /* 0x228 Protocol Configuration A */ 588 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 589 u8 res_230[0x800-0x230]; 590 struct { 591 u32 gcr0; /* 0x800 General Control Register 0 */ 592 u32 gcr1; /* 0x804 General Control Register 1 */ 593 u32 gcr2; /* 0x808 General Control Register 2 */ 594 u32 sscr0; 595 u32 recr0; /* 0x810 Receive Equalization Control */ 596 u32 recr1; 597 u32 tecr0; /* 0x818 Transmit Equalization Control */ 598 u32 sscr1; 599 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 600 u8 res_824[0x83c-0x824]; 601 u32 tcsr3; 602 } lane[4]; /* Lane A, B, C, D */ 603 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 604 struct { 605 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 606 u8 res_1004[0x1040-0x1004]; 607 } pcie[3]; 608 u8 res_10c0[0x1800-0x10c0]; 609 struct { 610 u8 res_1800[0x1804-0x1800]; 611 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 612 u8 res_1808[0x180c-0x1808]; 613 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 614 } sgmii[4]; /* Lane A, B, C, D */ 615 u8 res_1840[0x1880-0x1840]; 616 struct { 617 u8 res_1880[0x1884-0x1880]; 618 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 619 u8 res_1888[0x188c-0x1888]; 620 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 621 } qsgmii[2]; /* Lane A, B */ 622 u8 res_18a0[0x1980-0x18a0]; 623 struct { 624 u8 res_1980[0x1984-0x1980]; 625 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 626 u8 res_1988[0x198c-0x1988]; 627 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 628 } xfi[2]; /* Lane A, B */ 629 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 630 }; 631 632 struct ccsr_gpio { 633 u32 gpdir; 634 u32 gpodr; 635 u32 gpdat; 636 u32 gpier; 637 u32 gpimr; 638 u32 gpicr; 639 u32 gpibe; 640 }; 641 642 /* MMU 500 */ 643 #define SMMU_SCR0 (SMMU_BASE + 0x0) 644 #define SMMU_SCR1 (SMMU_BASE + 0x4) 645 #define SMMU_SCR2 (SMMU_BASE + 0x8) 646 #define SMMU_SACR (SMMU_BASE + 0x10) 647 #define SMMU_IDR0 (SMMU_BASE + 0x20) 648 #define SMMU_IDR1 (SMMU_BASE + 0x24) 649 650 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 651 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 652 #define SMMU_NSACR (SMMU_BASE + 0x410) 653 654 #define SCR0_CLIENTPD_MASK 0x00000001 655 #define SCR0_USFCFG_MASK 0x00000400 656 657 #ifdef CONFIG_TFABOOT 658 #define RCW_SRC_MASK (0xFF800000) 659 #define RCW_SRC_BIT 23 660 661 /* RCW SRC NAND */ 662 #define RCW_SRC_NAND_MASK (0x100) 663 #define RCW_SRC_NAND_VAL (0x100) 664 #define NAND_RESERVED_MASK (0xFC) 665 #define NAND_RESERVED_1 (0x0) 666 #define NAND_RESERVED_2 (0x80) 667 668 /* RCW SRC NOR */ 669 #define RCW_SRC_NOR_MASK (0x1F0) 670 #define NOR_8B_VAL (0x10) 671 #define NOR_16B_VAL (0x20) 672 #define SD_VAL (0x40) 673 #define QSPI_VAL1 (0x44) 674 #define QSPI_VAL2 (0x45) 675 #endif 676 677 uint get_svr(void); 678 679 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 680