1 #ifndef __ASM_MSR_INDEX_H 2 #define __ASM_MSR_INDEX_H 3 4 /* 5 * CPU model specific register (MSR) numbers 6 * 7 * Definitions for an MSR should follow this style: 8 * 9 * #define MSR_$NAME 0x$INDEX 10 * #define $NAME_$FIELD1 (_AC($X, ULL) << $POS1) 11 * #define $NAME_$FIELD2 (_AC($Y, ULL) << $POS2) 12 * 13 * Blocks of related constants should be sorted by MSR index. The constant 14 * names should be as concise as possible, and the bit names may have an 15 * abbreviated name. Exceptions will be considered on a case-by-case basis. 16 */ 17 18 #define MSR_P5_MC_ADDR 0 19 #define MSR_P5_MC_TYPE 0x00000001 20 21 #define MSR_APIC_BASE 0x0000001b 22 #define APIC_BASE_BSP (_AC(1, ULL) << 8) 23 #define APIC_BASE_EXTD (_AC(1, ULL) << 10) 24 #define APIC_BASE_ENABLE (_AC(1, ULL) << 11) 25 #define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL) 26 27 #define MSR_TEST_CTRL 0x00000033 28 #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) 29 #define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) 30 31 #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 32 #define MSR_CTC_THREAD_MASK 0x0000ffff 33 #define MSR_CTC_CORE_MASK _AC(0xffff0000, U) 34 35 #define MSR_SPEC_CTRL 0x00000048 36 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) 37 #define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) 38 #define SPEC_CTRL_SSBD (_AC(1, ULL) << 2) 39 #define SPEC_CTRL_IPRED_DIS_U (_AC(1, ULL) << 3) 40 #define SPEC_CTRL_IPRED_DIS_S (_AC(1, ULL) << 4) 41 #define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5) 42 #define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6) 43 #define SPEC_CTRL_PSFD (_AC(1, ULL) << 7) 44 #define SPEC_CTRL_DDP_DIS_U (_AC(1, ULL) << 8) 45 #define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10) 46 47 #define MSR_PRED_CMD 0x00000049 48 #define PRED_CMD_IBPB (_AC(1, ULL) << 0) 49 #define PRED_CMD_SBPB (_AC(1, ULL) << 7) 50 51 #define MSR_PPIN_CTL 0x0000004e 52 #define PPIN_LOCKOUT (_AC(1, ULL) << 0) 53 #define PPIN_ENABLE (_AC(1, ULL) << 1) 54 #define MSR_PPIN 0x0000004f 55 56 #define MSR_MISC_PACKAGE_CTRL 0x000000bc 57 #define PGK_CTRL_ENERGY_FILTER_EN (_AC(1, ULL) << 0) 58 59 #define MSR_CORE_CAPABILITIES 0x000000cf 60 #define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) 61 62 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 63 #define NHM_C3_AUTO_DEMOTE (_AC(1, ULL) << 25) 64 #define NHM_C1_AUTO_DEMOTE (_AC(1, ULL) << 26) 65 #define ATM_LNC_C6_AUTO_DEMOTE (_AC(1, ULL) << 25) 66 #define SNB_C3_AUTO_UNDEMOTE (_AC(1, ULL) << 27) 67 #define SNB_C1_AUTO_UNDEMOTE (_AC(1, ULL) << 28) 68 69 #define MSR_ARCH_CAPABILITIES 0x0000010a 70 #define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) 71 #define ARCH_CAPS_EIBRS (_AC(1, ULL) << 1) 72 #define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) 73 #define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3) 74 #define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4) 75 #define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5) 76 #define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6) 77 #define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7) 78 #define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8) 79 #define ARCH_CAPS_MISC_PACKAGE_CTRL (_AC(1, ULL) << 10) 80 #define ARCH_CAPS_ENERGY_FILTERING (_AC(1, ULL) << 11) 81 #define ARCH_CAPS_DOITM (_AC(1, ULL) << 12) 82 #define ARCH_CAPS_SBDR_SSDP_NO (_AC(1, ULL) << 13) 83 #define ARCH_CAPS_FBSDP_NO (_AC(1, ULL) << 14) 84 #define ARCH_CAPS_PSDP_NO (_AC(1, ULL) << 15) 85 #define ARCH_CAPS_FB_CLEAR (_AC(1, ULL) << 17) 86 #define ARCH_CAPS_FB_CLEAR_CTRL (_AC(1, ULL) << 18) 87 #define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19) 88 #define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20) 89 #define ARCH_CAPS_PBRSB_NO (_AC(1, ULL) << 24) 90 #define ARCH_CAPS_GDS_CTRL (_AC(1, ULL) << 25) 91 #define ARCH_CAPS_GDS_NO (_AC(1, ULL) << 26) 92 #define ARCH_CAPS_RFDS_NO (_AC(1, ULL) << 27) 93 #define ARCH_CAPS_RFDS_CLEAR (_AC(1, ULL) << 28) 94 95 #define MSR_FLUSH_CMD 0x0000010b 96 #define FLUSH_CMD_L1D (_AC(1, ULL) << 0) 97 98 #define MSR_TSX_FORCE_ABORT 0x0000010f 99 #define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0) 100 #define TSX_CPUID_CLEAR (_AC(1, ULL) << 1) 101 #define TSX_ENABLE_RTM (_AC(1, ULL) << 2) 102 103 #define MSR_TSX_CTRL 0x00000122 104 #define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0) 105 #define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1) 106 107 #define MSR_MCU_OPT_CTRL 0x00000123 108 #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0) 109 #define MCU_OPT_CTRL_RTM_ALLOW (_AC(1, ULL) << 1) 110 #define MCU_OPT_CTRL_RTM_LOCKED (_AC(1, ULL) << 2) 111 #define MCU_OPT_CTRL_FB_CLEAR_DIS (_AC(1, ULL) << 3) 112 #define MCU_OPT_CTRL_GDS_MIT_DIS (_AC(1, ULL) << 4) 113 #define MCU_OPT_CTRL_GDS_MIT_LOCK (_AC(1, ULL) << 5) 114 115 #define MSR_RTIT_OUTPUT_BASE 0x00000560 116 #define MSR_RTIT_OUTPUT_MASK 0x00000561 117 #define MSR_RTIT_CTL 0x00000570 118 #define RTIT_CTL_TRACE_EN (_AC(1, ULL) << 0) 119 #define RTIT_CTL_CYC_EN (_AC(1, ULL) << 1) 120 #define RTIT_CTL_OS (_AC(1, ULL) << 2) 121 #define RTIT_CTL_USR (_AC(1, ULL) << 3) 122 #define RTIT_CTL_PWR_EVT_EN (_AC(1, ULL) << 4) 123 #define RTIT_CTL_FUP_ON_PTW (_AC(1, ULL) << 5) 124 #define RTIT_CTL_FABRIC_EN (_AC(1, ULL) << 6) 125 #define RTIT_CTL_CR3_FILTER (_AC(1, ULL) << 7) 126 #define RTIT_CTL_TOPA (_AC(1, ULL) << 8) 127 #define RTIT_CTL_MTC_EN (_AC(1, ULL) << 9) 128 #define RTIT_CTL_TSC_EN (_AC(1, ULL) << 10) 129 #define RTIT_CTL_DIS_RETC (_AC(1, ULL) << 11) 130 #define RTIT_CTL_PTW_EN (_AC(1, ULL) << 12) 131 #define RTIT_CTL_BRANCH_EN (_AC(1, ULL) << 13) 132 #define RTIT_CTL_MTC_FREQ (_AC(0xf, ULL) << 14) 133 #define RTIT_CTL_CYC_THRESH (_AC(0xf, ULL) << 19) 134 #define RTIT_CTL_PSB_FREQ (_AC(0xf, ULL) << 24) 135 #define RTIT_CTL_ADDR(n) (_AC(0xf, ULL) << (32 + 4 * (n))) 136 #define MSR_RTIT_STATUS 0x00000571 137 #define RTIT_STATUS_FILTER_EN (_AC(1, ULL) << 0) 138 #define RTIT_STATUS_CONTEXT_EN (_AC(1, ULL) << 1) 139 #define RTIT_STATUS_TRIGGER_EN (_AC(1, ULL) << 2) 140 #define RTIT_STATUS_ERROR (_AC(1, ULL) << 4) 141 #define RTIT_STATUS_STOPPED (_AC(1, ULL) << 5) 142 #define RTIT_STATUS_BYTECNT (_AC(0x1ffff, ULL) << 32) 143 #define MSR_RTIT_CR3_MATCH 0x00000572 144 #define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) 145 #define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) 146 147 #define MSR_U_CET 0x000006a0 148 #define MSR_S_CET 0x000006a2 149 #define CET_SHSTK_EN (_AC(1, ULL) << 0) 150 #define CET_WRSS_EN (_AC(1, ULL) << 1) 151 #define CET_ENDBR_EN (_AC(1, ULL) << 2) 152 153 #define MSR_PL0_SSP 0x000006a4 154 #define MSR_PL1_SSP 0x000006a5 155 #define MSR_PL2_SSP 0x000006a6 156 #define MSR_PL3_SSP 0x000006a7 157 #define MSR_INTERRUPT_SSP_TABLE 0x000006a8 158 159 #define MSR_PKRS 0x000006e1 160 161 #define MSR_PM_ENABLE 0x00000770 162 #define PM_ENABLE_HWP_ENABLE BIT(0, ULL) 163 164 #define MSR_HWP_CAPABILITIES 0x00000771 165 #define MSR_HWP_INTERRUPT 0x00000773 166 #define MSR_HWP_REQUEST 0x00000774 167 #define MSR_HWP_STATUS 0x00000777 168 169 #define MSR_X2APIC_FIRST 0x00000800 170 #define MSR_X2APIC_LAST 0x000008ff 171 172 #define MSR_X2APIC_TPR 0x00000808 173 #define MSR_X2APIC_PPR 0x0000080a 174 #define MSR_X2APIC_EOI 0x0000080b 175 #define MSR_X2APIC_TMICT 0x00000838 176 #define MSR_X2APIC_TMCCT 0x00000839 177 #define MSR_X2APIC_SELF 0x0000083f 178 179 #define MSR_PASID 0x00000d93 180 #define PASID_PASID_MASK 0x000fffff 181 #define PASID_VALID (_AC(1, ULL) << 31) 182 183 #define MSR_PKG_HDC_CTL 0x00000db0 184 #define PKG_HDC_CTL_HDC_PKG_ENABLE BIT(0, ULL) 185 #define MSR_PM_CTL1 0x00000db1 186 #define PM_CTL1_HDC_ALLOW_BLOCK BIT(0, ULL) 187 188 #define MSR_MCU_CONTROL 0x00001406 189 #define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) 190 #define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) 191 #define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) 192 193 #define MSR_UARCH_MISC_CTRL 0x00001b01 194 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) 195 196 #define MSR_EFER _AC(0xc0000080, U) /* Extended Feature Enable Register */ 197 #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */ 198 #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */ 199 #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */ 200 #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ 201 #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ 202 #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ 203 #define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ 204 205 #define EFER_KNOWN_MASK \ 206 (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ 207 EFER_AIBRSE) 208 209 #define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */ 210 #define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */ 211 #define MSR_CSTAR _AC(0xc0000083, U) /* compat mode SYSCALL target */ 212 #define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS mask for syscall */ 213 #define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit FS base */ 214 #define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit GS base */ 215 #define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS GS shadow */ 216 #define MSR_TSC_AUX _AC(0xc0000103, U) /* Auxiliary TSC */ 217 218 #define MSR_K8_SYSCFG _AC(0xc0010010, U) 219 #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18) 220 #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19) 221 #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20) 222 #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21) 223 #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22) 224 225 #define MSR_K8_IORR_BASE0 _AC(0xc0010016, U) 226 #define MSR_K8_IORR_MASK0 _AC(0xc0010017, U) 227 #define MSR_K8_IORR_BASE1 _AC(0xc0010018, U) 228 #define MSR_K8_IORR_MASK1 _AC(0xc0010019, U) 229 230 #define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD doc: SMMAddr */ 231 #define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD doc: SMMMask */ 232 233 #define MSR_K8_VM_CR _AC(0xc0010114, U) 234 #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) 235 #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) 236 237 #define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout matches MSR_SPEC_CTRL */ 238 239 #define MSR_AMD_CSTATE_CFG 0xc0010296U 240 241 /* 242 * Legacy MSR constants in need of cleanup. No new MSRs below this comment. 243 */ 244 245 /* Intel MSRs. Some also available on other CPUs */ 246 #define MSR_IA32_PERFCTR0 0x000000c1 247 #define MSR_IA32_A_PERFCTR0 0x000004c1 248 #define MSR_FSB_FREQ 0x000000cd 249 250 #define MSR_MTRRcap 0x000000fe 251 #define MTRRcap_VCNT 0x000000ff 252 253 #define MSR_IA32_BBL_CR_CTL 0x00000119 254 255 #define MSR_IA32_SYSENTER_CS 0x00000174 256 #define MSR_IA32_SYSENTER_ESP 0x00000175 257 #define MSR_IA32_SYSENTER_EIP 0x00000176 258 259 #define MSR_IA32_MCG_CAP 0x00000179 260 #define MSR_IA32_MCG_STATUS 0x0000017a 261 #define MSR_IA32_MCG_CTL 0x0000017b 262 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 263 264 #define MSR_IA32_PEBS_ENABLE 0x000003f1 265 #define MSR_IA32_DS_AREA 0x00000600 266 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 267 /* Lower 6 bits define the format of the address in the LBR stack */ 268 #define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f 269 270 #define MSR_IA32_BNDCFGS 0x00000d90 271 #define IA32_BNDCFGS_ENABLE 0x00000001 272 #define IA32_BNDCFGS_PRESERVE 0x00000002 273 #define IA32_BNDCFGS_RESERVED 0x00000ffc 274 275 #define MSR_IA32_XSS 0x00000da0 276 277 #define MSR_MTRRfix64K_00000 0x00000250 278 #define MSR_MTRRfix16K_80000 0x00000258 279 #define MSR_MTRRfix16K_A0000 0x00000259 280 #define MSR_MTRRfix4K_C0000 0x00000268 281 #define MSR_MTRRfix4K_C8000 0x00000269 282 #define MSR_MTRRfix4K_D0000 0x0000026a 283 #define MSR_MTRRfix4K_D8000 0x0000026b 284 #define MSR_MTRRfix4K_E0000 0x0000026c 285 #define MSR_MTRRfix4K_E8000 0x0000026d 286 #define MSR_MTRRfix4K_F0000 0x0000026e 287 #define MSR_MTRRfix4K_F8000 0x0000026f 288 #define MSR_MTRRdefType 0x000002ff 289 #define MTRRdefType_FE (1u << 10) 290 #define MTRRdefType_E (1u << 11) 291 292 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 293 #define IA32_DEBUGCTLMSR_LBR (1<<0) /* Last Branch Record */ 294 #define IA32_DEBUGCTLMSR_BTF (1<<1) /* Single Step on Branches */ 295 #define IA32_DEBUGCTLMSR_TR (1<<6) /* Trace Message Enable */ 296 #define IA32_DEBUGCTLMSR_BTS (1<<7) /* Branch Trace Store */ 297 #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ 298 #define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9) /* BTS off if CPL 0 */ 299 #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ 300 #define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ 301 302 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 303 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 304 #define MSR_IA32_LASTINTFROMIP 0x000001dd 305 #define MSR_IA32_LASTINTTOIP 0x000001de 306 307 #define MSR_IA32_POWER_CTL 0x000001fc 308 309 #define MSR_IA32_MTRR_PHYSBASE(n) (0x00000200 + 2 * (n)) 310 #define MSR_IA32_MTRR_PHYSMASK(n) (0x00000201 + 2 * (n)) 311 312 #define MSR_IA32_CR_PAT 0x00000277 313 #define MSR_IA32_CR_PAT_RESET 0x0007040600070406ULL 314 315 #define MSR_IA32_MC0_CTL 0x00000400 316 #define MSR_IA32_MC0_STATUS 0x00000401 317 #define MSR_IA32_MC0_ADDR 0x00000402 318 #define MSR_IA32_MC0_MISC 0x00000403 319 #define MSR_IA32_MC0_CTL2 0x00000280 320 #define CMCI_EN (1UL<<30) 321 #define CMCI_THRESHOLD_MASK 0x7FFF 322 323 #define MSR_AMD64_MC0_MASK 0xc0010044U 324 325 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 326 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 327 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 328 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 329 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 330 331 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 332 333 /* MSRs & bits used for VMX enabling */ 334 #define MSR_IA32_VMX_BASIC 0x480 335 #define MSR_IA32_VMX_PINBASED_CTLS 0x481 336 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 337 #define MSR_IA32_VMX_EXIT_CTLS 0x483 338 #define MSR_IA32_VMX_ENTRY_CTLS 0x484 339 #define MSR_IA32_VMX_MISC 0x485 340 #define MSR_IA32_VMX_CR0_FIXED0 0x486 341 #define MSR_IA32_VMX_CR0_FIXED1 0x487 342 #define MSR_IA32_VMX_CR4_FIXED0 0x488 343 #define MSR_IA32_VMX_CR4_FIXED1 0x489 344 #define MSR_IA32_VMX_VMCS_ENUM 0x48a 345 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b 346 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 347 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d 348 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 349 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f 350 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 351 #define MSR_IA32_VMX_VMFUNC 0x491 352 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x492 353 354 /* K7/K8 MSRs. Not complete. See the architecture manual for a more 355 complete list. */ 356 #define MSR_K7_EVNTSEL0 0xc0010000U 357 #define MSR_K7_PERFCTR0 0xc0010004U 358 #define MSR_K7_EVNTSEL1 0xc0010001U 359 #define MSR_K7_PERFCTR1 0xc0010005U 360 #define MSR_K7_EVNTSEL2 0xc0010002U 361 #define MSR_K7_PERFCTR2 0xc0010006U 362 #define MSR_K7_EVNTSEL3 0xc0010003U 363 #define MSR_K7_PERFCTR3 0xc0010007U 364 #define MSR_K8_TOP_MEM1 0xc001001aU 365 #define MSR_K8_TOP_MEM2 0xc001001dU 366 367 #define MSR_K8_HWCR 0xc0010015U 368 #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) 369 #define K8_HWCR_CPUID_USER_DIS (1ULL << 35) 370 371 #define MSR_K7_FID_VID_CTL 0xc0010041U 372 #define MSR_K7_FID_VID_STATUS 0xc0010042U 373 #define MSR_K8_PSTATE_LIMIT 0xc0010061U 374 #define MSR_K8_PSTATE_CTRL 0xc0010062U 375 #define MSR_K8_PSTATE_STATUS 0xc0010063U 376 #define MSR_K8_PSTATE0 0xc0010064U 377 #define MSR_K8_PSTATE1 0xc0010065U 378 #define MSR_K8_PSTATE2 0xc0010066U 379 #define MSR_K8_PSTATE3 0xc0010067U 380 #define MSR_K8_PSTATE4 0xc0010068U 381 #define MSR_K8_PSTATE5 0xc0010069U 382 #define MSR_K8_PSTATE6 0xc001006AU 383 #define MSR_K8_PSTATE7 0xc001006BU 384 #define MSR_K8_ENABLE_C1E 0xc0010055U 385 #define MSR_K8_VM_HSAVE_PA 0xc0010117U 386 387 #define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U 388 #define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U 389 #define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U 390 #define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U 391 #define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U 392 #define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U 393 #define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U 394 #define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U 395 #define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U 396 #define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U 397 #define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU 398 #define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU 399 400 #define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U 401 #define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U 402 #define MSR_K8_FEATURE_MASK 0xc0011004U 403 #define MSR_K8_EXT_FEATURE_MASK 0xc0011005U 404 405 /* AMD64 MSRs */ 406 #define MSR_AMD64_NB_CFG 0xc001001fU 407 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 408 #define MSR_AMD64_LS_CFG 0xc0011020U 409 #define MSR_AMD64_IC_CFG 0xc0011021U 410 #define MSR_AMD64_DC_CFG 0xc0011022U 411 #define MSR_AMD64_DE_CFG 0xc0011029U 412 #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1) 413 #define MSR_AMD64_EX_CFG 0xc001102cU 414 #define MSR_AMD64_BP_CFG 0xc001102eU 415 #define MSR_AMD64_DE_CFG2 0xc00110e3U 416 417 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U 418 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U 419 #define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU 420 #define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU 421 422 /* AMD Family10h machine check MSRs */ 423 #define MSR_F10_MC4_MISC1 0xc0000408U 424 #define MSR_F10_MC4_MISC2 0xc0000409U 425 #define MSR_F10_MC4_MISC3 0xc000040AU 426 427 /* AMD Family10h Bus Unit MSRs */ 428 #define MSR_F10_BU_CFG 0xc0011023U 429 #define MSR_F10_BU_CFG2 0xc001102aU 430 431 /* Other AMD Fam10h MSRs */ 432 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U 433 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 434 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 435 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 436 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 437 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 438 439 /* AMD Microcode MSRs */ 440 #define MSR_AMD_PATCHLEVEL 0x0000008b 441 #define MSR_AMD_PATCHLOADER 0xc0010020U 442 443 /* AMD TSC RATE MSR */ 444 #define MSR_AMD64_TSC_RATIO 0xc0000104U 445 446 /* AMD Lightweight Profiling MSRs */ 447 #define MSR_AMD64_LWP_CFG 0xc0000105U 448 #define MSR_AMD64_LWP_CBADDR 0xc0000106U 449 450 /* AMD OS Visible Workaround MSRs */ 451 #define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U 452 #define MSR_AMD_OSVW_STATUS 0xc0010141U 453 454 /* AMD Protected Processor Inventory Number */ 455 #define MSR_AMD_PPIN_CTL 0xc00102f0U 456 #define MSR_AMD_PPIN 0xc00102f1U 457 458 /* VIA Cyrix defined MSRs*/ 459 #define MSR_VIA_FCR 0x00001107 460 #define MSR_VIA_RNG 0x0000110b 461 462 /* Intel defined MSRs. */ 463 #define MSR_IA32_TSC 0x00000010 464 #define MSR_IA32_PLATFORM_ID 0x00000017 465 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 466 #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c 467 468 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 469 #define IA32_FEATURE_CONTROL_LOCK 0x0001 470 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 471 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 472 #define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 473 #define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 474 #define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 475 #define IA32_FEATURE_CONTROL_LMCE_ON 0x100000 476 477 #define MSR_IA32_TSC_ADJUST 0x0000003b 478 479 #define MSR_IA32_UCODE_WRITE 0x00000079 480 #define MSR_IA32_UCODE_REV 0x0000008b 481 482 #define MSR_IA32_PERF_STATUS 0x00000198 483 #define MSR_IA32_PERF_CTL 0x00000199 484 485 #define MSR_IA32_MPERF 0x000000e7 486 #define MSR_IA32_APERF 0x000000e8 487 488 #define MSR_IA32_THERM_CONTROL 0x0000019a 489 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 490 #define MSR_IA32_THERM_STATUS 0x0000019c 491 #define MSR_IA32_MISC_ENABLE 0x000001a0 492 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) 493 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) 494 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) 495 #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) 496 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) 497 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) 498 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (_AC(1, ULL) << 34) 499 #define MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE (_AC(1, ULL) << 38) 500 501 #define MSR_IA32_TSC_DEADLINE 0x000006E0 502 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 503 504 /* Platform Shared Resource MSRs */ 505 #define MSR_IA32_CMT_EVTSEL 0x00000c8d 506 #define MSR_IA32_CMT_EVTSEL_UE_MASK 0x0000ffff 507 #define MSR_IA32_CMT_CTR 0x00000c8e 508 #define MSR_IA32_PSR_ASSOC 0x00000c8f 509 #define MSR_IA32_PSR_L3_QOS_CFG 0x00000c81 510 #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) 511 #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) 512 #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) 513 #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) 514 #define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n)) 515 516 /* Intel Model 6 */ 517 #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) 518 #define MSR_P6_EVNTSEL(n) (0x00000186 + (n)) 519 520 /* P4/Xeon+ specific */ 521 #define MSR_IA32_MCG_EAX 0x00000180 522 #define MSR_IA32_MCG_EBX 0x00000181 523 #define MSR_IA32_MCG_ECX 0x00000182 524 #define MSR_IA32_MCG_EDX 0x00000183 525 #define MSR_IA32_MCG_ESI 0x00000184 526 #define MSR_IA32_MCG_EDI 0x00000185 527 #define MSR_IA32_MCG_EBP 0x00000186 528 #define MSR_IA32_MCG_ESP 0x00000187 529 #define MSR_IA32_MCG_EFLAGS 0x00000188 530 #define MSR_IA32_MCG_EIP 0x00000189 531 #define MSR_IA32_MCG_MISC 0x0000018a 532 #define MSR_IA32_MCG_R8 0x00000190 533 #define MSR_IA32_MCG_R9 0x00000191 534 #define MSR_IA32_MCG_R10 0x00000192 535 #define MSR_IA32_MCG_R11 0x00000193 536 #define MSR_IA32_MCG_R12 0x00000194 537 #define MSR_IA32_MCG_R13 0x00000195 538 #define MSR_IA32_MCG_R14 0x00000196 539 #define MSR_IA32_MCG_R15 0x00000197 540 541 /* Pentium IV performance counter MSRs */ 542 #define MSR_P4_BPU_PERFCTR0 0x00000300 543 #define MSR_P4_BPU_PERFCTR1 0x00000301 544 #define MSR_P4_BPU_PERFCTR2 0x00000302 545 #define MSR_P4_BPU_PERFCTR3 0x00000303 546 #define MSR_P4_MS_PERFCTR0 0x00000304 547 #define MSR_P4_MS_PERFCTR1 0x00000305 548 #define MSR_P4_MS_PERFCTR2 0x00000306 549 #define MSR_P4_MS_PERFCTR3 0x00000307 550 #define MSR_P4_FLAME_PERFCTR0 0x00000308 551 #define MSR_P4_FLAME_PERFCTR1 0x00000309 552 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 553 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 554 #define MSR_P4_IQ_PERFCTR0 0x0000030c 555 #define MSR_P4_IQ_PERFCTR1 0x0000030d 556 #define MSR_P4_IQ_PERFCTR2 0x0000030e 557 #define MSR_P4_IQ_PERFCTR3 0x0000030f 558 #define MSR_P4_IQ_PERFCTR4 0x00000310 559 #define MSR_P4_IQ_PERFCTR5 0x00000311 560 #define MSR_P4_BPU_CCCR0 0x00000360 561 #define MSR_P4_BPU_CCCR1 0x00000361 562 #define MSR_P4_BPU_CCCR2 0x00000362 563 #define MSR_P4_BPU_CCCR3 0x00000363 564 #define MSR_P4_MS_CCCR0 0x00000364 565 #define MSR_P4_MS_CCCR1 0x00000365 566 #define MSR_P4_MS_CCCR2 0x00000366 567 #define MSR_P4_MS_CCCR3 0x00000367 568 #define MSR_P4_FLAME_CCCR0 0x00000368 569 #define MSR_P4_FLAME_CCCR1 0x00000369 570 #define MSR_P4_FLAME_CCCR2 0x0000036a 571 #define MSR_P4_FLAME_CCCR3 0x0000036b 572 #define MSR_P4_IQ_CCCR0 0x0000036c 573 #define MSR_P4_IQ_CCCR1 0x0000036d 574 #define MSR_P4_IQ_CCCR2 0x0000036e 575 #define MSR_P4_IQ_CCCR3 0x0000036f 576 #define MSR_P4_IQ_CCCR4 0x00000370 577 #define MSR_P4_IQ_CCCR5 0x00000371 578 #define MSR_P4_ALF_ESCR0 0x000003ca 579 #define MSR_P4_ALF_ESCR1 0x000003cb 580 #define MSR_P4_BPU_ESCR0 0x000003b2 581 #define MSR_P4_BPU_ESCR1 0x000003b3 582 #define MSR_P4_BSU_ESCR0 0x000003a0 583 #define MSR_P4_BSU_ESCR1 0x000003a1 584 #define MSR_P4_CRU_ESCR0 0x000003b8 585 #define MSR_P4_CRU_ESCR1 0x000003b9 586 #define MSR_P4_CRU_ESCR2 0x000003cc 587 #define MSR_P4_CRU_ESCR3 0x000003cd 588 #define MSR_P4_CRU_ESCR4 0x000003e0 589 #define MSR_P4_CRU_ESCR5 0x000003e1 590 #define MSR_P4_DAC_ESCR0 0x000003a8 591 #define MSR_P4_DAC_ESCR1 0x000003a9 592 #define MSR_P4_FIRM_ESCR0 0x000003a4 593 #define MSR_P4_FIRM_ESCR1 0x000003a5 594 #define MSR_P4_FLAME_ESCR0 0x000003a6 595 #define MSR_P4_FLAME_ESCR1 0x000003a7 596 #define MSR_P4_FSB_ESCR0 0x000003a2 597 #define MSR_P4_FSB_ESCR1 0x000003a3 598 #define MSR_P4_IQ_ESCR0 0x000003ba 599 #define MSR_P4_IQ_ESCR1 0x000003bb 600 #define MSR_P4_IS_ESCR0 0x000003b4 601 #define MSR_P4_IS_ESCR1 0x000003b5 602 #define MSR_P4_ITLB_ESCR0 0x000003b6 603 #define MSR_P4_ITLB_ESCR1 0x000003b7 604 #define MSR_P4_IX_ESCR0 0x000003c8 605 #define MSR_P4_IX_ESCR1 0x000003c9 606 #define MSR_P4_MOB_ESCR0 0x000003aa 607 #define MSR_P4_MOB_ESCR1 0x000003ab 608 #define MSR_P4_MS_ESCR0 0x000003c0 609 #define MSR_P4_MS_ESCR1 0x000003c1 610 #define MSR_P4_PMH_ESCR0 0x000003ac 611 #define MSR_P4_PMH_ESCR1 0x000003ad 612 #define MSR_P4_RAT_ESCR0 0x000003bc 613 #define MSR_P4_RAT_ESCR1 0x000003bd 614 #define MSR_P4_SAAT_ESCR0 0x000003ae 615 #define MSR_P4_SAAT_ESCR1 0x000003af 616 #define MSR_P4_SSU_ESCR0 0x000003be 617 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 618 619 #define MSR_P4_TBPU_ESCR0 0x000003c2 620 #define MSR_P4_TBPU_ESCR1 0x000003c3 621 #define MSR_P4_TC_ESCR0 0x000003c4 622 #define MSR_P4_TC_ESCR1 0x000003c5 623 #define MSR_P4_U2L_ESCR0 0x000003b0 624 #define MSR_P4_U2L_ESCR1 0x000003b1 625 626 /* Netburst (P4) last-branch recording */ 627 #define MSR_P4_LER_FROM_LIP 0x000001d7 628 #define MSR_P4_LER_TO_LIP 0x000001d8 629 #define MSR_P4_LASTBRANCH_TOS 0x000001da 630 #define MSR_P4_LASTBRANCH_0 0x000001db 631 #define NUM_MSR_P4_LASTBRANCH 4 632 #define MSR_P4_LASTBRANCH_0_FROM_LIP 0x00000680 633 #define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0 634 #define NUM_MSR_P4_LASTBRANCH_FROM_TO 16 635 636 /* Core 2 and Atom last-branch recording */ 637 #define MSR_C2_LASTBRANCH_TOS 0x000001c9 638 #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040 639 #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060 640 #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4 641 #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8 642 643 /* Nehalem (and newer) last-branch recording */ 644 #define MSR_NHL_LBR_SELECT 0x000001c8 645 #define MSR_NHL_LASTBRANCH_TOS 0x000001c9 646 647 /* Skylake (and newer) last-branch recording */ 648 #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680 649 #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0 650 #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0 651 #define NUM_MSR_SKL_LASTBRANCH 32 652 653 /* Silvermont (and newer) last-branch recording */ 654 #define MSR_SM_LBR_SELECT 0x000001c8 655 #define MSR_SM_LASTBRANCH_TOS 0x000001c9 656 657 /* Goldmont last-branch recording */ 658 #define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680 659 #define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0 660 #define NUM_MSR_GM_LASTBRANCH_FROM_TO 32 661 662 /* Intel Core-based CPU performance counters */ 663 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 664 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 665 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 666 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 667 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 668 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 669 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 670 671 /* Intel cpuid spoofing MSRs */ 672 #define MSR_INTEL_MASK_V1_CPUID1 0x00000478 673 674 #define MSR_INTEL_MASK_V2_CPUID1 0x00000130 675 #define MSR_INTEL_MASK_V2_CPUID80000001 0x00000131 676 677 #define MSR_INTEL_MASK_V3_CPUID1 0x00000132 678 #define MSR_INTEL_MASK_V3_CPUID80000001 0x00000133 679 #define MSR_INTEL_MASK_V3_CPUIDD_01 0x00000134 680 681 /* Intel cpuid faulting MSRs */ 682 #define MSR_INTEL_PLATFORM_INFO 0x000000ce 683 #define _MSR_PLATFORM_INFO_CPUID_FAULTING 31 684 #define MSR_PLATFORM_INFO_CPUID_FAULTING (1ULL << _MSR_PLATFORM_INFO_CPUID_FAULTING) 685 686 #define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140 687 #define _MSR_MISC_FEATURES_CPUID_FAULTING 0 688 #define MSR_MISC_FEATURES_CPUID_FAULTING (1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING) 689 690 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 691 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 692 693 /* Interrupt Response Limit */ 694 #define MSR_PKGC3_IRTL 0x0000060a 695 #define MSR_PKGC6_IRTL 0x0000060b 696 #define MSR_PKGC7_IRTL 0x0000060c 697 #define MSR_PKGC8_IRTL 0x00000633 698 #define MSR_PKGC9_IRTL 0x00000634 699 #define MSR_PKGC10_IRTL 0x00000635 700 701 #endif /* __ASM_MSR_INDEX_H */ 702