1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <i2c.h>
9 #include <init.h>
10 #include <miiphy.h>
11 #include <net.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include "../common/tlv_data.h"
21
22 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
23 #include <../serdes/a38x/high_speed_env_spec.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /*
28 * Those values and defines are taken from the Marvell U-Boot version
29 * "u-boot-2013.01-15t1-clearfog"
30 */
31 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
32 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
33
34 #define BOARD_GPP_OUT_VAL_LOW 0x0
35 #define BOARD_GPP_OUT_VAL_MID 0x0
36 #define BOARD_GPP_POL_LOW 0x0
37 #define BOARD_GPP_POL_MID 0x0
38
39 static struct tlv_data cf_tlv_data;
40
cf_read_tlv_data(void)41 static void cf_read_tlv_data(void)
42 {
43 static bool read_once;
44
45 if (read_once)
46 return;
47 read_once = true;
48
49 read_tlv_data(&cf_tlv_data);
50 }
51
52 /* The starting board_serdes_map reflects original Clearfog Pro usage */
53 static struct serdes_map board_serdes_map[] = {
54 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
55 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
56 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
57 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
58 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
59 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
60 };
61
config_cfbase_serdes_map(void)62 void config_cfbase_serdes_map(void)
63 {
64 board_serdes_map[4].serdes_type = USB3_HOST0;
65 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
66 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
67 }
68
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)69 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
70 {
71 cf_read_tlv_data();
72
73 /* Apply build configuration options before runtime configuration */
74 if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
75 board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
76
77 if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
78 board_serdes_map[4].serdes_type = SATA2;
79 board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
80 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
81 board_serdes_map[4].swap_rx = 1;
82 }
83
84 if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
85 board_serdes_map[2].serdes_type = SATA1;
86 board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
87 board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
88 board_serdes_map[2].swap_rx = 1;
89 }
90
91 /* Apply runtime detection changes */
92 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
93 board_serdes_map[0].serdes_type = PEX0;
94 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
95 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
96 } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
97 /* handle recognized product as noop, no adjustment required */
98 } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
99 config_cfbase_serdes_map();
100 } else {
101 /*
102 * Fallback to static default. EEPROM TLV support is not
103 * enabled, runtime detection failed, hardware support is not
104 * present, EEPROM is corrupt, or an unrecognized product name
105 * is present.
106 */
107 if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
108 puts("EEPROM TLV detection failed: ");
109 puts("Using static config for ");
110 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
111 puts("Clearfog Base.\n");
112 config_cfbase_serdes_map();
113 } else {
114 puts("Clearfog Pro.\n");
115 }
116 }
117
118 *serdes_map_array = board_serdes_map;
119 *count = ARRAY_SIZE(board_serdes_map);
120 return 0;
121 }
122
123 /*
124 * Define the DDR layout / topology here in the board file. This will
125 * be used by the DDR3 init code in the SPL U-Boot version to configure
126 * the DDR3 controller.
127 */
128 static struct mv_ddr_topology_map board_topology_map = {
129 DEBUG_LEVEL_ERROR,
130 0x1, /* active interfaces */
131 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
132 { { { {0x1, 0, 0, 0},
133 {0x1, 0, 0, 0},
134 {0x1, 0, 0, 0},
135 {0x1, 0, 0, 0},
136 {0x1, 0, 0, 0} },
137 SPEED_BIN_DDR_1600K, /* speed_bin */
138 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
139 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
140 MV_DDR_FREQ_800, /* frequency */
141 0, 0, /* cas_wl cas_l */
142 MV_DDR_TEMP_LOW, /* temperature */
143 MV_DDR_TIM_DEFAULT} }, /* timing */
144 BUS_MASK_32BIT, /* Busses mask */
145 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
146 NOT_COMBINED, /* ddr twin-die combined */
147 { {0} }, /* raw spd data */
148 {0}, /* timing parameters */
149 { {0} }, /* electrical configuration */
150 {0,}, /* electrical parameters */
151 0, /* ODT configuration */
152 0x3, /* clock enable mask */
153 };
154
mv_ddr_topology_map_get(void)155 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
156 {
157 struct if_params *ifp = &board_topology_map.interface_params[0];
158
159 cf_read_tlv_data();
160
161 switch (cf_tlv_data.ram_size) {
162 case 4:
163 default:
164 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
165 break;
166 case 8:
167 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
168 break;
169 }
170
171 /* Return the board topology as defined in the board code */
172 return &board_topology_map;
173 }
174
board_early_init_f(void)175 int board_early_init_f(void)
176 {
177 /* Configure MPP */
178 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
179 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
180 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
181 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
182 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
183 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
184 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
185 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
186
187 /* Set GPP Out value */
188 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
189 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
190
191 /* Set GPP Polarity */
192 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
193 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
194
195 /* Set GPP Out Enable */
196 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
197 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
198
199 return 0;
200 }
201
board_init(void)202 int board_init(void)
203 {
204 /* Address of boot parameters */
205 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
206
207 /* Toggle GPIO41 to reset onboard switch and phy */
208 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
209 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
210 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
211 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
212 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
213 mdelay(1);
214 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
215 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
216 mdelay(10);
217
218 return 0;
219 }
220
checkboard(void)221 int checkboard(void)
222 {
223 char *board = "Clearfog Pro";
224 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
225 board = "Clearfog Base";
226
227 cf_read_tlv_data();
228 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
229 board = cf_tlv_data.tlv_product_name[0];
230
231 printf("Board: SolidRun %s", board);
232 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
233 printf(", %s", cf_tlv_data.tlv_product_name[1]);
234 puts("\n");
235
236 return 0;
237 }
238
board_eth_init(struct bd_info * bis)239 int board_eth_init(struct bd_info *bis)
240 {
241 cpu_eth_init(bis); /* Built in controller(s) come first */
242 return pci_eth_init(bis);
243 }
244
board_late_init(void)245 int board_late_init(void)
246 {
247 if (env_get("fdtfile"))
248 return 0;
249
250 cf_read_tlv_data();
251
252 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
253 env_set("fdtfile", "armada-388-clearfog-base.dtb");
254 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
255 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
256 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
257 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
258 else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
259 env_set("fdtfile", "armada-388-clearfog-base.dtb");
260 else
261 env_set("fdtfile", "armada-388-clearfog-pro.dtb");
262
263 return 0;
264 }
265
has_emmc(void)266 static bool has_emmc(void)
267 {
268 struct mmc *mmc;
269
270 mmc = find_mmc_device(0);
271 if (!mmc)
272 return 0;
273 return (!mmc_init(mmc) && IS_MMC(mmc)) ? true : false;
274 }
275
276 /*
277 * The Clearfog devices have only one SDHC device. This is either eMMC
278 * if it is populated on the SOM or SDHC if not. The Linux device tree
279 * assumes the SDHC case. Detect if the device is an eMMC and fixup the
280 * device-tree, so that it will be detected by Linux.
281 */
ft_board_setup(void * blob,struct bd_info * bd)282 int ft_board_setup(void *blob, struct bd_info *bd)
283 {
284 int node;
285
286 if (has_emmc()) {
287 node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-380-sdhci");
288 if (node < 0)
289 return 0; /* Unexpected eMMC device; patching not supported */
290
291 puts("Patching FDT so that eMMC is detected by OS\n");
292 return fdt_setprop_empty(blob, node, "non-removable");
293 }
294
295 return 0;
296 }
297