1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 4 * Altera Corporation <www.altera.com> 5 */ 6 7 #ifndef __CADENCE_QSPI_H__ 8 #define __CADENCE_QSPI_H__ 9 10 #include <reset.h> 11 #include <linux/mtd/spi-nor.h> 12 #include <spi-mem.h> 13 14 #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) 15 16 #define CQSPI_NO_DECODER_MAX_CS 4 17 #define CQSPI_DECODER_MAX_CS 16 18 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 19 20 #define CQSPI_REG_POLL_US 1 /* 1us */ 21 #define CQSPI_REG_RETRY 10000 22 #define CQSPI_POLL_IDLE_RETRY 3 23 24 /* Transfer mode */ 25 #define CQSPI_INST_TYPE_SINGLE 0 26 #define CQSPI_INST_TYPE_DUAL 1 27 #define CQSPI_INST_TYPE_QUAD 2 28 #define CQSPI_INST_TYPE_OCTAL 3 29 30 #define CQSPI_STIG_DATA_LEN_MAX 8 31 32 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 33 #define CQSPI_DUMMY_BYTES_MAX 4 34 #define CQSPI_DUMMY_CLKS_MAX 31 35 36 /**************************************************************************** 37 * Controller's configuration and status register (offset from QSPI_BASE) 38 ****************************************************************************/ 39 #define CQSPI_REG_CONFIG 0x00 40 #define CQSPI_REG_CONFIG_ENABLE BIT(0) 41 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) 42 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2) 43 #define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) 44 #define CQSPI_REG_CONFIG_DIRECT BIT(7) 45 #define CQSPI_REG_CONFIG_DECODE BIT(9) 46 #define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) 47 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18) 48 #define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24) 49 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 50 #define CQSPI_REG_CONFIG_BAUD_LSB 19 51 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 52 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 53 #define CQSPI_REG_CONFIG_IDLE_LSB 31 54 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 55 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 56 57 #define CQSPI_REG_RD_INSTR 0x04 58 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 59 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 60 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 61 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 62 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 63 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 64 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 65 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 66 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 67 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 68 69 #define CQSPI_REG_WR_INSTR 0x08 70 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 71 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 72 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 73 74 #define CQSPI_REG_DELAY 0x0C 75 #define CQSPI_REG_DELAY_TSLCH_LSB 0 76 #define CQSPI_REG_DELAY_TCHSH_LSB 8 77 #define CQSPI_REG_DELAY_TSD2D_LSB 16 78 #define CQSPI_REG_DELAY_TSHSL_LSB 24 79 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 80 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 81 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 82 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 83 84 #define CQSPI_REG_RD_DATA_CAPTURE 0x10 85 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) 86 #define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8) 87 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 88 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF 89 90 #define CQSPI_REG_SIZE 0x14 91 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 92 #define CQSPI_REG_SIZE_PAGE_LSB 4 93 #define CQSPI_REG_SIZE_BLOCK_LSB 16 94 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 95 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 96 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 97 98 #define CQSPI_REG_SRAMPARTITION 0x18 99 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 100 101 #define CQSPI_REG_REMAP 0x24 102 #define CQSPI_REG_MODE_BIT 0x28 103 104 #define CQSPI_REG_SDRAMLEVEL 0x2C 105 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 106 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 107 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 108 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 109 110 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 111 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 112 113 #define CQSPI_REG_IRQSTATUS 0x40 114 #define CQSPI_REG_IRQMASK 0x44 115 116 #define CQSPI_REG_INDIRECTRD 0x60 117 #define CQSPI_REG_INDIRECTRD_START BIT(0) 118 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) 119 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) 120 #define CQSPI_REG_INDIRECTRD_DONE BIT(5) 121 122 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 123 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 124 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 125 126 #define CQSPI_REG_CMDCTRL 0x90 127 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) 128 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) 129 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 130 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 131 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 132 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 133 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 134 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 135 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 136 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 137 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 138 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 139 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 140 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 141 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF 142 143 #define CQSPI_REG_INDIRECTWR 0x70 144 #define CQSPI_REG_INDIRECTWR_START BIT(0) 145 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) 146 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) 147 #define CQSPI_REG_INDIRECTWR_DONE BIT(5) 148 149 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 150 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 151 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 152 153 #define CQSPI_REG_CMDADDRESS 0x94 154 #define CQSPI_REG_CMDREADDATALOWER 0xA0 155 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 156 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 157 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 158 159 #define CQSPI_REG_OP_EXT_LOWER 0xE0 160 #define CQSPI_REG_OP_EXT_READ_LSB 24 161 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 162 #define CQSPI_REG_OP_EXT_STIG_LSB 0 163 164 #define CQSPI_REG_PHY_CONFIG 0xB4 165 #define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000 166 167 #define CQSPI_DMA_DST_ADDR_REG 0x1800 168 #define CQSPI_DMA_DST_SIZE_REG 0x1804 169 #define CQSPI_DMA_DST_STS_REG 0x1808 170 #define CQSPI_DMA_DST_CTRL_REG 0x180C 171 #define CQSPI_DMA_DST_I_STS_REG 0x1814 172 #define CQSPI_DMA_DST_I_ENBL_REG 0x1818 173 #define CQSPI_DMA_DST_I_DISBL_REG 0x181C 174 #define CQSPI_DMA_DST_CTRL2_REG 0x1824 175 #define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828 176 177 #define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000 178 179 #define CQSPI_REG_DMA_PERIPH_CFG 0x20 180 #define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80 181 #define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6 182 #define CQSPI_DFLT_DMA_PERIPH_CFG 0x602 183 #define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00 184 185 #define CQSPI_DMA_DST_I_STS_DONE BIT(1) 186 #define CQSPI_DMA_TIMEOUT 10000000 187 188 #define CQSPI_REG_IS_IDLE(base) \ 189 ((readl((base) + CQSPI_REG_CONFIG) >> \ 190 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) 191 192 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ 193 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ 194 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) 195 196 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ 197 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ 198 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) 199 200 struct cadence_spi_plat { 201 unsigned int max_hz; 202 void *regbase; 203 void *ahbbase; 204 bool is_decoded_cs; 205 u32 fifo_depth; 206 u32 fifo_width; 207 u32 trigger_address; 208 fdt_addr_t ahbsize; 209 bool use_dac_mode; 210 int read_delay; 211 212 /* Flash parameters */ 213 u32 page_size; 214 u32 block_size; 215 u32 tshsl_ns; 216 u32 tsd2d_ns; 217 u32 tchsh_ns; 218 u32 tslch_ns; 219 220 bool is_dma; 221 }; 222 223 struct cadence_spi_priv { 224 unsigned int ref_clk_hz; 225 unsigned int max_hz; 226 void *regbase; 227 void *ahbbase; 228 unsigned int fifo_depth; 229 unsigned int fifo_width; 230 unsigned int trigger_address; 231 fdt_addr_t ahbsize; 232 size_t cmd_len; 233 u8 cmd_buf[32]; 234 size_t data_len; 235 236 int qspi_is_init; 237 unsigned int qspi_calibrated_hz; 238 unsigned int qspi_calibrated_cs; 239 unsigned int previous_hz; 240 u32 wr_delay; 241 int read_delay; 242 243 struct reset_ctl_bulk *resets; 244 u32 page_size; 245 u32 block_size; 246 u32 tshsl_ns; 247 u32 tsd2d_ns; 248 u32 tchsh_ns; 249 u32 tslch_ns; 250 u8 edge_mode; 251 u8 dll_mode; 252 bool extra_dummy; 253 bool ddr_init; 254 bool is_decoded_cs; 255 bool use_dac_mode; 256 bool is_dma; 257 258 /* Transaction protocol parameters. */ 259 u8 inst_width; 260 u8 addr_width; 261 u8 data_width; 262 bool dtr; 263 }; 264 265 /* Functions call declaration */ 266 void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv); 267 void cadence_qspi_apb_controller_enable(void *reg_base_addr); 268 void cadence_qspi_apb_controller_disable(void *reg_base_addr); 269 void cadence_qspi_apb_dac_mode_enable(void *reg_base); 270 271 int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv, 272 const struct spi_mem_op *op); 273 int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, 274 const struct spi_mem_op *op); 275 int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv, 276 const struct spi_mem_op *op); 277 int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, 278 const struct spi_mem_op *op); 279 280 int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, 281 const struct spi_mem_op *op); 282 int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv, 283 const struct spi_mem_op *op); 284 int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, 285 const struct spi_mem_op *op); 286 int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv, 287 const struct spi_mem_op *op); 288 289 void cadence_qspi_apb_chipselect(void *reg_base, 290 unsigned int chip_select, unsigned int decoder_enable); 291 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); 292 void cadence_qspi_apb_config_baudrate_div(void *reg_base, 293 unsigned int ref_clk_hz, unsigned int sclk_hz); 294 void cadence_qspi_apb_delay(void *reg_base, 295 unsigned int ref_clk, unsigned int sclk_hz, 296 unsigned int tshsl_ns, unsigned int tsd2d_ns, 297 unsigned int tchsh_ns, unsigned int tslch_ns); 298 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); 299 void cadence_qspi_apb_readdata_capture(void *reg_base, 300 unsigned int bypass, unsigned int delay); 301 unsigned int cm_get_qspi_controller_clk_hz(void); 302 int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, 303 const struct spi_mem_op *op); 304 int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); 305 int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); 306 int cadence_qspi_versal_flash_reset(struct udevice *dev); 307 void cadence_qspi_apb_enable_linear_mode(bool enable); 308 309 #endif /* __CADENCE_QSPI_H__ */ 310