1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Qualcomm APQ8016, APQ8096, SDM845 4 * 5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 6 */ 7 #ifndef _CLOCK_SNAPDRAGON_H 8 #define _CLOCK_SNAPDRAGON_H 9 10 #define CFG_CLK_SRC_CXO (0 << 8) 11 #define CFG_CLK_SRC_GPLL0 (1 << 8) 12 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) 13 #define CFG_CLK_SRC_MASK (7 << 8) 14 15 struct pll_vote_clk { 16 uintptr_t status; 17 int status_bit; 18 uintptr_t ena_vote; 19 int vote_bit; 20 }; 21 22 struct vote_clk { 23 uintptr_t cbcr_reg; 24 uintptr_t ena_vote; 25 int vote_bit; 26 }; 27 struct bcr_regs { 28 uintptr_t cfg_rcgr; 29 uintptr_t cmd_rcgr; 30 uintptr_t M; 31 uintptr_t N; 32 uintptr_t D; 33 }; 34 35 struct msm_clk_priv { 36 phys_addr_t base; 37 }; 38 39 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); 40 void clk_bcr_update(phys_addr_t apps_cmd_rgcr); 41 void clk_enable_cbc(phys_addr_t cbcr); 42 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); 43 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, 44 int div, int m, int n, int source); 45 void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, 46 int source); 47 48 #endif 49