1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 */
11
12 #include <common.h>
13 #include <bloblist.h>
14 #include <bootstage.h>
15 #include <clock_legacy.h>
16 #include <console.h>
17 #include <cpu.h>
18 #include <cpu_func.h>
19 #include <cyclic.h>
20 #include <display_options.h>
21 #include <dm.h>
22 #include <env.h>
23 #include <env_internal.h>
24 #include <event.h>
25 #include <fdtdec.h>
26 #include <fs.h>
27 #include <hang.h>
28 #include <i2c.h>
29 #include <init.h>
30 #include <initcall.h>
31 #include <log.h>
32 #include <malloc.h>
33 #include <mapmem.h>
34 #include <os.h>
35 #include <post.h>
36 #include <relocate.h>
37 #include <serial.h>
38 #include <spl.h>
39 #include <status_led.h>
40 #include <sysreset.h>
41 #include <timer.h>
42 #include <trace.h>
43 #include <video.h>
44 #include <watchdog.h>
45 #include <asm/cache.h>
46 #include <asm/global_data.h>
47 #include <asm/io.h>
48 #include <asm/sections.h>
49 #include <dm/root.h>
50 #include <linux/errno.h>
51 #include <linux/log2.h>
52
53 DECLARE_GLOBAL_DATA_PTR;
54
55 /*
56 * TODO(sjg@chromium.org): IMO this code should be
57 * refactored to a single function, something like:
58 *
59 * void led_set_state(enum led_colour_t colour, int on);
60 */
61 /************************************************************************
62 * Coloured LED functionality
63 ************************************************************************
64 * May be supplied by boards if desired
65 */
coloured_LED_init(void)66 __weak void coloured_LED_init(void) {}
red_led_on(void)67 __weak void red_led_on(void) {}
red_led_off(void)68 __weak void red_led_off(void) {}
green_led_on(void)69 __weak void green_led_on(void) {}
green_led_off(void)70 __weak void green_led_off(void) {}
yellow_led_on(void)71 __weak void yellow_led_on(void) {}
yellow_led_off(void)72 __weak void yellow_led_off(void) {}
blue_led_on(void)73 __weak void blue_led_on(void) {}
blue_led_off(void)74 __weak void blue_led_off(void) {}
75
76 /*
77 * Why is gd allocated a register? Prior to reloc it might be better to
78 * just pass it around to each function in this file?
79 *
80 * After reloc one could argue that it is hardly used and doesn't need
81 * to be in a register. Or if it is it should perhaps hold pointers to all
82 * global data for all modules, so that post-reloc we can avoid the massive
83 * literal pool we get on ARM. Or perhaps just encourage each module to use
84 * a structure...
85 */
86
87 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
init_func_watchdog_init(void)88 static int init_func_watchdog_init(void)
89 {
90 # if defined(CONFIG_HW_WATCHDOG) && \
91 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
92 defined(CONFIG_SH) || \
93 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
94 defined(CONFIG_IMX_WATCHDOG))
95 hw_watchdog_init();
96 puts(" Watchdog enabled\n");
97 # endif
98 schedule();
99
100 return 0;
101 }
102
init_func_watchdog_reset(void)103 int init_func_watchdog_reset(void)
104 {
105 schedule();
106
107 return 0;
108 }
109 #endif /* CONFIG_WATCHDOG */
110
board_add_ram_info(int use_default)111 __weak void board_add_ram_info(int use_default)
112 {
113 /* please define platform specific board_add_ram_info() */
114 }
115
init_baud_rate(void)116 static int init_baud_rate(void)
117 {
118 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
119 return 0;
120 }
121
display_text_info(void)122 static int display_text_info(void)
123 {
124 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
125 ulong bss_start, bss_end, text_base;
126
127 bss_start = (ulong)&__bss_start;
128 bss_end = (ulong)&__bss_end;
129
130 #ifdef CONFIG_TEXT_BASE
131 text_base = CONFIG_TEXT_BASE;
132 #else
133 text_base = CONFIG_SYS_MONITOR_BASE;
134 #endif
135
136 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
137 text_base, bss_start, bss_end);
138 #endif
139
140 return 0;
141 }
142
143 #ifdef CONFIG_SYSRESET
print_resetinfo(void)144 static int print_resetinfo(void)
145 {
146 struct udevice *dev;
147 char status[256];
148 bool status_printed = false;
149 int ret;
150
151 /* Not all boards have sysreset drivers available during early
152 * boot, so don't fail if one can't be found.
153 */
154 for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev;
155 ret = uclass_next_device_check(&dev)) {
156 if (ret) {
157 debug("%s: %s sysreset device (error: %d)\n",
158 __func__, dev->name, ret);
159 continue;
160 }
161
162 if (!sysreset_get_status(dev, status, sizeof(status))) {
163 printf("%s%s", status_printed ? " " : "", status);
164 status_printed = true;
165 }
166 }
167 if (status_printed)
168 printf("\n");
169
170 return 0;
171 }
172 #endif
173
174 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
print_cpuinfo(void)175 static int print_cpuinfo(void)
176 {
177 struct udevice *dev;
178 char desc[512];
179 int ret;
180
181 dev = cpu_get_current_dev();
182 if (!dev) {
183 debug("%s: Could not get CPU device\n",
184 __func__);
185 return -ENODEV;
186 }
187
188 ret = cpu_get_desc(dev, desc, sizeof(desc));
189 if (ret) {
190 debug("%s: Could not get CPU description (err = %d)\n",
191 dev->name, ret);
192 return ret;
193 }
194
195 printf("CPU: %s\n", desc);
196
197 return 0;
198 }
199 #endif
200
announce_dram_init(void)201 static int announce_dram_init(void)
202 {
203 puts("DRAM: ");
204 return 0;
205 }
206
207 /*
208 * From input size calculate its nearest rounded unit scale (multiply of 2^10)
209 * and value in calculated unit scale multiplied by 10 (as fractional fixed
210 * point number with one decimal digit), which is human natural format,
211 * same what uses print_size() function for displaying. Mathematically it is:
212 * round_nearest(val * 2^scale) = size * 10; where: 10 <= val < 10240.
213 *
214 * For example for size=87654321 we calculate scale=20 and val=836 which means
215 * that input has natural human format 83.6 M (mega = 2^20).
216 */
217 #define compute_size_scale_val(size, scale, val) do { \
218 scale = ilog2(size) / 10 * 10; \
219 val = (10 * size + ((1ULL << scale) >> 1)) >> scale; \
220 if (val == 10240) { val = 10; scale += 10; } \
221 } while (0)
222
223 /*
224 * Check if the sizes in their natural units written in decimal format with
225 * one fraction number are same.
226 */
sizes_near(unsigned long long size1,unsigned long long size2)227 static int sizes_near(unsigned long long size1, unsigned long long size2)
228 {
229 unsigned int size1_scale, size1_val, size2_scale, size2_val;
230
231 compute_size_scale_val(size1, size1_scale, size1_val);
232 compute_size_scale_val(size2, size2_scale, size2_val);
233
234 return size1_scale == size2_scale && size1_val == size2_val;
235 }
236
show_dram_config(void)237 static int show_dram_config(void)
238 {
239 unsigned long long size;
240 int i;
241
242 debug("\nRAM Configuration:\n");
243 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
244 size += gd->bd->bi_dram[i].size;
245 debug("Bank #%d: %llx ", i,
246 (unsigned long long)(gd->bd->bi_dram[i].start));
247 #ifdef DEBUG
248 print_size(gd->bd->bi_dram[i].size, "\n");
249 #endif
250 }
251 debug("\nDRAM: ");
252
253 print_size(gd->ram_size, "");
254 if (!sizes_near(gd->ram_size, size)) {
255 printf(" (effective ");
256 print_size(size, ")");
257 }
258 board_add_ram_info(0);
259 putc('\n');
260
261 return 0;
262 }
263
dram_init_banksize(void)264 __weak int dram_init_banksize(void)
265 {
266 gd->bd->bi_dram[0].start = gd->ram_base;
267 gd->bd->bi_dram[0].size = get_effective_memsize();
268
269 return 0;
270 }
271
272 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
init_func_i2c(void)273 static int init_func_i2c(void)
274 {
275 puts("I2C: ");
276 i2c_init_all();
277 puts("ready\n");
278 return 0;
279 }
280 #endif
281
282 #if defined(CONFIG_VID)
init_func_vid(void)283 __weak int init_func_vid(void)
284 {
285 return 0;
286 }
287 #endif
288
setup_mon_len(void)289 static int setup_mon_len(void)
290 {
291 #if defined(__ARM__) || defined(__MICROBLAZE__)
292 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
293 #elif defined(CONFIG_SANDBOX) && !defined(__riscv)
294 gd->mon_len = (ulong)&_end - (ulong)_init;
295 #elif defined(CONFIG_SANDBOX)
296 /* gcc does not provide _init in crti.o on RISC-V */
297 gd->mon_len = 0;
298 #elif defined(CONFIG_EFI_APP)
299 gd->mon_len = (ulong)&_end - (ulong)_init;
300 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
301 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
302 #elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
303 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
304 #elif defined(CONFIG_SYS_MONITOR_BASE)
305 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
306 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
307 #endif
308 return 0;
309 }
310
setup_spl_handoff(void)311 static int setup_spl_handoff(void)
312 {
313 #if CONFIG_IS_ENABLED(HANDOFF)
314 gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
315 sizeof(struct spl_handoff));
316 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
317 #endif
318
319 return 0;
320 }
321
arch_cpu_init(void)322 __weak int arch_cpu_init(void)
323 {
324 return 0;
325 }
326
mach_cpu_init(void)327 __weak int mach_cpu_init(void)
328 {
329 return 0;
330 }
331
332 /* Get the top of usable RAM */
board_get_usable_ram_top(phys_size_t total_size)333 __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
334 {
335 #if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
336 /*
337 * Detect whether we have so much RAM that it goes past the end of our
338 * 32-bit address space. If so, clip the usable RAM so it doesn't.
339 */
340 if (gd->ram_top < CFG_SYS_SDRAM_BASE)
341 /*
342 * Will wrap back to top of 32-bit space when reservations
343 * are made.
344 */
345 return 0;
346 #endif
347 return gd->ram_top;
348 }
349
arch_setup_dest_addr(void)350 __weak int arch_setup_dest_addr(void)
351 {
352 return 0;
353 }
354
setup_dest_addr(void)355 static int setup_dest_addr(void)
356 {
357 debug("Monitor len: %08lX\n", gd->mon_len);
358 /*
359 * Ram is setup, size stored in gd !!
360 */
361 debug("Ram size: %08llX\n", (unsigned long long)gd->ram_size);
362 #if CONFIG_VAL(SYS_MEM_TOP_HIDE)
363 /*
364 * Subtract specified amount of memory to hide so that it won't
365 * get "touched" at all by U-Boot. By fixing up gd->ram_size
366 * the Linux kernel should now get passed the now "corrected"
367 * memory size and won't touch it either. This should work
368 * for arch/ppc and arch/powerpc. Only Linux board ports in
369 * arch/powerpc with bootwrapper support, that recalculate the
370 * memory size from the SDRAM controller setup will have to
371 * get fixed.
372 */
373 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
374 #endif
375 #ifdef CFG_SYS_SDRAM_BASE
376 gd->ram_base = CFG_SYS_SDRAM_BASE;
377 #endif
378 gd->ram_top = gd->ram_base + get_effective_memsize();
379 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
380 gd->relocaddr = gd->ram_top;
381 debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top);
382
383 return arch_setup_dest_addr();
384 }
385
386 #ifdef CFG_PRAM
387 /* reserve protected RAM */
reserve_pram(void)388 static int reserve_pram(void)
389 {
390 ulong reg;
391
392 reg = env_get_ulong("pram", 10, CFG_PRAM);
393 gd->relocaddr -= (reg << 10); /* size is in kB */
394 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
395 gd->relocaddr);
396 return 0;
397 }
398 #endif /* CFG_PRAM */
399
400 /* Round memory pointer down to next 4 kB limit */
reserve_round_4k(void)401 static int reserve_round_4k(void)
402 {
403 gd->relocaddr &= ~(4096 - 1);
404 return 0;
405 }
406
arch_reserve_mmu(void)407 __weak int arch_reserve_mmu(void)
408 {
409 return 0;
410 }
411
reserve_video(void)412 static int reserve_video(void)
413 {
414 if (IS_ENABLED(CONFIG_VIDEO)) {
415 ulong addr;
416 int ret;
417
418 addr = gd->relocaddr;
419 ret = video_reserve(&addr);
420 if (ret)
421 return ret;
422 debug("Reserving %luk for video at: %08lx\n",
423 ((unsigned long)gd->relocaddr - addr) >> 10, addr);
424 gd->relocaddr = addr;
425 }
426
427 return 0;
428 }
429
reserve_trace(void)430 static int reserve_trace(void)
431 {
432 #ifdef CONFIG_TRACE
433 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
434 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
435 debug("Reserving %luk for trace data at: %08lx\n",
436 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
437 #endif
438
439 return 0;
440 }
441
reserve_uboot(void)442 static int reserve_uboot(void)
443 {
444 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
445 /*
446 * reserve memory for U-Boot code, data & bss
447 * round down to next 4 kB limit
448 */
449 gd->relocaddr -= gd->mon_len;
450 gd->relocaddr &= ~(4096 - 1);
451 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
452 /* round down to next 64 kB limit so that IVPR stays aligned */
453 gd->relocaddr &= ~(65536 - 1);
454 #endif
455
456 debug("Reserving %ldk for U-Boot at: %08lx\n",
457 gd->mon_len >> 10, gd->relocaddr);
458 }
459
460 gd->start_addr_sp = gd->relocaddr;
461
462 return 0;
463 }
464
465 /*
466 * reserve after start_addr_sp the requested size and make the stack pointer
467 * 16-byte aligned, this alignment is needed for cast on the reserved memory
468 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
469 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
470 */
reserve_stack_aligned(size_t size)471 static unsigned long reserve_stack_aligned(size_t size)
472 {
473 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
474 }
475
476 #ifdef CONFIG_SYS_NONCACHED_MEMORY
reserve_noncached(void)477 static int reserve_noncached(void)
478 {
479 /*
480 * The value of gd->start_addr_sp must match the value of malloc_start
481 * calculated in board_r.c:initr_malloc(), which is passed to
482 * dlmalloc.c:mem_malloc_init() and then used by
483 * cache.c:noncached_init()
484 *
485 * These calculations must match the code in cache.c:noncached_init()
486 */
487 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
488 MMU_SECTION_SIZE;
489 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
490 MMU_SECTION_SIZE);
491 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
492 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
493
494 return 0;
495 }
496 #endif
497
498 /* reserve memory for malloc() area */
reserve_malloc(void)499 static int reserve_malloc(void)
500 {
501 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
502 debug("Reserving %dk for malloc() at: %08lx\n",
503 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
504 #ifdef CONFIG_SYS_NONCACHED_MEMORY
505 reserve_noncached();
506 #endif
507
508 return 0;
509 }
510
511 /* (permanently) allocate a Board Info struct */
reserve_board(void)512 static int reserve_board(void)
513 {
514 if (!gd->bd) {
515 gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
516 gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
517 sizeof(struct bd_info));
518 memset(gd->bd, '\0', sizeof(struct bd_info));
519 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
520 sizeof(struct bd_info), gd->start_addr_sp);
521 }
522 return 0;
523 }
524
reserve_global_data(void)525 static int reserve_global_data(void)
526 {
527 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
528 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
529 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
530 sizeof(gd_t), gd->start_addr_sp);
531 return 0;
532 }
533
reserve_fdt(void)534 static int reserve_fdt(void)
535 {
536 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
537 /*
538 * If the device tree is sitting immediately above our image
539 * then we must relocate it. If it is embedded in the data
540 * section, then it will be relocated with other data.
541 */
542 if (gd->fdt_blob) {
543 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
544
545 gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
546 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
547 debug("Reserving %lu Bytes for FDT at: %08lx\n",
548 gd->fdt_size, gd->start_addr_sp);
549 }
550 }
551
552 return 0;
553 }
554
reserve_bootstage(void)555 static int reserve_bootstage(void)
556 {
557 #ifdef CONFIG_BOOTSTAGE
558 int size = bootstage_get_size();
559
560 gd->start_addr_sp = reserve_stack_aligned(size);
561 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
562 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
563 gd->start_addr_sp);
564 #endif
565
566 return 0;
567 }
568
arch_reserve_stacks(void)569 __weak int arch_reserve_stacks(void)
570 {
571 return 0;
572 }
573
reserve_stacks(void)574 static int reserve_stacks(void)
575 {
576 /* make stack pointer 16-byte aligned */
577 gd->start_addr_sp = reserve_stack_aligned(16);
578
579 /*
580 * let the architecture-specific code tailor gd->start_addr_sp and
581 * gd->irq_sp
582 */
583 return arch_reserve_stacks();
584 }
585
reserve_bloblist(void)586 static int reserve_bloblist(void)
587 {
588 #ifdef CONFIG_BLOBLIST
589 /* Align to a 4KB boundary for easier reading of addresses */
590 gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
591 CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
592 gd->new_bloblist = map_sysmem(gd->start_addr_sp,
593 CONFIG_BLOBLIST_SIZE_RELOC);
594 #endif
595
596 return 0;
597 }
598
display_new_sp(void)599 static int display_new_sp(void)
600 {
601 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
602
603 return 0;
604 }
605
arch_setup_bdinfo(void)606 __weak int arch_setup_bdinfo(void)
607 {
608 return 0;
609 }
610
setup_bdinfo(void)611 int setup_bdinfo(void)
612 {
613 struct bd_info *bd = gd->bd;
614
615 if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
616 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
617 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
618 }
619
620 return arch_setup_bdinfo();
621 }
622
623 #ifdef CONFIG_POST
init_post(void)624 static int init_post(void)
625 {
626 post_bootmode_init();
627 post_run(NULL, POST_ROM | post_bootmode_get(0));
628
629 return 0;
630 }
631 #endif
632
reloc_fdt(void)633 static int reloc_fdt(void)
634 {
635 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
636 if (gd->flags & GD_FLG_SKIP_RELOC)
637 return 0;
638 if (gd->new_fdt) {
639 memcpy(gd->new_fdt, gd->fdt_blob,
640 fdt_totalsize(gd->fdt_blob));
641 gd->fdt_blob = gd->new_fdt;
642 }
643 }
644
645 return 0;
646 }
647
reloc_bootstage(void)648 static int reloc_bootstage(void)
649 {
650 #ifdef CONFIG_BOOTSTAGE
651 if (gd->flags & GD_FLG_SKIP_RELOC)
652 return 0;
653 if (gd->new_bootstage) {
654 int size = bootstage_get_size();
655
656 debug("Copying bootstage from %p to %p, size %x\n",
657 gd->bootstage, gd->new_bootstage, size);
658 memcpy(gd->new_bootstage, gd->bootstage, size);
659 gd->bootstage = gd->new_bootstage;
660 bootstage_relocate();
661 }
662 #endif
663
664 return 0;
665 }
666
reloc_bloblist(void)667 static int reloc_bloblist(void)
668 {
669 #ifdef CONFIG_BLOBLIST
670 /*
671 * Relocate only if we are supposed to send it
672 */
673 if ((gd->flags & GD_FLG_SKIP_RELOC) &&
674 CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
675 debug("Not relocating bloblist\n");
676 return 0;
677 }
678 if (gd->new_bloblist) {
679 int size = CONFIG_BLOBLIST_SIZE;
680
681 debug("Copying bloblist from %p to %p, size %x\n",
682 gd->bloblist, gd->new_bloblist, size);
683 bloblist_reloc(gd->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC,
684 gd->bloblist, size);
685 gd->bloblist = gd->new_bloblist;
686 }
687 #endif
688
689 return 0;
690 }
691
setup_reloc(void)692 static int setup_reloc(void)
693 {
694 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
695 #ifdef CONFIG_TEXT_BASE
696 #ifdef ARM
697 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
698 #elif defined(CONFIG_MICROBLAZE)
699 gd->reloc_off = gd->relocaddr - (u32)_start;
700 #elif defined(CONFIG_M68K)
701 /*
702 * On all ColdFire arch cpu, monitor code starts always
703 * just after the default vector table location, so at 0x400
704 */
705 gd->reloc_off = gd->relocaddr - (CONFIG_TEXT_BASE + 0x400);
706 #elif !defined(CONFIG_SANDBOX)
707 gd->reloc_off = gd->relocaddr - CONFIG_TEXT_BASE;
708 #endif
709 #endif
710 }
711
712 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
713
714 if (gd->flags & GD_FLG_SKIP_RELOC) {
715 debug("Skipping relocation due to flag\n");
716 } else {
717 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
718 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
719 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
720 gd->start_addr_sp);
721 }
722
723 return 0;
724 }
725
726 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt(void)727 static int fix_fdt(void)
728 {
729 return board_fix_fdt((void *)gd->fdt_blob);
730 }
731 #endif
732
733 /* ARM calls relocate_code from its crt0.S */
734 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
735 !CONFIG_IS_ENABLED(X86_64)
736
jump_to_copy(void)737 static int jump_to_copy(void)
738 {
739 if (gd->flags & GD_FLG_SKIP_RELOC)
740 return 0;
741 /*
742 * x86 is special, but in a nice way. It uses a trampoline which
743 * enables the dcache if possible.
744 *
745 * For now, other archs use relocate_code(), which is implemented
746 * similarly for all archs. When we do generic relocation, hopefully
747 * we can make all archs enable the dcache prior to relocation.
748 */
749 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
750 /*
751 * SDRAM and console are now initialised. The final stack can now
752 * be setup in SDRAM. Code execution will continue in Flash, but
753 * with the stack in SDRAM and Global Data in temporary memory
754 * (CPU cache)
755 */
756 arch_setup_gd(gd->new_gd);
757 board_init_f_r_trampoline(gd->start_addr_sp);
758 #else
759 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
760 #endif
761
762 return 0;
763 }
764 #endif
765
766 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
initf_bootstage(void)767 static int initf_bootstage(void)
768 {
769 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
770 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
771 int ret;
772
773 ret = bootstage_init(!from_spl);
774 if (ret)
775 return ret;
776 if (from_spl) {
777 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
778 CONFIG_BOOTSTAGE_STASH_SIZE);
779
780 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
781 if (ret && ret != -ENOENT) {
782 debug("Failed to unstash bootstage: err=%d\n", ret);
783 return ret;
784 }
785 }
786
787 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
788
789 return 0;
790 }
791
initf_dm(void)792 static int initf_dm(void)
793 {
794 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
795 int ret;
796
797 bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
798 ret = dm_init_and_scan(true);
799 bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
800 if (ret)
801 return ret;
802
803 if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
804 ret = dm_timer_init();
805 if (ret)
806 return ret;
807 }
808 #endif
809
810 return 0;
811 }
812
813 /* Architecture-specific memory reservation */
reserve_arch(void)814 __weak int reserve_arch(void)
815 {
816 return 0;
817 }
818
checkcpu(void)819 __weak int checkcpu(void)
820 {
821 return 0;
822 }
823
clear_bss(void)824 __weak int clear_bss(void)
825 {
826 return 0;
827 }
828
misc_init_f(void)829 static int misc_init_f(void)
830 {
831 return event_notify_null(EVT_MISC_INIT_F);
832 }
833
834 static const init_fnc_t init_sequence_f[] = {
835 setup_mon_len,
836 #ifdef CONFIG_OF_CONTROL
837 fdtdec_setup,
838 #endif
839 #ifdef CONFIG_TRACE_EARLY
840 trace_early_init,
841 #endif
842 initf_malloc,
843 log_init,
844 initf_bootstage, /* uses its own timer, so does not need DM */
845 event_init,
846 #ifdef CONFIG_BLOBLIST
847 bloblist_init,
848 #endif
849 setup_spl_handoff,
850 #if defined(CONFIG_CONSOLE_RECORD_INIT_F)
851 console_record_init,
852 #endif
853 #if defined(CONFIG_HAVE_FSP)
854 arch_fsp_init,
855 #endif
856 arch_cpu_init, /* basic arch cpu dependent setup */
857 mach_cpu_init, /* SoC/machine dependent CPU setup */
858 initf_dm,
859 #if defined(CONFIG_BOARD_EARLY_INIT_F)
860 board_early_init_f,
861 #endif
862 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
863 /* get CPU and bus clocks according to the environment variable */
864 get_clocks, /* get CPU and bus clocks (etc.) */
865 #endif
866 #if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR))
867 timer_init, /* initialize timer */
868 #endif
869 #if defined(CONFIG_BOARD_POSTCLK_INIT)
870 board_postclk_init,
871 #endif
872 env_init, /* initialize environment */
873 init_baud_rate, /* initialze baudrate settings */
874 serial_init, /* serial communications setup */
875 console_init_f, /* stage 1 init of console */
876 display_options, /* say that we are here */
877 display_text_info, /* show debugging info if required */
878 checkcpu,
879 #if defined(CONFIG_SYSRESET)
880 print_resetinfo,
881 #endif
882 #if defined(CONFIG_DISPLAY_CPUINFO)
883 print_cpuinfo, /* display cpu info (and speed) */
884 #endif
885 #if defined(CONFIG_DTB_RESELECT)
886 embedded_dtb_select,
887 #endif
888 #if defined(CONFIG_DISPLAY_BOARDINFO)
889 show_board_info,
890 #endif
891 INIT_FUNC_WATCHDOG_INIT
892 misc_init_f,
893 INIT_FUNC_WATCHDOG_RESET
894 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
895 init_func_i2c,
896 #endif
897 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
898 init_func_vid,
899 #endif
900 announce_dram_init,
901 dram_init, /* configure available RAM banks */
902 #ifdef CONFIG_POST
903 post_init_f,
904 #endif
905 INIT_FUNC_WATCHDOG_RESET
906 #if defined(CFG_SYS_DRAM_TEST)
907 testdram,
908 #endif /* CFG_SYS_DRAM_TEST */
909 INIT_FUNC_WATCHDOG_RESET
910
911 #ifdef CONFIG_POST
912 init_post,
913 #endif
914 INIT_FUNC_WATCHDOG_RESET
915 /*
916 * Now that we have DRAM mapped and working, we can
917 * relocate the code and continue running from DRAM.
918 *
919 * Reserve memory at end of RAM for (top down in that order):
920 * - area that won't get touched by U-Boot and Linux (optional)
921 * - kernel log buffer
922 * - protected RAM
923 * - LCD framebuffer
924 * - monitor code
925 * - board info struct
926 */
927 setup_dest_addr,
928 #ifdef CONFIG_OF_BOARD_FIXUP
929 fix_fdt,
930 #endif
931 #ifdef CFG_PRAM
932 reserve_pram,
933 #endif
934 reserve_round_4k,
935 arch_reserve_mmu,
936 reserve_video,
937 reserve_trace,
938 reserve_uboot,
939 reserve_malloc,
940 reserve_board,
941 reserve_global_data,
942 reserve_fdt,
943 reserve_bootstage,
944 reserve_bloblist,
945 reserve_arch,
946 reserve_stacks,
947 dram_init_banksize,
948 show_dram_config,
949 INIT_FUNC_WATCHDOG_RESET
950 setup_bdinfo,
951 display_new_sp,
952 INIT_FUNC_WATCHDOG_RESET
953 reloc_fdt,
954 reloc_bootstage,
955 reloc_bloblist,
956 setup_reloc,
957 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
958 copy_uboot_to_ram,
959 do_elf_reloc_fixups,
960 #endif
961 clear_bss,
962 /*
963 * Deregister all cyclic functions before relocation, so that
964 * gd->cyclic_list does not contain any references to pre-relocation
965 * devices. Drivers will register their cyclic functions anew when the
966 * devices are probed again.
967 *
968 * This should happen as late as possible so that the window where a
969 * watchdog device is not serviced is as small as possible.
970 */
971 cyclic_unregister_all,
972 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
973 !CONFIG_IS_ENABLED(X86_64)
974 jump_to_copy,
975 #endif
976 NULL,
977 };
978
board_init_f(ulong boot_flags)979 void board_init_f(ulong boot_flags)
980 {
981 gd->flags = boot_flags;
982 gd->have_console = 0;
983
984 if (initcall_run_list(init_sequence_f))
985 hang();
986
987 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
988 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
989 !defined(CONFIG_ARC)
990 /* NOTREACHED - jump_to_copy() does not return */
991 hang();
992 #endif
993 }
994
995 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
996 /*
997 * For now this code is only used on x86.
998 *
999 * init_sequence_f_r is the list of init functions which are run when
1000 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1001 * The following limitations must be considered when implementing an
1002 * '_f_r' function:
1003 * - 'static' variables are read-only
1004 * - Global Data (gd->xxx) is read/write
1005 *
1006 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1007 * supported). It _should_, if possible, copy global data to RAM and
1008 * initialise the CPU caches (to speed up the relocation process)
1009 *
1010 * NOTE: At present only x86 uses this route, but it is intended that
1011 * all archs will move to this when generic relocation is implemented.
1012 */
1013 static const init_fnc_t init_sequence_f_r[] = {
1014 #if !CONFIG_IS_ENABLED(X86_64)
1015 init_cache_f_r,
1016 #endif
1017
1018 NULL,
1019 };
1020
board_init_f_r(void)1021 void board_init_f_r(void)
1022 {
1023 if (initcall_run_list(init_sequence_f_r))
1024 hang();
1025
1026 /*
1027 * The pre-relocation drivers may be using memory that has now gone
1028 * away. Mark serial as unavailable - this will fall back to the debug
1029 * UART if available.
1030 *
1031 * Do the same with log drivers since the memory may not be available.
1032 */
1033 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1034 #ifdef CONFIG_TIMER
1035 gd->timer = NULL;
1036 #endif
1037
1038 /*
1039 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1040 * Transfer execution from Flash to RAM by calculating the address
1041 * of the in-RAM copy of board_init_r() and calling it
1042 */
1043 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1044
1045 /* NOTREACHED - board_init_r() does not return */
1046 hang();
1047 }
1048 #endif /* CONFIG_X86 */
1049