1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 */ 5 6 #ifndef __CVMX_CONFIG_H__ 7 #define __CVMX_CONFIG_H__ 8 9 /************************* Config Specific Defines ************************/ 10 #define CVMX_LLM_NUM_PORTS 1 11 12 /**< PKO queues per port for interface 0 (ports 0-15) */ 13 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 14 15 /**< PKO queues per port for interface 1 (ports 16-31) */ 16 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 17 18 /**< PKO queues per port for interface 4 (AGL) */ 19 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4 1 20 21 /**< Limit on the number of PKO ports enabled for interface 0 */ 22 #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 23 24 /**< Limit on the number of PKO ports enabled for interface 1 */ 25 #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 26 27 /**< PKO queues per port for PCI (ports 32-35) */ 28 #define CVMX_PKO_QUEUES_PER_PORT_PCI 1 29 30 /**< PKO queues per port for Loop devices (ports 36-39) */ 31 #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 32 33 /**< PKO queues per port for SRIO0 devices (ports 40-41) */ 34 #define CVMX_PKO_QUEUES_PER_PORT_SRIO0 1 35 36 /**< PKO queues per port for SRIO1 devices (ports 42-43) */ 37 #define CVMX_PKO_QUEUES_PER_PORT_SRIO1 1 38 39 /************************* FPA allocation *********************************/ 40 /* Pool sizes in bytes, must be multiple of a cache line */ 41 #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) 42 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) 43 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) 44 #define CVMX_FPA_POOL_3_SIZE (2 * CVMX_CACHE_LINE_SIZE) 45 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) 46 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) 47 #define CVMX_FPA_POOL_6_SIZE (8 * CVMX_CACHE_LINE_SIZE) 48 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) 49 50 /* Pools in use */ 51 /**< Packet buffers */ 52 #define CVMX_FPA_PACKET_POOL (0) 53 #ifndef CVMX_FPA_PACKET_POOL_SIZE 54 #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE 55 #endif 56 57 /**< Work queue entries */ 58 #define CVMX_FPA_WQE_POOL (1) 59 #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE 60 61 /**< PKO queue command buffers */ 62 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2) 63 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE 64 65 /**< BCH queue command buffers */ 66 #define CVMX_FPA_BCH_POOL (6) 67 #define CVMX_FPA_BCH_POOL_SIZE CVMX_FPA_POOL6_SIZE 68 69 /************************* FAU allocation ********************************/ 70 /* The fetch and add registers are allocated here. They are arranged 71 * in order of descending size so that all alignment constraints are 72 * automatically met. 73 * The enums are linked so that the following enum continues allocating 74 * where the previous one left off, so the numbering within each 75 * enum always starts with zero. The macros take care of the address 76 * increment size, so the values entered always increase by 1. 77 * FAU registers are accessed with byte addresses. 78 */ 79 80 #define CVMX_FAU_REG_64_ADDR(x) (((x) << 3) + CVMX_FAU_REG_64_START) 81 typedef enum { 82 CVMX_FAU_REG_64_START = 0, 83 /**< FAU registers for the position in PKO command buffers */ 84 CVMX_FAU_REG_OQ_ADDR_INDEX = CVMX_FAU_REG_64_ADDR(0), 85 /* Array of 36 */ 86 CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(36), 87 } cvmx_fau_reg_64_t; 88 89 #define CVMX_FAU_REG_32_ADDR(x) (((x) << 2) + CVMX_FAU_REG_32_START) 90 typedef enum { 91 CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, 92 CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), 93 } cvmx_fau_reg_32_t; 94 95 #define CVMX_FAU_REG_16_ADDR(x) (((x) << 1) + CVMX_FAU_REG_16_START) 96 typedef enum { 97 CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, 98 CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), 99 } cvmx_fau_reg_16_t; 100 101 #define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) 102 typedef enum { 103 CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, 104 CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), 105 } cvmx_fau_reg_8_t; 106 107 /* The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first available 108 * FAU address that is not allocated in cvmx-config.h. This is 64 bit aligned. 109 */ 110 #define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) 111 #define CVMX_FAU_REG_END (2048) 112 113 /********************** scratch memory allocation *************************/ 114 /* Scratchpad memory allocation. Note that these are byte memory addresses. 115 * Some uses of scratchpad (IOBDMA for example) require the use of 8-byte 116 * aligned addresses, so proper alignment needs to be taken into account. 117 */ 118 119 /**< Pre allocation for PKO queue command buffers */ 120 #define CVMX_SCR_OQ_BUF_PRE_ALLOC (0) 121 122 /**< Generic scratch iobdma area */ 123 #define CVMX_SCR_SCRATCH (8) 124 125 /**< First location available after cvmx-config.h allocated region. */ 126 #define CVMX_SCR_REG_AVAIL_BASE (16) 127 128 #endif /* __CVMX_CONFIG_H__ */ 129