1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_DB_H_ 7 #define _DDR3_TRAINING_IP_DB_H_ 8 9 enum hws_pattern { 10 #if defined(CONFIG_DDR4) /* DDR4 16/32-bit */ 11 PATTERN_PBS1,/*0*/ 12 PATTERN_PBS2, 13 PATTERN_PBS3, 14 PATTERN_TEST, 15 PATTERN_RL, 16 PATTERN_RL2, 17 PATTERN_STATIC_PBS, 18 PATTERN_KILLER_DQ0, 19 PATTERN_KILLER_DQ1, 20 PATTERN_KILLER_DQ2, 21 PATTERN_KILLER_DQ3,/*10*/ 22 PATTERN_KILLER_DQ4, 23 PATTERN_KILLER_DQ5, 24 PATTERN_KILLER_DQ6, 25 PATTERN_KILLER_DQ7, 26 PATTERN_KILLER_DQ0_INV, 27 PATTERN_KILLER_DQ1_INV, 28 PATTERN_KILLER_DQ2_INV, 29 PATTERN_KILLER_DQ3_INV, 30 PATTERN_KILLER_DQ4_INV, 31 PATTERN_KILLER_DQ5_INV,/*20*/ 32 PATTERN_KILLER_DQ6_INV, 33 PATTERN_KILLER_DQ7_INV, 34 PATTERN_VREF, 35 PATTERN_VREF_INV, 36 PATTERN_FULL_SSO0, 37 PATTERN_FULL_SSO1, 38 PATTERN_FULL_SSO2, 39 PATTERN_FULL_SSO3, 40 PATTERN_ZERO, 41 PATTERN_ONE, 42 PATTERN_LAST, 43 PATTERN_SSO_FULL_XTALK_DQ0, 44 PATTERN_SSO_FULL_XTALK_DQ1,/*30*/ 45 PATTERN_SSO_FULL_XTALK_DQ2, 46 PATTERN_SSO_FULL_XTALK_DQ3, 47 PATTERN_SSO_FULL_XTALK_DQ4, 48 PATTERN_SSO_FULL_XTALK_DQ5, 49 PATTERN_SSO_FULL_XTALK_DQ6, 50 PATTERN_SSO_FULL_XTALK_DQ7, 51 PATTERN_SSO_XTALK_FREE_DQ0, 52 PATTERN_SSO_XTALK_FREE_DQ1, 53 PATTERN_SSO_XTALK_FREE_DQ2, 54 PATTERN_SSO_XTALK_FREE_DQ3,/*40*/ 55 PATTERN_SSO_XTALK_FREE_DQ4, 56 PATTERN_SSO_XTALK_FREE_DQ5, 57 PATTERN_SSO_XTALK_FREE_DQ6, 58 PATTERN_SSO_XTALK_FREE_DQ7, 59 PATTERN_ISI_XTALK_FREE, 60 PATTERN_RESONANCE_1T, 61 PATTERN_RESONANCE_2T, 62 PATTERN_RESONANCE_3T, 63 PATTERN_RESONANCE_4T, 64 PATTERN_RESONANCE_5T,/*50*/ 65 PATTERN_RESONANCE_6T, 66 PATTERN_RESONANCE_7T, 67 PATTERN_RESONANCE_8T, 68 PATTERN_RESONANCE_9T 69 #else /* DDR3 16/32-bit */ 70 PATTERN_PBS1, 71 PATTERN_PBS2, 72 PATTERN_PBS3, 73 PATTERN_TEST, 74 PATTERN_RL, 75 PATTERN_RL2, 76 PATTERN_STATIC_PBS, 77 PATTERN_KILLER_DQ0, 78 PATTERN_KILLER_DQ1, 79 PATTERN_KILLER_DQ2, 80 PATTERN_KILLER_DQ3, 81 PATTERN_KILLER_DQ4, 82 PATTERN_KILLER_DQ5, 83 PATTERN_KILLER_DQ6, 84 PATTERN_KILLER_DQ7, 85 PATTERN_VREF, 86 PATTERN_FULL_SSO0, 87 PATTERN_FULL_SSO1, 88 PATTERN_FULL_SSO2, 89 PATTERN_FULL_SSO3, 90 PATTERN_LAST, 91 PATTERN_SSO_FULL_XTALK_DQ0, 92 PATTERN_SSO_FULL_XTALK_DQ1, 93 PATTERN_SSO_FULL_XTALK_DQ2, 94 PATTERN_SSO_FULL_XTALK_DQ3, 95 PATTERN_SSO_FULL_XTALK_DQ4, 96 PATTERN_SSO_FULL_XTALK_DQ5, 97 PATTERN_SSO_FULL_XTALK_DQ6, 98 PATTERN_SSO_FULL_XTALK_DQ7, 99 PATTERN_SSO_XTALK_FREE_DQ0, 100 PATTERN_SSO_XTALK_FREE_DQ1, 101 PATTERN_SSO_XTALK_FREE_DQ2, 102 PATTERN_SSO_XTALK_FREE_DQ3, 103 PATTERN_SSO_XTALK_FREE_DQ4, 104 PATTERN_SSO_XTALK_FREE_DQ5, 105 PATTERN_SSO_XTALK_FREE_DQ6, 106 PATTERN_SSO_XTALK_FREE_DQ7, 107 PATTERN_ISI_XTALK_FREE 108 #endif /* CONFIG_64BIT */ 109 }; 110 111 enum mv_wl_supp_mode { 112 WRITE_LEVELING_SUPP_REG_MODE, 113 WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS, 114 WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4, 115 WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3, 116 WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8 117 }; 118 119 enum mv_ddr_dev_attribute { 120 MV_ATTR_TIP_REV, 121 MV_ATTR_PHY_EDGE, 122 MV_ATTR_OCTET_PER_INTERFACE, 123 MV_ATTR_PLL_BEFORE_INIT, 124 MV_ATTR_TUNE_MASK, 125 MV_ATTR_INIT_FREQ, 126 MV_ATTR_MID_FREQ, 127 MV_ATTR_DFS_LOW_FREQ, 128 MV_ATTR_DFS_LOW_PHY, 129 MV_ATTR_DELAY_ENABLE, 130 MV_ATTR_CK_DELAY, 131 MV_ATTR_CA_DELAY, 132 MV_ATTR_INTERLEAVE_WA, 133 MV_ATTR_LAST 134 }; 135 136 enum mv_ddr_tip_revison { 137 MV_TIP_REV_NA, 138 MV_TIP_REV_1, /* NP5 */ 139 MV_TIP_REV_2, /* BC2 */ 140 MV_TIP_REV_3, /* AC3 */ 141 MV_TIP_REV_4, /* A-380/A-390 */ 142 MV_TIP_REV_LAST 143 }; 144 145 enum mv_ddr_phy_edge { 146 MV_DDR_PHY_EDGE_POSITIVE, 147 MV_DDR_PHY_EDGE_NEGATIVE 148 }; 149 150 /* Device attribute functions */ 151 void ddr3_tip_dev_attr_init(u32 dev_num); 152 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id); 153 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value); 154 155 #endif /* _DDR3_TRAINING_IP_DB_H_ */ 156