1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <linux/kernel.h>
11 #include <linux/bitops.h>
12 #include <linux/compiler.h>
13 #include <serial.h>
14 #include <clk.h>
15
16 struct meson_uart {
17 u32 wfifo;
18 u32 rfifo;
19 u32 control;
20 u32 status;
21 u32 misc;
22 u32 reg5; /* New baud control register */
23 };
24
25 struct meson_serial_plat {
26 struct meson_uart *reg;
27 };
28
29 /* AML_UART_STATUS bits */
30 #define AML_UART_PARITY_ERR BIT(16)
31 #define AML_UART_FRAME_ERR BIT(17)
32 #define AML_UART_TX_FIFO_WERR BIT(18)
33 #define AML_UART_RX_EMPTY BIT(20)
34 #define AML_UART_TX_FULL BIT(21)
35 #define AML_UART_TX_EMPTY BIT(22)
36 #define AML_UART_XMIT_BUSY BIT(25)
37 #define AML_UART_ERR (AML_UART_PARITY_ERR | \
38 AML_UART_FRAME_ERR | \
39 AML_UART_TX_FIFO_WERR)
40
41 /* AML_UART_CONTROL bits */
42 #define AML_UART_TX_EN BIT(12)
43 #define AML_UART_RX_EN BIT(13)
44 #define AML_UART_TX_RST BIT(22)
45 #define AML_UART_RX_RST BIT(23)
46 #define AML_UART_CLR_ERR BIT(24)
47
48 /* AML_UART_REG5 bits */
49 #define AML_UART_REG5_XTAL_DIV2 BIT(27)
50 #define AML_UART_REG5_XTAL_CLK_SEL BIT(26) /* default 0 (div by 3), 1 for no div */
51 #define AML_UART_REG5_USE_XTAL_CLK BIT(24) /* default 1 (use crystal as clock source) */
52 #define AML_UART_REG5_USE_NEW_BAUD BIT(23) /* default 1 (use new baud rate register) */
53 #define AML_UART_REG5_BAUD_MASK 0x7fffff
54
meson_calc_baud_divisor(ulong src_rate,u32 baud)55 static u32 meson_calc_baud_divisor(ulong src_rate, u32 baud)
56 {
57 /*
58 * Usually src_rate is 24 MHz (from crystal) as clock source for serial
59 * device. Since 8 Mb/s is the maximum supported baud rate, use div by 3
60 * to derive baud rate. This choice is used also in meson_serial_setbrg.
61 */
62 return DIV_ROUND_CLOSEST(src_rate / 3, baud) - 1;
63 }
64
meson_serial_set_baud(struct meson_uart * uart,ulong src_rate,u32 baud)65 static void meson_serial_set_baud(struct meson_uart *uart, ulong src_rate, u32 baud)
66 {
67 /*
68 * Set crystal divided by 3 (regardless of device tree clock property)
69 * as clock source and the corresponding divisor to approximate baud
70 */
71 u32 divisor = meson_calc_baud_divisor(src_rate, baud);
72 u32 val = AML_UART_REG5_USE_XTAL_CLK | AML_UART_REG5_USE_NEW_BAUD |
73 (divisor & AML_UART_REG5_BAUD_MASK);
74 writel(val, &uart->reg5);
75 }
76
meson_serial_init(struct meson_uart * uart)77 static void meson_serial_init(struct meson_uart *uart)
78 {
79 u32 val;
80
81 val = readl(&uart->control);
82 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
83 writel(val, &uart->control);
84 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
85 writel(val, &uart->control);
86 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
87 writel(val, &uart->control);
88 }
89
meson_serial_probe(struct udevice * dev)90 static int meson_serial_probe(struct udevice *dev)
91 {
92 struct meson_serial_plat *plat = dev_get_plat(dev);
93 struct meson_uart *const uart = plat->reg;
94 struct clk per_clk;
95 int ret = clk_get_by_name(dev, "baud", &per_clk);
96
97 if (ret)
98 return ret;
99 ulong rate = clk_get_rate(&per_clk);
100
101 meson_serial_set_baud(uart, rate, CONFIG_BAUDRATE);
102 meson_serial_init(uart);
103
104 return 0;
105 }
106
meson_serial_rx_error(struct udevice * dev)107 static void meson_serial_rx_error(struct udevice *dev)
108 {
109 struct meson_serial_plat *plat = dev_get_plat(dev);
110 struct meson_uart *const uart = plat->reg;
111 u32 val = readl(&uart->control);
112
113 /* Clear error */
114 val |= AML_UART_CLR_ERR;
115 writel(val, &uart->control);
116 val &= ~AML_UART_CLR_ERR;
117 writel(val, &uart->control);
118
119 /* Remove spurious byte from fifo */
120 readl(&uart->rfifo);
121 }
122
meson_serial_getc(struct udevice * dev)123 static int meson_serial_getc(struct udevice *dev)
124 {
125 struct meson_serial_plat *plat = dev_get_plat(dev);
126 struct meson_uart *const uart = plat->reg;
127 uint32_t status = readl(&uart->status);
128
129 if (status & AML_UART_RX_EMPTY)
130 return -EAGAIN;
131
132 if (status & AML_UART_ERR) {
133 meson_serial_rx_error(dev);
134 return -EIO;
135 }
136
137 return readl(&uart->rfifo) & 0xff;
138 }
139
meson_serial_putc(struct udevice * dev,const char ch)140 static int meson_serial_putc(struct udevice *dev, const char ch)
141 {
142 struct meson_serial_plat *plat = dev_get_plat(dev);
143 struct meson_uart *const uart = plat->reg;
144
145 if (readl(&uart->status) & AML_UART_TX_FULL)
146 return -EAGAIN;
147
148 writel(ch, &uart->wfifo);
149
150 return 0;
151 }
152
meson_serial_setbrg(struct udevice * dev,const int baud)153 static int meson_serial_setbrg(struct udevice *dev, const int baud)
154 {
155 /*
156 * Change device baud rate if baud is reasonable (considering a 23 bit
157 * counter with an 8 MHz clock input) and the actual baud
158 * rate is within 2% of the requested value (2% is arbitrary).
159 */
160 if (baud < 1 || baud > 8000000)
161 return -EINVAL;
162
163 struct meson_serial_plat *const plat = dev_get_plat(dev);
164 struct meson_uart *const uart = plat->reg;
165 struct clk per_clk;
166 int ret = clk_get_by_name(dev, "baud", &per_clk);
167
168 if (ret)
169 return ret;
170 ulong rate = clk_get_rate(&per_clk);
171 u32 divisor = meson_calc_baud_divisor(rate, baud);
172 u32 calc_baud = (rate / 3) / (divisor + 1);
173 u32 calc_err = baud > calc_baud ? baud - calc_baud : calc_baud - baud;
174
175 if (((calc_err * 100) / baud) > 2)
176 return -EINVAL;
177
178 meson_serial_set_baud(uart, rate, baud);
179
180 return 0;
181 }
182
meson_serial_pending(struct udevice * dev,bool input)183 static int meson_serial_pending(struct udevice *dev, bool input)
184 {
185 struct meson_serial_plat *plat = dev_get_plat(dev);
186 struct meson_uart *const uart = plat->reg;
187 uint32_t status = readl(&uart->status);
188
189 if (input) {
190 if (status & AML_UART_RX_EMPTY)
191 return false;
192
193 /*
194 * Handle and drop any RX error here to avoid
195 * returning true here when an error byte is in the FIFO
196 */
197 if (status & AML_UART_ERR) {
198 meson_serial_rx_error(dev);
199 return false;
200 }
201
202 return true;
203 } else {
204 if (status & AML_UART_TX_EMPTY)
205 return false;
206
207 return true;
208 }
209 }
210
meson_serial_of_to_plat(struct udevice * dev)211 static int meson_serial_of_to_plat(struct udevice *dev)
212 {
213 struct meson_serial_plat *plat = dev_get_plat(dev);
214 fdt_addr_t addr;
215
216 addr = dev_read_addr(dev);
217 if (addr == FDT_ADDR_T_NONE)
218 return -EINVAL;
219
220 plat->reg = (struct meson_uart *)addr;
221
222 return 0;
223 }
224
225 static const struct dm_serial_ops meson_serial_ops = {
226 .putc = meson_serial_putc,
227 .pending = meson_serial_pending,
228 .getc = meson_serial_getc,
229 .setbrg = meson_serial_setbrg,
230 };
231
232 static const struct udevice_id meson_serial_ids[] = {
233 { .compatible = "amlogic,meson-uart" },
234 { .compatible = "amlogic,meson-gx-uart" },
235 { }
236 };
237
238 U_BOOT_DRIVER(serial_meson) = {
239 .name = "serial_meson",
240 .id = UCLASS_SERIAL,
241 .of_match = meson_serial_ids,
242 .probe = meson_serial_probe,
243 .ops = &meson_serial_ops,
244 .of_to_plat = meson_serial_of_to_plat,
245 .plat_auto = sizeof(struct meson_serial_plat),
246 };
247
248 #ifdef CONFIG_DEBUG_UART_MESON
249
250 #include <debug_uart.h>
251
_debug_uart_init(void)252 static inline void _debug_uart_init(void)
253 {
254 }
255
_debug_uart_putc(int ch)256 static inline void _debug_uart_putc(int ch)
257 {
258 struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE);
259
260 while (readl(®s->status) & AML_UART_TX_FULL)
261 ;
262
263 writel(ch, ®s->wfifo);
264 }
265
266 DEBUG_UART_FUNCS
267
268 #endif
269