1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2022 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef LPDDR4_IF_H 10 #define LPDDR4_IF_H 11 12 #include <linux/types.h> 13 #ifdef CONFIG_K3_AM64_DDRSS 14 #include <lpddr4_am64_if.h> 15 #elif CONFIG_K3_AM62A_DDRSS 16 #include <lpddr4_am62a_if.h> 17 #else 18 #include <lpddr4_j721e_if.h> 19 #endif 20 21 typedef struct lpddr4_config_s lpddr4_config; 22 typedef struct lpddr4_privatedata_s lpddr4_privatedata; 23 typedef struct lpddr4_debuginfo_s lpddr4_debuginfo; 24 typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs; 25 26 typedef enum { 27 LPDDR4_CTL_REGS = 0U, 28 LPDDR4_PHY_REGS = 1U, 29 LPDDR4_PHY_INDEP_REGS = 2U 30 } lpddr4_regblock; 31 32 typedef enum { 33 LPDDR4_DRV_NONE = 0U, 34 LPDDR4_DRV_SOC_PLL_UPDATE = 1U 35 } lpddr4_infotype; 36 37 typedef enum { 38 LPDDR4_LPI_PD_WAKEUP_FN = 0U, 39 LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U, 40 LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U, 41 LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U, 42 LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U, 43 LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U, 44 LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U 45 } lpddr4_lpiwakeupparam; 46 47 typedef enum { 48 LPDDR4_REDUC_ON = 0U, 49 LPDDR4_REDUC_OFF = 1U 50 } lpddr4_reducmode; 51 52 typedef enum { 53 LPDDR4_ECC_DISABLED = 0U, 54 LPDDR4_ECC_ENABLED = 1U, 55 LPDDR4_ECC_ERR_DETECT = 2U, 56 LPDDR4_ECC_ERR_DETECT_CORRECT = 3U 57 } lpddr4_eccenable; 58 59 typedef enum { 60 LPDDR4_DBI_RD_ON = 0U, 61 LPDDR4_DBI_RD_OFF = 1U, 62 LPDDR4_DBI_WR_ON = 2U, 63 LPDDR4_DBI_WR_OFF = 3U 64 } lpddr4_dbimode; 65 66 typedef enum { 67 LPDDR4_FSP_0 = 0U, 68 LPDDR4_FSP_1 = 1U, 69 LPDDR4_FSP_2 = 2U 70 } lpddr4_ctlfspnum; 71 72 typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype); 73 74 typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect); 75 76 typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect); 77 78 u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize); 79 80 u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg); 81 82 u32 lpddr4_start(const lpddr4_privatedata *pd); 83 84 u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue); 85 86 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); 87 88 u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus); 89 90 u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus); 91 92 u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 93 94 u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 95 96 u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 97 98 u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 99 100 u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 101 102 u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 103 104 u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask); 105 106 u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask); 107 108 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus); 109 110 u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr); 111 112 u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask); 113 114 u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask); 115 116 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus); 117 118 u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr); 119 120 u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo); 121 122 u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); 123 124 u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); 125 126 u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam); 127 128 u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); 129 130 u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode); 131 132 u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); 133 134 u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off); 135 136 u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off); 137 138 u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); 139 140 u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max); 141 142 u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); 143 144 u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval); 145 146 u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount); 147 148 #endif /* LPDDR4_IF_H */ 149