1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon pcsxx. 7 */ 8 9 #ifndef __CVMX_PCSXX_DEFS_H__ 10 #define __CVMX_PCSXX_DEFS_H__ 11 CVMX_PCSXX_10GBX_STATUS_REG(unsigned long offset)12static inline u64 CVMX_PCSXX_10GBX_STATUS_REG(unsigned long offset) 13 { 14 switch (cvmx_get_octeon_family()) { 15 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 16 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 17 return 0x00011800B0000828ull + (offset) * 0x8000000ull; 18 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 19 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 20 return 0x00011800B0000828ull + (offset) * 0x8000000ull; 21 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 22 return 0x00011800B0000828ull + (offset) * 0x1000000ull; 23 } 24 return 0x00011800B0000828ull + (offset) * 0x8000000ull; 25 } 26 CVMX_PCSXX_BIST_STATUS_REG(unsigned long offset)27static inline u64 CVMX_PCSXX_BIST_STATUS_REG(unsigned long offset) 28 { 29 switch (cvmx_get_octeon_family()) { 30 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 31 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 32 return 0x00011800B0000870ull + (offset) * 0x8000000ull; 33 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 34 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 35 return 0x00011800B0000870ull + (offset) * 0x8000000ull; 36 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 37 return 0x00011800B0000870ull + (offset) * 0x1000000ull; 38 } 39 return 0x00011800B0000870ull + (offset) * 0x8000000ull; 40 } 41 CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long offset)42static inline u64 CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long offset) 43 { 44 switch (cvmx_get_octeon_family()) { 45 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 46 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 47 return 0x00011800B0000850ull + (offset) * 0x8000000ull; 48 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 49 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 50 return 0x00011800B0000850ull + (offset) * 0x8000000ull; 51 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 52 return 0x00011800B0000850ull + (offset) * 0x1000000ull; 53 } 54 return 0x00011800B0000850ull + (offset) * 0x8000000ull; 55 } 56 CVMX_PCSXX_CONTROL1_REG(unsigned long offset)57static inline u64 CVMX_PCSXX_CONTROL1_REG(unsigned long offset) 58 { 59 switch (cvmx_get_octeon_family()) { 60 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 61 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 62 return 0x00011800B0000800ull + (offset) * 0x8000000ull; 63 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 64 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 65 return 0x00011800B0000800ull + (offset) * 0x8000000ull; 66 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 67 return 0x00011800B0000800ull + (offset) * 0x1000000ull; 68 } 69 return 0x00011800B0000800ull + (offset) * 0x8000000ull; 70 } 71 CVMX_PCSXX_CONTROL2_REG(unsigned long offset)72static inline u64 CVMX_PCSXX_CONTROL2_REG(unsigned long offset) 73 { 74 switch (cvmx_get_octeon_family()) { 75 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 76 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 77 return 0x00011800B0000818ull + (offset) * 0x8000000ull; 78 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 79 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 80 return 0x00011800B0000818ull + (offset) * 0x8000000ull; 81 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 82 return 0x00011800B0000818ull + (offset) * 0x1000000ull; 83 } 84 return 0x00011800B0000818ull + (offset) * 0x8000000ull; 85 } 86 CVMX_PCSXX_INT_EN_REG(unsigned long offset)87static inline u64 CVMX_PCSXX_INT_EN_REG(unsigned long offset) 88 { 89 switch (cvmx_get_octeon_family()) { 90 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 91 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 92 return 0x00011800B0000860ull + (offset) * 0x8000000ull; 93 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 94 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 95 return 0x00011800B0000860ull + (offset) * 0x8000000ull; 96 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 97 return 0x00011800B0000860ull + (offset) * 0x1000000ull; 98 } 99 return 0x00011800B0000860ull + (offset) * 0x8000000ull; 100 } 101 CVMX_PCSXX_INT_REG(unsigned long offset)102static inline u64 CVMX_PCSXX_INT_REG(unsigned long offset) 103 { 104 switch (cvmx_get_octeon_family()) { 105 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 106 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 107 return 0x00011800B0000858ull + (offset) * 0x8000000ull; 108 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 109 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 110 return 0x00011800B0000858ull + (offset) * 0x8000000ull; 111 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 112 return 0x00011800B0000858ull + (offset) * 0x1000000ull; 113 } 114 return 0x00011800B0000858ull + (offset) * 0x8000000ull; 115 } 116 CVMX_PCSXX_LOG_ANL_REG(unsigned long offset)117static inline u64 CVMX_PCSXX_LOG_ANL_REG(unsigned long offset) 118 { 119 switch (cvmx_get_octeon_family()) { 120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 121 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 122 return 0x00011800B0000868ull + (offset) * 0x8000000ull; 123 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 124 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 125 return 0x00011800B0000868ull + (offset) * 0x8000000ull; 126 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 127 return 0x00011800B0000868ull + (offset) * 0x1000000ull; 128 } 129 return 0x00011800B0000868ull + (offset) * 0x8000000ull; 130 } 131 CVMX_PCSXX_MISC_CTL_REG(unsigned long offset)132static inline u64 CVMX_PCSXX_MISC_CTL_REG(unsigned long offset) 133 { 134 switch (cvmx_get_octeon_family()) { 135 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 136 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 137 return 0x00011800B0000848ull + (offset) * 0x8000000ull; 138 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 139 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 140 return 0x00011800B0000848ull + (offset) * 0x8000000ull; 141 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 142 return 0x00011800B0000848ull + (offset) * 0x1000000ull; 143 } 144 return 0x00011800B0000848ull + (offset) * 0x8000000ull; 145 } 146 CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long offset)147static inline u64 CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long offset) 148 { 149 switch (cvmx_get_octeon_family()) { 150 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 151 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 152 return 0x00011800B0000838ull + (offset) * 0x8000000ull; 153 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 154 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 155 return 0x00011800B0000838ull + (offset) * 0x8000000ull; 156 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 157 return 0x00011800B0000838ull + (offset) * 0x1000000ull; 158 } 159 return 0x00011800B0000838ull + (offset) * 0x8000000ull; 160 } 161 162 #define CVMX_PCSXX_SERDES_CRDT_CNT_REG(offset) (0x00011800B0000880ull) CVMX_PCSXX_SPD_ABIL_REG(unsigned long offset)163static inline u64 CVMX_PCSXX_SPD_ABIL_REG(unsigned long offset) 164 { 165 switch (cvmx_get_octeon_family()) { 166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 168 return 0x00011800B0000810ull + (offset) * 0x8000000ull; 169 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 170 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 171 return 0x00011800B0000810ull + (offset) * 0x8000000ull; 172 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 173 return 0x00011800B0000810ull + (offset) * 0x1000000ull; 174 } 175 return 0x00011800B0000810ull + (offset) * 0x8000000ull; 176 } 177 CVMX_PCSXX_STATUS1_REG(unsigned long offset)178static inline u64 CVMX_PCSXX_STATUS1_REG(unsigned long offset) 179 { 180 switch (cvmx_get_octeon_family()) { 181 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 182 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 183 return 0x00011800B0000808ull + (offset) * 0x8000000ull; 184 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 185 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 186 return 0x00011800B0000808ull + (offset) * 0x8000000ull; 187 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 188 return 0x00011800B0000808ull + (offset) * 0x1000000ull; 189 } 190 return 0x00011800B0000808ull + (offset) * 0x8000000ull; 191 } 192 CVMX_PCSXX_STATUS2_REG(unsigned long offset)193static inline u64 CVMX_PCSXX_STATUS2_REG(unsigned long offset) 194 { 195 switch (cvmx_get_octeon_family()) { 196 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 197 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 198 return 0x00011800B0000820ull + (offset) * 0x8000000ull; 199 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 200 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 201 return 0x00011800B0000820ull + (offset) * 0x8000000ull; 202 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 203 return 0x00011800B0000820ull + (offset) * 0x1000000ull; 204 } 205 return 0x00011800B0000820ull + (offset) * 0x8000000ull; 206 } 207 CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long offset)208static inline u64 CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long offset) 209 { 210 switch (cvmx_get_octeon_family()) { 211 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 212 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 213 return 0x00011800B0000840ull + (offset) * 0x8000000ull; 214 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 215 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 216 return 0x00011800B0000840ull + (offset) * 0x8000000ull; 217 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 218 return 0x00011800B0000840ull + (offset) * 0x1000000ull; 219 } 220 return 0x00011800B0000840ull + (offset) * 0x8000000ull; 221 } 222 CVMX_PCSXX_TX_RX_STATES_REG(unsigned long offset)223static inline u64 CVMX_PCSXX_TX_RX_STATES_REG(unsigned long offset) 224 { 225 switch (cvmx_get_octeon_family()) { 226 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 227 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 228 return 0x00011800B0000830ull + (offset) * 0x8000000ull; 229 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 230 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 231 return 0x00011800B0000830ull + (offset) * 0x8000000ull; 232 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 233 return 0x00011800B0000830ull + (offset) * 0x1000000ull; 234 } 235 return 0x00011800B0000830ull + (offset) * 0x8000000ull; 236 } 237 238 /** 239 * cvmx_pcsx#_10gbx_status_reg 240 * 241 * PCSX_10GBX_STATUS_REG = 10gbx_status_reg 242 * 243 */ 244 union cvmx_pcsxx_10gbx_status_reg { 245 u64 u64; 246 struct cvmx_pcsxx_10gbx_status_reg_s { 247 u64 reserved_13_63 : 51; 248 u64 alignd : 1; 249 u64 pattst : 1; 250 u64 reserved_4_10 : 7; 251 u64 l3sync : 1; 252 u64 l2sync : 1; 253 u64 l1sync : 1; 254 u64 l0sync : 1; 255 } s; 256 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; 257 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; 258 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; 259 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; 260 struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; 261 struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; 262 struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; 263 struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; 264 struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; 265 struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; 266 struct cvmx_pcsxx_10gbx_status_reg_s cn70xx; 267 struct cvmx_pcsxx_10gbx_status_reg_s cn70xxp1; 268 }; 269 270 typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t; 271 272 /** 273 * cvmx_pcsx#_bist_status_reg 274 * 275 * PCSX Bist Status Register 276 * 277 */ 278 union cvmx_pcsxx_bist_status_reg { 279 u64 u64; 280 struct cvmx_pcsxx_bist_status_reg_s { 281 u64 reserved_1_63 : 63; 282 u64 bist_status : 1; 283 } s; 284 struct cvmx_pcsxx_bist_status_reg_s cn52xx; 285 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; 286 struct cvmx_pcsxx_bist_status_reg_s cn56xx; 287 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; 288 struct cvmx_pcsxx_bist_status_reg_s cn61xx; 289 struct cvmx_pcsxx_bist_status_reg_s cn63xx; 290 struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; 291 struct cvmx_pcsxx_bist_status_reg_s cn66xx; 292 struct cvmx_pcsxx_bist_status_reg_s cn68xx; 293 struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; 294 struct cvmx_pcsxx_bist_status_reg_s cn70xx; 295 struct cvmx_pcsxx_bist_status_reg_s cn70xxp1; 296 }; 297 298 typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t; 299 300 /** 301 * cvmx_pcsx#_bit_lock_status_reg 302 * 303 * PCSX Bit Lock Status Register 304 * 305 */ 306 union cvmx_pcsxx_bit_lock_status_reg { 307 u64 u64; 308 struct cvmx_pcsxx_bit_lock_status_reg_s { 309 u64 reserved_4_63 : 60; 310 u64 bitlck3 : 1; 311 u64 bitlck2 : 1; 312 u64 bitlck1 : 1; 313 u64 bitlck0 : 1; 314 } s; 315 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; 316 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; 317 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; 318 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; 319 struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; 320 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; 321 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; 322 struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; 323 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; 324 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; 325 struct cvmx_pcsxx_bit_lock_status_reg_s cn70xx; 326 struct cvmx_pcsxx_bit_lock_status_reg_s cn70xxp1; 327 }; 328 329 typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t; 330 331 /** 332 * cvmx_pcsx#_control1_reg 333 * 334 * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. 335 * PKT_SZ is effective only when LA_EN=1 336 * For normal operation(sgmii or 1000Base-X), this bit must be 0. 337 * See pcsx.csr for xaui logic analyzer mode. 338 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 339 * 340 * 341 * PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3 342 * 343 * 344 * PCSX_CONTROL1_REG = Control Register1 345 */ 346 union cvmx_pcsxx_control1_reg { 347 u64 u64; 348 struct cvmx_pcsxx_control1_reg_s { 349 u64 reserved_16_63 : 48; 350 u64 reset : 1; 351 u64 loopbck1 : 1; 352 u64 spdsel1 : 1; 353 u64 reserved_12_12 : 1; 354 u64 lo_pwr : 1; 355 u64 reserved_7_10 : 4; 356 u64 spdsel0 : 1; 357 u64 spd : 4; 358 u64 reserved_0_1 : 2; 359 } s; 360 struct cvmx_pcsxx_control1_reg_s cn52xx; 361 struct cvmx_pcsxx_control1_reg_s cn52xxp1; 362 struct cvmx_pcsxx_control1_reg_s cn56xx; 363 struct cvmx_pcsxx_control1_reg_s cn56xxp1; 364 struct cvmx_pcsxx_control1_reg_s cn61xx; 365 struct cvmx_pcsxx_control1_reg_s cn63xx; 366 struct cvmx_pcsxx_control1_reg_s cn63xxp1; 367 struct cvmx_pcsxx_control1_reg_s cn66xx; 368 struct cvmx_pcsxx_control1_reg_s cn68xx; 369 struct cvmx_pcsxx_control1_reg_s cn68xxp1; 370 struct cvmx_pcsxx_control1_reg_s cn70xx; 371 struct cvmx_pcsxx_control1_reg_s cn70xxp1; 372 }; 373 374 typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t; 375 376 /** 377 * cvmx_pcsx#_control2_reg 378 * 379 * PCSX_CONTROL2_REG = Control Register2 380 * 381 */ 382 union cvmx_pcsxx_control2_reg { 383 u64 u64; 384 struct cvmx_pcsxx_control2_reg_s { 385 u64 reserved_2_63 : 62; 386 u64 type : 2; 387 } s; 388 struct cvmx_pcsxx_control2_reg_s cn52xx; 389 struct cvmx_pcsxx_control2_reg_s cn52xxp1; 390 struct cvmx_pcsxx_control2_reg_s cn56xx; 391 struct cvmx_pcsxx_control2_reg_s cn56xxp1; 392 struct cvmx_pcsxx_control2_reg_s cn61xx; 393 struct cvmx_pcsxx_control2_reg_s cn63xx; 394 struct cvmx_pcsxx_control2_reg_s cn63xxp1; 395 struct cvmx_pcsxx_control2_reg_s cn66xx; 396 struct cvmx_pcsxx_control2_reg_s cn68xx; 397 struct cvmx_pcsxx_control2_reg_s cn68xxp1; 398 struct cvmx_pcsxx_control2_reg_s cn70xx; 399 struct cvmx_pcsxx_control2_reg_s cn70xxp1; 400 }; 401 402 typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t; 403 404 /** 405 * cvmx_pcsx#_int_en_reg 406 * 407 * PCSX Interrupt Enable Register 408 * 409 */ 410 union cvmx_pcsxx_int_en_reg { 411 u64 u64; 412 struct cvmx_pcsxx_int_en_reg_s { 413 u64 reserved_7_63 : 57; 414 u64 dbg_sync_en : 1; 415 u64 algnlos_en : 1; 416 u64 synlos_en : 1; 417 u64 bitlckls_en : 1; 418 u64 rxsynbad_en : 1; 419 u64 rxbad_en : 1; 420 u64 txflt_en : 1; 421 } s; 422 struct cvmx_pcsxx_int_en_reg_cn52xx { 423 u64 reserved_6_63 : 58; 424 u64 algnlos_en : 1; 425 u64 synlos_en : 1; 426 u64 bitlckls_en : 1; 427 u64 rxsynbad_en : 1; 428 u64 rxbad_en : 1; 429 u64 txflt_en : 1; 430 } cn52xx; 431 struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; 432 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; 433 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; 434 struct cvmx_pcsxx_int_en_reg_s cn61xx; 435 struct cvmx_pcsxx_int_en_reg_s cn63xx; 436 struct cvmx_pcsxx_int_en_reg_s cn63xxp1; 437 struct cvmx_pcsxx_int_en_reg_s cn66xx; 438 struct cvmx_pcsxx_int_en_reg_s cn68xx; 439 struct cvmx_pcsxx_int_en_reg_s cn68xxp1; 440 struct cvmx_pcsxx_int_en_reg_s cn70xx; 441 struct cvmx_pcsxx_int_en_reg_s cn70xxp1; 442 }; 443 444 typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t; 445 446 /** 447 * cvmx_pcsx#_int_reg 448 * 449 * PCSX Interrupt Register 450 * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state 451 * machine in 452 * Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to 453 * SYNC_ACQUIRED_2 454 * indicating an invalid code group was received on one of the 4 receive lanes. 455 * This interrupt should be always disabled and used only for link problem debugging help. 456 */ 457 union cvmx_pcsxx_int_reg { 458 u64 u64; 459 struct cvmx_pcsxx_int_reg_s { 460 u64 reserved_7_63 : 57; 461 u64 dbg_sync : 1; 462 u64 algnlos : 1; 463 u64 synlos : 1; 464 u64 bitlckls : 1; 465 u64 rxsynbad : 1; 466 u64 rxbad : 1; 467 u64 txflt : 1; 468 } s; 469 struct cvmx_pcsxx_int_reg_cn52xx { 470 u64 reserved_6_63 : 58; 471 u64 algnlos : 1; 472 u64 synlos : 1; 473 u64 bitlckls : 1; 474 u64 rxsynbad : 1; 475 u64 rxbad : 1; 476 u64 txflt : 1; 477 } cn52xx; 478 struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; 479 struct cvmx_pcsxx_int_reg_cn52xx cn56xx; 480 struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; 481 struct cvmx_pcsxx_int_reg_s cn61xx; 482 struct cvmx_pcsxx_int_reg_s cn63xx; 483 struct cvmx_pcsxx_int_reg_s cn63xxp1; 484 struct cvmx_pcsxx_int_reg_s cn66xx; 485 struct cvmx_pcsxx_int_reg_s cn68xx; 486 struct cvmx_pcsxx_int_reg_s cn68xxp1; 487 struct cvmx_pcsxx_int_reg_s cn70xx; 488 struct cvmx_pcsxx_int_reg_s cn70xxp1; 489 }; 490 491 typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t; 492 493 /** 494 * cvmx_pcsx#_log_anl_reg 495 * 496 * PCSX Logic Analyzer Register 497 * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when 498 * LA_EN=1 499 * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0]. 500 * See pcs.csr for sgmii/1000Base-X logic analyzer mode. 501 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 502 */ 503 union cvmx_pcsxx_log_anl_reg { 504 u64 u64; 505 struct cvmx_pcsxx_log_anl_reg_s { 506 u64 reserved_7_63 : 57; 507 u64 enc_mode : 1; 508 u64 drop_ln : 2; 509 u64 lafifovfl : 1; 510 u64 la_en : 1; 511 u64 pkt_sz : 2; 512 } s; 513 struct cvmx_pcsxx_log_anl_reg_s cn52xx; 514 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; 515 struct cvmx_pcsxx_log_anl_reg_s cn56xx; 516 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; 517 struct cvmx_pcsxx_log_anl_reg_s cn61xx; 518 struct cvmx_pcsxx_log_anl_reg_s cn63xx; 519 struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; 520 struct cvmx_pcsxx_log_anl_reg_s cn66xx; 521 struct cvmx_pcsxx_log_anl_reg_s cn68xx; 522 struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; 523 struct cvmx_pcsxx_log_anl_reg_s cn70xx; 524 struct cvmx_pcsxx_log_anl_reg_s cn70xxp1; 525 }; 526 527 typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t; 528 529 /** 530 * cvmx_pcsx#_misc_ctl_reg 531 * 532 * PCSX Misc Control Register 533 * LN_SWAP for XAUI is to simplify interconnection layout between devices 534 */ 535 union cvmx_pcsxx_misc_ctl_reg { 536 u64 u64; 537 struct cvmx_pcsxx_misc_ctl_reg_s { 538 u64 reserved_4_63 : 60; 539 u64 tx_swap : 1; 540 u64 rx_swap : 1; 541 u64 xaui : 1; 542 u64 gmxeno : 1; 543 } s; 544 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; 545 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; 546 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; 547 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; 548 struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; 549 struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; 550 struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; 551 struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; 552 struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; 553 struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; 554 struct cvmx_pcsxx_misc_ctl_reg_s cn70xx; 555 struct cvmx_pcsxx_misc_ctl_reg_s cn70xxp1; 556 }; 557 558 typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t; 559 560 /** 561 * cvmx_pcsx#_rx_sync_states_reg 562 * 563 * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register 564 * 565 */ 566 union cvmx_pcsxx_rx_sync_states_reg { 567 u64 u64; 568 struct cvmx_pcsxx_rx_sync_states_reg_s { 569 u64 reserved_16_63 : 48; 570 u64 sync3st : 4; 571 u64 sync2st : 4; 572 u64 sync1st : 4; 573 u64 sync0st : 4; 574 } s; 575 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; 576 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; 577 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; 578 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; 579 struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; 580 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; 581 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; 582 struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; 583 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; 584 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; 585 struct cvmx_pcsxx_rx_sync_states_reg_s cn70xx; 586 struct cvmx_pcsxx_rx_sync_states_reg_s cn70xxp1; 587 }; 588 589 typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t; 590 591 /** 592 * cvmx_pcsx#_serdes_crdt_cnt_reg 593 * 594 * PCSX SERDES Credit Count 595 * 596 */ 597 union cvmx_pcsxx_serdes_crdt_cnt_reg { 598 u64 u64; 599 struct cvmx_pcsxx_serdes_crdt_cnt_reg_s { 600 u64 reserved_5_63 : 59; 601 u64 cnt : 5; 602 } s; 603 struct cvmx_pcsxx_serdes_crdt_cnt_reg_s cn70xx; 604 struct cvmx_pcsxx_serdes_crdt_cnt_reg_s cn70xxp1; 605 }; 606 607 typedef union cvmx_pcsxx_serdes_crdt_cnt_reg cvmx_pcsxx_serdes_crdt_cnt_reg_t; 608 609 /** 610 * cvmx_pcsx#_spd_abil_reg 611 * 612 * PCSX_SPD_ABIL_REG = Speed ability register 613 * 614 */ 615 union cvmx_pcsxx_spd_abil_reg { 616 u64 u64; 617 struct cvmx_pcsxx_spd_abil_reg_s { 618 u64 reserved_2_63 : 62; 619 u64 tenpasst : 1; 620 u64 tengb : 1; 621 } s; 622 struct cvmx_pcsxx_spd_abil_reg_s cn52xx; 623 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; 624 struct cvmx_pcsxx_spd_abil_reg_s cn56xx; 625 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; 626 struct cvmx_pcsxx_spd_abil_reg_s cn61xx; 627 struct cvmx_pcsxx_spd_abil_reg_s cn63xx; 628 struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; 629 struct cvmx_pcsxx_spd_abil_reg_s cn66xx; 630 struct cvmx_pcsxx_spd_abil_reg_s cn68xx; 631 struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; 632 struct cvmx_pcsxx_spd_abil_reg_s cn70xx; 633 struct cvmx_pcsxx_spd_abil_reg_s cn70xxp1; 634 }; 635 636 typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t; 637 638 /** 639 * cvmx_pcsx#_status1_reg 640 * 641 * PCSX_STATUS1_REG = Status Register1 642 * 643 */ 644 union cvmx_pcsxx_status1_reg { 645 u64 u64; 646 struct cvmx_pcsxx_status1_reg_s { 647 u64 reserved_8_63 : 56; 648 u64 flt : 1; 649 u64 reserved_3_6 : 4; 650 u64 rcv_lnk : 1; 651 u64 lpable : 1; 652 u64 reserved_0_0 : 1; 653 } s; 654 struct cvmx_pcsxx_status1_reg_s cn52xx; 655 struct cvmx_pcsxx_status1_reg_s cn52xxp1; 656 struct cvmx_pcsxx_status1_reg_s cn56xx; 657 struct cvmx_pcsxx_status1_reg_s cn56xxp1; 658 struct cvmx_pcsxx_status1_reg_s cn61xx; 659 struct cvmx_pcsxx_status1_reg_s cn63xx; 660 struct cvmx_pcsxx_status1_reg_s cn63xxp1; 661 struct cvmx_pcsxx_status1_reg_s cn66xx; 662 struct cvmx_pcsxx_status1_reg_s cn68xx; 663 struct cvmx_pcsxx_status1_reg_s cn68xxp1; 664 struct cvmx_pcsxx_status1_reg_s cn70xx; 665 struct cvmx_pcsxx_status1_reg_s cn70xxp1; 666 }; 667 668 typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t; 669 670 /** 671 * cvmx_pcsx#_status2_reg 672 * 673 * PCSX_STATUS2_REG = Status Register2 674 * 675 */ 676 union cvmx_pcsxx_status2_reg { 677 u64 u64; 678 struct cvmx_pcsxx_status2_reg_s { 679 u64 reserved_16_63 : 48; 680 u64 dev : 2; 681 u64 reserved_12_13 : 2; 682 u64 xmtflt : 1; 683 u64 rcvflt : 1; 684 u64 reserved_3_9 : 7; 685 u64 tengb_w : 1; 686 u64 tengb_x : 1; 687 u64 tengb_r : 1; 688 } s; 689 struct cvmx_pcsxx_status2_reg_s cn52xx; 690 struct cvmx_pcsxx_status2_reg_s cn52xxp1; 691 struct cvmx_pcsxx_status2_reg_s cn56xx; 692 struct cvmx_pcsxx_status2_reg_s cn56xxp1; 693 struct cvmx_pcsxx_status2_reg_s cn61xx; 694 struct cvmx_pcsxx_status2_reg_s cn63xx; 695 struct cvmx_pcsxx_status2_reg_s cn63xxp1; 696 struct cvmx_pcsxx_status2_reg_s cn66xx; 697 struct cvmx_pcsxx_status2_reg_s cn68xx; 698 struct cvmx_pcsxx_status2_reg_s cn68xxp1; 699 struct cvmx_pcsxx_status2_reg_s cn70xx; 700 struct cvmx_pcsxx_status2_reg_s cn70xxp1; 701 }; 702 703 typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t; 704 705 /** 706 * cvmx_pcsx#_tx_rx_polarity_reg 707 * 708 * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]]; 709 * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]]; 710 * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities 711 */ 712 union cvmx_pcsxx_tx_rx_polarity_reg { 713 u64 u64; 714 struct cvmx_pcsxx_tx_rx_polarity_reg_s { 715 u64 reserved_10_63 : 54; 716 u64 xor_rxplrt : 4; 717 u64 xor_txplrt : 4; 718 u64 rxplrt : 1; 719 u64 txplrt : 1; 720 } s; 721 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; 722 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { 723 u64 reserved_2_63 : 62; 724 u64 rxplrt : 1; 725 u64 txplrt : 1; 726 } cn52xxp1; 727 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; 728 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; 729 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; 730 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; 731 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; 732 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; 733 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; 734 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; 735 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn70xx; 736 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn70xxp1; 737 }; 738 739 typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t; 740 741 /** 742 * cvmx_pcsx#_tx_rx_states_reg 743 * 744 * PCSX_TX_RX_STATES_REG = Transmit Receive States Register 745 * 746 */ 747 union cvmx_pcsxx_tx_rx_states_reg { 748 u64 u64; 749 struct cvmx_pcsxx_tx_rx_states_reg_s { 750 u64 reserved_14_63 : 50; 751 u64 term_err : 1; 752 u64 syn3bad : 1; 753 u64 syn2bad : 1; 754 u64 syn1bad : 1; 755 u64 syn0bad : 1; 756 u64 rxbad : 1; 757 u64 algn_st : 3; 758 u64 rx_st : 2; 759 u64 tx_st : 3; 760 } s; 761 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; 762 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { 763 u64 reserved_13_63 : 51; 764 u64 syn3bad : 1; 765 u64 syn2bad : 1; 766 u64 syn1bad : 1; 767 u64 syn0bad : 1; 768 u64 rxbad : 1; 769 u64 algn_st : 3; 770 u64 rx_st : 2; 771 u64 tx_st : 3; 772 } cn52xxp1; 773 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; 774 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; 775 struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; 776 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; 777 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; 778 struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; 779 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; 780 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; 781 struct cvmx_pcsxx_tx_rx_states_reg_s cn70xx; 782 struct cvmx_pcsxx_tx_rx_states_reg_s cn70xxp1; 783 }; 784 785 typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t; 786 787 #endif 788