1 /* 2 * NS16550 Serial Port 3 * originally from linux source (arch/powerpc/boot/ns16550.h) 4 * 5 * Cleanup and unification 6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7 * 8 * modified slightly to 9 * have addresses as offsets from CONFIG_SYS_ISA_BASE 10 * added a few more definitions 11 * added prototypes for ns16550.c 12 * reduced no of com ports to 2 13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14 * 15 * added support for port on 64-bit bus 16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17 */ 18 19 /* 20 * Note that the following macro magic uses the fact that the compiler 21 * will not allocate storage for arrays of size 0 22 */ 23 24 #ifndef __ns16550_h 25 #define __ns16550_h 26 27 #include <linux/types.h> 28 29 #if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \ 30 defined(CONFIG_DEBUG_UART) 31 /* 32 * For driver model we always use one byte per register, and sort out the 33 * differences in the driver. In the case of CONFIG_NS16550_DYNAMIC we do 34 * similar, and CONFIG_DEBUG_UART is responsible for shifts in its own manner. 35 */ 36 #define UART_REG(x) unsigned char x 37 #else 38 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 39 #error "Please define NS16550 registers size." 40 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 41 #define UART_REG(x) \ 42 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 43 unsigned char x; 44 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 45 #define UART_REG(x) \ 46 unsigned char x; \ 47 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 48 #endif 49 #endif /* CONFIG_NS16550_DYNAMIC */ 50 51 enum ns16550_flags { 52 NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ 53 NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */ 54 NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */ 55 }; 56 57 /** 58 * struct ns16550_plat - information about a NS16550 port 59 * 60 * @base: Base register address 61 * @reg_width: IO accesses size of registers (in bytes, 1 or 4) 62 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) 63 * @reg_offset: Offset to start of registers (normally 0) 64 * @clock: UART base clock speed in Hz 65 * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) 66 * @flags: A few flags (enum ns16550_flags) 67 * @bdf: PCI slot/function (pci_dev_t) 68 */ 69 struct ns16550_plat { 70 unsigned long base; 71 int reg_width; 72 int reg_shift; 73 int reg_offset; 74 int clock; 75 u32 fcr; 76 int flags; 77 #if defined(CONFIG_PCI) && defined(CONFIG_SPL) 78 int bdf; 79 #endif 80 }; 81 82 struct udevice; 83 84 struct ns16550 { 85 UART_REG(rbr); /* 0 */ 86 UART_REG(ier); /* 1 */ 87 UART_REG(fcr); /* 2 */ 88 UART_REG(lcr); /* 3 */ 89 UART_REG(mcr); /* 4 */ 90 UART_REG(lsr); /* 5 */ 91 UART_REG(msr); /* 6 */ 92 UART_REG(spr); /* 7 */ 93 #ifdef CONFIG_SOC_DA8XX 94 UART_REG(reg8); /* 8 */ 95 UART_REG(reg9); /* 9 */ 96 UART_REG(revid1); /* A */ 97 UART_REG(revid2); /* B */ 98 UART_REG(pwr_mgmt); /* C */ 99 UART_REG(mdr1); /* D */ 100 #else 101 UART_REG(mdr1); /* 8 */ 102 UART_REG(reg9); /* 9 */ 103 UART_REG(regA); /* A */ 104 UART_REG(regB); /* B */ 105 UART_REG(regC); /* C */ 106 UART_REG(regD); /* D */ 107 UART_REG(regE); /* E */ 108 UART_REG(uasr); /* F */ 109 UART_REG(scr); /* 10*/ 110 UART_REG(ssr); /* 11*/ 111 #endif 112 #if CONFIG_IS_ENABLED(DM_SERIAL) 113 struct ns16550_plat *plat; 114 #endif 115 }; 116 117 #define thr rbr 118 #define iir fcr 119 #define dll rbr 120 #define dlm ier 121 122 /* 123 * These are the definitions for the FIFO Control Register 124 */ 125 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 126 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 127 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 128 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 129 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 130 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 131 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 132 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 133 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 134 135 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 136 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 137 138 /* Ingenic JZ47xx specific UART-enable bit. */ 139 #define UART_FCR_UME 0x10 140 141 /* Clear & enable FIFOs */ 142 #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ 143 UART_FCR_RXSR | \ 144 UART_FCR_TXSR) 145 146 /* 147 * These are the definitions for the Modem Control Register 148 */ 149 #define UART_MCR_DTR 0x01 /* DTR */ 150 #define UART_MCR_RTS 0x02 /* RTS */ 151 #define UART_MCR_OUT1 0x04 /* Out 1 */ 152 #define UART_MCR_OUT2 0x08 /* Out 2 */ 153 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 154 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 155 156 #define UART_MCR_DMA_EN 0x04 157 #define UART_MCR_TX_DFR 0x08 158 159 /* 160 * These are the definitions for the Line Control Register 161 * 162 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 163 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 164 */ 165 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 166 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 167 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 168 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 169 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 170 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 171 #define UART_LCR_PEN 0x08 /* Parity eneble */ 172 #define UART_LCR_EPS 0x10 /* Even Parity Select */ 173 #define UART_LCR_STKP 0x20 /* Stick Parity */ 174 #define UART_LCR_SBRK 0x40 /* Set Break */ 175 #define UART_LCR_BKSE 0x80 /* Bank select enable */ 176 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 177 178 /* 179 * These are the definitions for the Line Status Register 180 */ 181 #define UART_LSR_DR 0x01 /* Data ready */ 182 #define UART_LSR_OE 0x02 /* Overrun */ 183 #define UART_LSR_PE 0x04 /* Parity error */ 184 #define UART_LSR_FE 0x08 /* Framing error */ 185 #define UART_LSR_BI 0x10 /* Break */ 186 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 187 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 188 #define UART_LSR_ERR 0x80 /* Error */ 189 190 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 191 #define UART_MSR_RI 0x40 /* Ring Indicator */ 192 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 193 #define UART_MSR_CTS 0x10 /* Clear to Send */ 194 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 195 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 196 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 197 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 198 199 /* 200 * These are the definitions for the Interrupt Identification Register 201 */ 202 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 203 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 204 205 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 206 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 207 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 208 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 209 210 /* 211 * These are the definitions for the Interrupt Enable Register 212 */ 213 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 214 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 215 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 216 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 217 218 /* useful defaults for LCR */ 219 #define UART_LCR_8N1 0x03 220 221 void ns16550_init(struct ns16550 *com_port, int baud_divisor); 222 void ns16550_putc(struct ns16550 *com_port, char c); 223 char ns16550_getc(struct ns16550 *com_port); 224 int ns16550_tstc(struct ns16550 *com_port); 225 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); 226 227 /** 228 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 229 * 230 * Given the UART input clock and required baudrate, calculate the divisor 231 * that should be used. 232 * 233 * @port: UART port 234 * @clock: UART input clock speed in Hz 235 * @baudrate: Required baud rate 236 * Return: baud rate divisor that should be used 237 */ 238 int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate); 239 240 /** 241 * ns16550_serial_of_to_plat() - convert DT to platform data 242 * 243 * Decode a device tree node for an ns16550 device. This includes the 244 * register base address and register shift properties. The caller must set 245 * up the clock frequency. 246 * 247 * @dev: dev to decode platform data for 248 * @return: 0 if OK, -EINVAL on error 249 */ 250 int ns16550_serial_of_to_plat(struct udevice *dev); 251 252 /** 253 * ns16550_serial_probe() - probe a serial port 254 * 255 * This sets up the serial port ready for use, except for the baud rate 256 * Return: 0, or -ve on error 257 */ 258 int ns16550_serial_probe(struct udevice *dev); 259 260 /** 261 * struct ns16550_serial_ops - ns16550 serial operations 262 * 263 * These should be used by the client driver for the driver's 'ops' member 264 */ 265 extern const struct dm_serial_ops ns16550_serial_ops; 266 267 #endif /* __ns16550_h */ 268