1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * Logic Product Development <www.logicpd.com>
5 *
6 * Author :
7 * Peter Barada <peter.barada@logicpd.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13 #include <common.h>
14 #include <dm.h>
15 #include <init.h>
16 #include <net.h>
17 #include <ns16550.h>
18 #include <nand.h>
19 #include <i2c.h>
20 #include <serial.h>
21 #include <twl4030.h>
22 #include <asm/global_data.h>
23 #include <asm/io.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/mux.h>
26 #include <asm/arch/mem.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/gpio.h>
29 #include <asm/omap_mmc.h>
30 #include <asm/mach-types.h>
31 #include <linux/mtd/rawnand.h>
32 #include <asm/omap_musb.h>
33 #include <linux/errno.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/musb.h>
37 #include "omap3logic.h"
38 #ifdef CONFIG_USB_EHCI_HCD
39 #include <usb.h>
40 #include <asm/ehci-omap.h>
41 #endif
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
50 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
51 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
52
53 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
58 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
59 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
60
61 #define CFG_SMC911X_BASE 0x08000000
62
63 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)64 int spl_start_uboot(void)
65 {
66 /* break into full u-boot on 'c' */
67 return serial_tstc() && serial_getc() == 'c';
68 }
69 #endif
70
71 #if defined(CONFIG_SPL_BUILD)
72 /*
73 * Routine: get_board_mem_timings
74 * Description: If we use SPL then there is no x-loader nor config header
75 * so we have to setup the DDR timings ourself on the first bank. This
76 * provides the timing values back to the function that configures
77 * the memory.
78 */
get_board_mem_timings(struct board_sdrc_timings * timings)79 void get_board_mem_timings(struct board_sdrc_timings *timings)
80 {
81 timings->mr = MICRON_V_MR_165;
82
83 if (get_cpu_family() == CPU_OMAP36XX) {
84 /* 200 MHz works for OMAP36/DM37 */
85 /* 256MB DDR */
86 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
87 timings->ctrla = MICRON_V_ACTIMA_200;
88 timings->ctrlb = MICRON_V_ACTIMB_200;
89 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
90 } else {
91 /* 165 MHz works for OMAP35 */
92 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
93 timings->ctrla = MICRON_V_ACTIMA_165;
94 timings->ctrlb = MICRON_V_ACTIMB_165;
95 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
96 }
97 }
98
99 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
100 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
101 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
102
spl_board_prepare_for_linux(void)103 void spl_board_prepare_for_linux(void)
104 {
105 /* The Micron NAND starts locked which
106 * prohibits mounting the NAND as RW
107 * The following commands are what unlocks
108 * the NAND to become RW Falcon Mode does not
109 * have as many smarts as U-Boot, but Logic PD
110 * only makes NAND with 512MB so these hard coded
111 * values should work for all current models
112 */
113
114 writeb(0x70, GPMC_NAND_COMMAND_0);
115 writeb(-1, GPMC_NAND_DATA_0);
116 writeb(0x7a, GPMC_NAND_COMMAND_0);
117 writeb(0x00, GPMC_NAND_ADDRESS_0);
118 writeb(0x00, GPMC_NAND_ADDRESS_0);
119 writeb(0x00, GPMC_NAND_ADDRESS_0);
120 writeb(-1, GPMC_NAND_COMMAND_0);
121
122 /* Begin address 0 */
123 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
124 writeb(0x00, GPMC_NAND_ADDRESS_0);
125 writeb(0x00, GPMC_NAND_ADDRESS_0);
126 writeb(0x00, GPMC_NAND_ADDRESS_0);
127 writeb(-1, GPMC_NAND_DATA_0);
128
129 /* Ending address at the end of Flash */
130 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
131 writeb(0xc0, GPMC_NAND_ADDRESS_0);
132 writeb(0xff, GPMC_NAND_ADDRESS_0);
133 writeb(0x03, GPMC_NAND_ADDRESS_0);
134 writeb(-1, GPMC_NAND_DATA_0);
135 writeb(0x79, GPMC_NAND_COMMAND_0);
136 writeb(-1, GPMC_NAND_DATA_0);
137 writeb(-1, GPMC_NAND_DATA_0);
138 }
139 #endif
140
141 /*
142 * Routine: misc_init_r
143 * Description: Configure board specific parts
144 */
misc_init_r(void)145 int misc_init_r(void)
146 {
147 twl4030_power_init();
148 twl4030_power_mmc_init(0);
149 omap_die_id_display();
150 return 0;
151 }
152
153 #if defined(CONFIG_FLASH_CFI_DRIVER)
154 static const u32 gpmc_dm37_c2nor_config[] = {
155 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
156 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
157 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
158 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
159 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
160 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
161 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
162 };
163
164 static const u32 gpmc_omap35_c2nor_config[] = {
165 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
166 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
167 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
168 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
169 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
170 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
171 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
172 };
173 #endif
174
175 /*
176 * Routine: board_init
177 * Description: Early hardware init.
178 */
board_init(void)179 int board_init(void)
180 {
181 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
182
183 /* boot param addr */
184 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
185 #if defined(CONFIG_FLASH_CFI_DRIVER)
186 if (get_cpu_family() == CPU_OMAP36XX) {
187 /* Enable CS2 for NOR Flash */
188 enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
189 0x10000000, GPMC_SIZE_64M);
190 } else {
191 enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
192 0x10000000, GPMC_SIZE_64M);
193 }
194 #endif
195 return 0;
196 }
197
198 #ifdef CONFIG_BOARD_LATE_INIT
199
unlock_nand(void)200 static void unlock_nand(void)
201 {
202 int dev = nand_curr_device;
203 struct mtd_info *mtd;
204
205 mtd = get_nand_dev_by_index(dev);
206 nand_unlock(mtd, 0, mtd->size, 0);
207 }
208
209 #ifdef CONFIG_SMC911X
210 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
211 static const u32 gpmc_lan92xx_config[] = {
212 NET_LAN92XX_GPMC_CONFIG1,
213 NET_LAN92XX_GPMC_CONFIG2,
214 NET_LAN92XX_GPMC_CONFIG3,
215 NET_LAN92XX_GPMC_CONFIG4,
216 NET_LAN92XX_GPMC_CONFIG5,
217 NET_LAN92XX_GPMC_CONFIG6,
218 };
219 #endif
220
board_late_init(void)221 int board_late_init(void)
222 {
223 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
224 unlock_nand();
225 #endif
226
227 #ifdef CONFIG_SMC911X
228 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
229 CFG_SMC911X_BASE, GPMC_SIZE_16M);
230 #endif
231 return 0;
232 }
233 #endif
234
235 #if defined(CONFIG_MMC)
board_mmc_power_init(void)236 void board_mmc_power_init(void)
237 {
238 twl4030_power_mmc_init(0);
239 }
240 #endif
241