1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Cadence DDR Controller 4 * 5 * Copyright (C) 2015 Renesas Electronics Europe Ltd 6 */ 7 8 #ifndef CADENCE_DDR_CTRL_H 9 #define CADENCE_DDR_CTRL_H 10 11 enum cdns_ddr_range_prot { 12 CDNS_DDR_RANGE_PROT_BITS_PRIV_SECURE = 0, 13 CDNS_DDR_RANGE_PROT_BITS_SECURE = 1, 14 CDNS_DDR_RANGE_PROT_BITS_PRIV = 2, 15 CDNS_DDR_RANGE_PROT_BITS_FULL = 3, 16 }; 17 18 /** 19 * Initialise the Cadence DDR Controller, but doesn't start it. 20 * 21 * It sets up the controller so that all 4 AXI slave ports allow access to all 22 * of the DDR with the same settings. This means that: 23 * - Full access permisions. 24 * - All read/write priorities are set to 2. 25 * - Bandwidth is set to 50%, overflow is allowed, i.e. it's a soft limit. 26 * If you want different properties for different ports and/or addr ranges, call 27 * the other functions before calling cdns_ddr_ctrl_start(). 28 * 29 * @ddr_ctrl_base Physical address of the DDR Controller. 30 * @async 0 if DDR clock is synchronous with the controller clock 31 * otherwise 1. 32 * @reg0 Pointer to array of 32-bit values to be written to registers 33 * 0 to 87. The values are generated by Cadence TCL scripts. 34 * @reg350 Pointer to array of 32-bit values to be written to registers 35 * 350 to 374. The values are generated by Cadence TCL scripts. 36 * @ddr_start_addr Physical address of the start of DDR. 37 * @ddr_size Size of the DDR in bytes. The controller will set the port 38 * protection range to match this size. 39 * @enable_ecc 0 to disable ECC, 1 to enable it. 40 * @enable_8bit 0 to use 16-bit bus width, 1 to use 8-bit bus width. 41 */ 42 void cdns_ddr_ctrl_init(void *ddr_ctrl_base, int async, 43 const u32 *reg0, const u32 *reg350, 44 u32 ddr_start_addr, u32 ddr_size, 45 int enable_ecc, int enable_8bit); 46 47 /** 48 * Start the Cadence DDR Controller. 49 * 50 * @ddr_ctrl_base Physical address of the DDR Controller. 51 */ 52 void cdns_ddr_ctrl_start(void *ddr_ctrl_base); 53 54 /** 55 * Set the priority for read and write operations for a specific AXI slave port. 56 * 57 * @base Physical address of the DDR Controller. 58 * @port Port number. Range is 0 to 3. 59 * @read_pri Priority for reads. Range is 0 to 3, where 0 is highest priority. 60 * @write_pri Priority for writes. Range is 0 to 3, where 0 is highest priority. 61 */ 62 void cdns_ddr_set_port_rw_priority(void *base, int port, 63 u8 read_pri, u8 write_pri); 64 65 /** 66 * Specify address range for a protection entry, for a specific AXI slave port. 67 * 68 * @base Physical address of the DDR Controller. 69 * @port Port number. Range is 0 to 3. 70 * @entry The protection entry. Range is 0 to 15. 71 * @start_addr Physical of the address range, must be aligned to 16KB. 72 * @size Size of the address range, must be multiple of 16KB. 73 */ 74 void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, 75 u32 addr_start, u32 size); 76 77 /** 78 * Specify address range for a protection entry, for all AXI slave ports. 79 * 80 * @base Physical address of the DDR Controller. 81 * @entry The protection entry. Range is 0 to 15. 82 * @start_addr Physical of the address range, must be aligned to 16KB. 83 * @size Size of the address range, must be multiple of 16KB. 84 */ 85 void cdns_ddr_enable_addr_range(void *base, int entry, 86 u32 addr_start, u32 size); 87 88 /** 89 * Specify protection entry details, for a specific AXI slave port. 90 * 91 * See the hardware manual for details of the range check bits. 92 * 93 * @base Physical address of the DDR Controller. 94 * @port Port number. Range is 0 to 3. 95 * @entry The protection entry. Range is 0 to 15. 96 */ 97 void cdns_ddr_enable_port_prot(void *base, int port, int entry, 98 enum cdns_ddr_range_prot range_protection_bits, 99 u16 range_RID_check_bits, 100 u16 range_WID_check_bits, 101 u8 range_RID_check_bits_ID_lookup, 102 u8 range_WID_check_bits_ID_lookup); 103 104 /** 105 * Specify protection entry details, for all AXI slave ports. 106 * 107 * See the hardware manual for details of the range check bits. 108 * 109 * @base Physical address of the DDR Controller. 110 * @entry The protection entry. Range is 0 to 15. 111 */ 112 void cdns_ddr_enable_prot(void *base, int entry, 113 enum cdns_ddr_range_prot range_protection_bits, 114 u16 range_RID_check_bits, 115 u16 range_WID_check_bits, 116 u8 range_RID_check_bits_ID_lookup, 117 u8 range_WID_check_bits_ID_lookup); 118 119 /** 120 * Specify bandwidth for each AXI port. 121 * 122 * See the hardware manual for details of the range check bits. 123 * 124 * @base Physical address of the DDR Controller. 125 * @port Port number. Range is 0 to 3. 126 * @max_percent 0 to 100. 127 */ 128 void cdns_ddr_set_port_bandwidth(void *base, int port, 129 u8 max_percent, u8 overflow_ok); 130 131 /* Standard JEDEC registers */ 132 #define MODE_REGISTER_MASK (3 << 14) 133 #define MODE_REGISTER_MR0 (0 << 14) 134 #define MODE_REGISTER_MR1 (1 << 14) 135 #define MODE_REGISTER_MR2 (2 << 14) 136 #define MODE_REGISTER_MR3 (3 << 14) 137 #define MR1_DRIVE_STRENGTH_MASK ((1 << 5) | (1 << 1)) 138 #define MR1_DRIVE_STRENGTH_34_OHMS ((0 << 5) | (1 << 1)) 139 #define MR1_DRIVE_STRENGTH_40_OHMS ((0 << 5) | (0 << 1)) 140 #define MR1_ODT_IMPEDANCE_MASK ((1 << 9) | (1 << 6) | (1 << 2)) 141 #define MR1_ODT_IMPEDANCE_60_OHMS ((0 << 9) | (0 << 6) | (1 << 2)) 142 #define MR1_ODT_IMPEDANCE_120_OHMS ((0 << 9) | (1 << 6) | (0 << 2)) 143 #define MR1_ODT_IMPEDANCE_40_OHMS ((0 << 9) | (1 << 6) | (1 << 2)) 144 #define MR1_ODT_IMPEDANCE_20_OHMS ((1 << 9) | (0 << 6) | (0 << 2)) 145 #define MR1_ODT_IMPEDANCE_30_OHMS ((1 << 9) | (0 << 6) | (1 << 2)) 146 #define MR2_DYNAMIC_ODT_MASK (3 << 9) 147 #define MR2_DYNAMIC_ODT_OFF (0 << 9) 148 #define MR2_SELF_REFRESH_TEMP_MASK (1 << 7) 149 #define MR2_SELF_REFRESH_TEMP_EXT (1 << 7) 150 151 /** 152 * Set certain fields of the JEDEC MR1 register. 153 */ 154 void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength); 155 156 /** 157 * Set certain fields of the JEDEC MR2 register. 158 */ 159 void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp); 160 161 /** 162 * Set ODT map of the DDR Controller. 163 */ 164 void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map); 165 166 /** 167 * Set ODT settings in the DDR Controller. 168 */ 169 void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, 170 u8 WR_TO_ODTH, u8 RD_TO_ODTH); 171 172 void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); 173 void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); 174 175 #endif 176