1 #ifndef __XEN_X86_DEFNS_H__ 2 #define __XEN_X86_DEFNS_H__ 3 4 /* 5 * EFLAGS bits 6 */ 7 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 8 #define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ 9 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25 26 #define X86_EFLAGS_ARITH_MASK \ 27 (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 28 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 29 30 /* 31 * Intel CPU flags in CR0 32 */ 33 #define X86_CR0_PE _AC(0x00000001, UL) /* Enable Protected Mode (RW) */ 34 #define X86_CR0_MP _AC(0x00000002, UL) /* Monitor Coprocessor (RW) */ 35 #define X86_CR0_EM _AC(0x00000004, UL) /* Require FPU Emulation (RO) */ 36 #define X86_CR0_TS _AC(0x00000008, UL) /* Task Switched (RW) */ 37 #define X86_CR0_ET _AC(0x00000010, UL) /* Extension type (RO) */ 38 #define X86_CR0_NE _AC(0x00000020, UL) /* Numeric Error Reporting (RW) */ 39 #define X86_CR0_WP _AC(0x00010000, UL) /* Supervisor Write Protect (RW) */ 40 #define X86_CR0_AM _AC(0x00040000, UL) /* Alignment Checking (RW) */ 41 #define X86_CR0_NW _AC(0x20000000, UL) /* Not Write-Through (RW) */ 42 #define X86_CR0_CD _AC(0x40000000, UL) /* Cache Disable (RW) */ 43 #define X86_CR0_PG _AC(0x80000000, UL) /* Paging (RW) */ 44 45 /* 46 * Intel CPU flags in CR3 47 */ 48 #define X86_CR3_NOFLUSH (_AC(1, ULL) << 63) 49 #define X86_CR3_ADDR_MASK (PAGE_MASK & PADDR_MASK) 50 #define X86_CR3_PCID_MASK _AC(0x0fff, ULL) /* Mask for PCID */ 51 52 /* 53 * Intel CPU features in CR4 54 */ 55 #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 56 #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 57 #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 58 #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 59 #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 60 #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 61 #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 62 #define X86_CR4_PGE 0x00000080 /* enable global pages */ 63 #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 64 #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 65 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 66 #define X86_CR4_UMIP 0x00000800 /* enable UMIP */ 67 #define X86_CR4_LA57 0x00001000 /* enable 5-level paging */ 68 #define X86_CR4_VMXE 0x00002000 /* enable VMX */ 69 #define X86_CR4_SMXE 0x00004000 /* enable SMX */ 70 #define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ 71 #define X86_CR4_PCIDE 0x00020000 /* enable PCID */ 72 #define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ 73 #define X86_CR4_SMEP 0x00100000 /* enable SMEP */ 74 #define X86_CR4_SMAP 0x00200000 /* enable SMAP */ 75 #define X86_CR4_PKE 0x00400000 /* enable PKE */ 76 #define X86_CR4_CET 0x00800000 /* Control-flow Enforcement Technology */ 77 #define X86_CR4_PKS 0x01000000 /* Protection Key Supervisor */ 78 79 /* 80 * XSTATE component flags in XCR0 | MSR_XSS 81 */ 82 #define X86_XCR0_X87 (_AC(1, ULL) << 0) 83 #define X86_XCR0_SSE (_AC(1, ULL) << 1) 84 #define X86_XCR0_YMM (_AC(1, ULL) << 2) 85 #define X86_XCR0_BNDREGS (_AC(1, ULL) << 3) 86 #define X86_XCR0_BNDCSR (_AC(1, ULL) << 4) 87 #define X86_XCR0_OPMASK (_AC(1, ULL) << 5) 88 #define X86_XCR0_ZMM (_AC(1, ULL) << 6) 89 #define X86_XCR0_HI_ZMM (_AC(1, ULL) << 7) 90 #define X86_XSS_PROC_TRACE (_AC(1, ULL) << 8) 91 #define X86_XCR0_PKRU (_AC(1, ULL) << 9) 92 #define X86_XSS_PASID (_AC(1, ULL) << 10) 93 #define X86_XSS_CET_U (_AC(1, ULL) << 11) 94 #define X86_XSS_CET_S (_AC(1, ULL) << 12) 95 #define X86_XSS_HDC (_AC(1, ULL) << 13) 96 #define X86_XSS_UINTR (_AC(1, ULL) << 14) 97 #define X86_XSS_LBR (_AC(1, ULL) << 15) 98 #define X86_XSS_HWP (_AC(1, ULL) << 16) 99 #define X86_XCR0_TILE_CFG (_AC(1, ULL) << 17) 100 #define X86_XCR0_TILE_DATA (_AC(1, ULL) << 18) 101 #define X86_XCR0_LWP (_AC(1, ULL) << 62) 102 103 #define X86_XCR0_STATES \ 104 (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS | \ 105 X86_XCR0_BNDCSR | X86_XCR0_OPMASK | X86_XCR0_ZMM | \ 106 X86_XCR0_HI_ZMM | X86_XCR0_PKRU | X86_XCR0_TILE_CFG | \ 107 X86_XCR0_TILE_DATA | \ 108 X86_XCR0_LWP) 109 110 #define X86_XSS_STATES \ 111 (X86_XSS_PROC_TRACE | X86_XSS_PASID | X86_XSS_CET_U | \ 112 X86_XSS_CET_S | X86_XSS_HDC | X86_XSS_UINTR | X86_XSS_LBR | \ 113 X86_XSS_HWP | \ 114 0) 115 116 /* 117 * Debug status flags in DR6. 118 * 119 * For backwards compatibility, status flags which overlap with 120 * X86_DR6_DEFAULT have inverted polarity. 121 */ 122 #define X86_DR6_B0 (_AC(1, UL) << 0) /* Breakpoint 0 */ 123 #define X86_DR6_B1 (_AC(1, UL) << 1) /* Breakpoint 1 */ 124 #define X86_DR6_B2 (_AC(1, UL) << 2) /* Breakpoint 2 */ 125 #define X86_DR6_B3 (_AC(1, UL) << 3) /* Breakpoint 3 */ 126 #define X86_DR6_BLD (_AC(1, UL) << 11) /* BusLock detect (INV) */ 127 #define X86_DR6_BD (_AC(1, UL) << 13) /* %dr access */ 128 #define X86_DR6_BS (_AC(1, UL) << 14) /* Single step */ 129 #define X86_DR6_BT (_AC(1, UL) << 15) /* Task switch */ 130 #define X86_DR6_RTM (_AC(1, UL) << 16) /* #DB/#BP in RTM region (INV) */ 131 132 #define X86_DR6_ZEROS _AC(0x00001000, UL) /* %dr6 bits forced to 0 */ 133 #define X86_DR6_DEFAULT _AC(0xffff0ff0, UL) /* Default %dr6 value */ 134 135 /* 136 * Debug control flags in DR7. 137 */ 138 #define X86_DR7_RTM (_AC(1, UL) << 11) /* RTM debugging enable */ 139 140 #define X86_DR7_ZEROS _AC(0x0000d000, UL) /* %dr7 bits forced to 0 */ 141 #define X86_DR7_DEFAULT _AC(0x00000400, UL) /* Default %dr7 value */ 142 143 /* 144 * Invalidation types for the INVPCID instruction. 145 */ 146 #define X86_INVPCID_INDIV_ADDR 0 147 #define X86_INVPCID_SINGLE_CTXT 1 148 #define X86_INVPCID_ALL_INCL_GLOBAL 2 149 #define X86_INVPCID_ALL_NON_GLOBAL 3 150 151 #define X86_NR_VECTORS 256 152 153 /* Exception Vectors */ 154 #define X86_EXC_DE 0 /* Divide Error */ 155 #define X86_EXC_DB 1 /* Debug Exception */ 156 #define X86_EXC_NMI 2 /* NMI */ 157 #define X86_EXC_BP 3 /* Breakpoint */ 158 #define X86_EXC_OF 4 /* Overflow */ 159 #define X86_EXC_BR 5 /* BOUND Range */ 160 #define X86_EXC_UD 6 /* Invalid Opcode */ 161 #define X86_EXC_NM 7 /* Device Not Available */ 162 #define X86_EXC_DF 8 /* Double Fault */ 163 #define X86_EXC_CSO 9 /* Coprocessor Segment Overrun */ 164 #define X86_EXC_TS 10 /* Invalid TSS */ 165 #define X86_EXC_NP 11 /* Segment Not Present */ 166 #define X86_EXC_SS 12 /* Stack-Segment Fault */ 167 #define X86_EXC_GP 13 /* General Porection Fault */ 168 #define X86_EXC_PF 14 /* Page Fault */ 169 #define X86_EXC_SPV 15 /* PIC Spurious Interrupt Vector */ 170 #define X86_EXC_MF 16 /* Maths fault (x87 FPU) */ 171 #define X86_EXC_AC 17 /* Alignment Check */ 172 #define X86_EXC_MC 18 /* Machine Check */ 173 #define X86_EXC_XM 19 /* SIMD Exception */ 174 #define X86_EXC_VE 20 /* Virtualisation Exception */ 175 #define X86_EXC_CP 21 /* Control-flow Protection */ 176 #define X86_EXC_HV 28 /* Hypervisor Injection */ 177 #define X86_EXC_VC 29 /* VMM Communication */ 178 #define X86_EXC_SX 30 /* Security Exception */ 179 180 #define X86_EXC_NUM 32 /* 32 reserved vectors */ 181 182 /* Bitmap of exceptions which have error codes. */ 183 #define X86_EXC_HAVE_EC \ 184 ((1u << X86_EXC_DF) | (1u << X86_EXC_TS) | (1u << X86_EXC_NP) | \ 185 (1u << X86_EXC_SS) | (1u << X86_EXC_GP) | (1u << X86_EXC_PF) | \ 186 (1u << X86_EXC_AC) | (1u << X86_EXC_CP) | \ 187 (1u << X86_EXC_VC) | (1u << X86_EXC_SX)) 188 189 /* Memory types */ 190 #define X86_MT_UC 0x00 /* uncachable */ 191 #define X86_MT_WC 0x01 /* write-combined */ 192 #define X86_MT_RSVD_2 0x02 /* reserved */ 193 #define X86_MT_RSVD_3 0x03 /* reserved */ 194 #define X86_MT_WT 0x04 /* write-through */ 195 #define X86_MT_WP 0x05 /* write-protect */ 196 #define X86_MT_WB 0x06 /* write-back */ 197 #define X86_MT_UCM 0x07 /* UC- */ 198 #define X86_NUM_MT 0x08 199 200 #endif /* __XEN_X86_DEFNS_H__ */ 201