1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <xen/types.h>
17 #include <xen/irq.h>
18 #include <xen/init.h>
19 #include <xen/acpi.h>
20 #include <xen/delay.h>
21 #include <xen/efi.h>
22 #include <xen/sched.h>
23
24 #include <xen/bitops.h>
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/setup.h>
31
32 #include <mach_apic.h>
33 #include <bios_ebda.h>
34
35 /* Have we found an MP table */
36 bool __initdata smp_found_config;
37
38 /*
39 * Various Linux-internal data structures created from the
40 * MP-table.
41 */
42 unsigned char __read_mostly apic_version[MAX_APICS];
43 unsigned char __read_mostly mp_bus_id_to_type[MAX_MP_BUSSES];
44
45 /* I/O APIC entries */
46 struct mpc_config_ioapic __read_mostly mp_ioapics[MAX_IO_APICS];
47
48 /* # of MP IRQ source entries */
49 struct mpc_config_intsrc __read_mostly mp_irqs[MAX_IRQ_SOURCES];
50
51 /* MP IRQ source entries */
52 int __read_mostly mp_irq_entries;
53
54 bool __read_mostly pic_mode;
55 bool __read_mostly def_to_bigsmp;
56 unsigned long __read_mostly mp_lapic_addr;
57
58 /* Processor that is doing the boot up */
59 unsigned int __read_mostly boot_cpu_physical_apicid = BAD_APICID;
60
61 /* Internal processor count */
62 static unsigned int num_processors;
63 unsigned int __read_mostly disabled_cpus;
64
65 /* Bitmask of physically existing CPUs */
66 physid_mask_t phys_cpu_present_map;
67
68 /* Record whether CPUs haven't been added due to overflows. */
69 bool __read_mostly unaccounted_cpus;
70
set_nr_cpu_ids(unsigned int max_cpus)71 void __init set_nr_cpu_ids(unsigned int max_cpus)
72 {
73 unsigned int tot_cpus = num_processors + disabled_cpus;
74
75 if (!max_cpus)
76 max_cpus = tot_cpus;
77 if (max_cpus > NR_CPUS)
78 max_cpus = NR_CPUS;
79 else if (!max_cpus)
80 max_cpus = 1;
81 printk(XENLOG_INFO "SMP: Allowing %u CPUs (%d hotplug CPUs)\n",
82 max_cpus, max_t(int, max_cpus - num_processors, 0));
83
84 if (!park_offline_cpus)
85 tot_cpus = max_cpus;
86 nr_cpu_ids = min(tot_cpus, NR_CPUS + 0u);
87 if (nr_cpu_ids < num_processors)
88 {
89 unaccounted_cpus = true;
90 if (park_offline_cpus)
91 printk(XENLOG_WARNING
92 "SMP: Cannot bring up %u further CPUs\n",
93 num_processors - nr_cpu_ids);
94 }
95
96 #ifndef nr_cpumask_bits
97 nr_cpumask_bits = ROUNDUP(nr_cpu_ids, BITS_PER_LONG);
98 printk(XENLOG_DEBUG "NR_CPUS:%u nr_cpumask_bits:%u\n",
99 NR_CPUS, nr_cpumask_bits);
100 #endif
101 }
102
set_nr_sockets(void)103 void __init set_nr_sockets(void)
104 {
105 nr_sockets = last_physid(phys_cpu_present_map)
106 / boot_cpu_data.x86_max_cores
107 / boot_cpu_data.x86_num_siblings + 1;
108 if (disabled_cpus)
109 nr_sockets += (disabled_cpus - 1)
110 / boot_cpu_data.x86_max_cores
111 / boot_cpu_data.x86_num_siblings + 1;
112 printk(XENLOG_DEBUG "nr_sockets: %u\n", nr_sockets);
113 }
114
115 /*
116 * Intel MP BIOS table parsing routines:
117 */
118
119
120 /*
121 * Checksum an MP configuration block.
122 */
123
mpf_checksum(unsigned char * mp,int len)124 static int __init mpf_checksum(unsigned char *mp, int len)
125 {
126 int sum = 0;
127
128 while (len--)
129 sum += *mp++;
130
131 return sum & 0xFF;
132 }
133
134 /* Return xen's logical cpu_id of the new added cpu or <0 if error */
MP_processor_info_x(struct mpc_config_processor * m,u32 apicid,bool hotplug)135 static int MP_processor_info_x(struct mpc_config_processor *m,
136 u32 apicid, bool hotplug)
137 {
138 int ver, cpu = 0;
139
140 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
141 if (!hotplug)
142 ++disabled_cpus;
143 return -EINVAL;
144 }
145
146 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
147 Dprintk(" Bootup CPU\n");
148 boot_cpu_physical_apicid = apicid;
149 }
150
151 ver = m->mpc_apicver;
152
153 /*
154 * Validate version
155 */
156 if (ver == 0x0) {
157 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
158 "fixing up to 0x10. (tell your hw vendor)\n",
159 apicid);
160 ver = 0x10;
161 }
162 apic_version[apicid] = ver;
163
164 set_apicid(apicid, &phys_cpu_present_map);
165
166 if (num_processors >= nr_cpu_ids) {
167 printk_once(XENLOG_WARNING
168 "WARNING: NR_CPUS limit of %u reached - ignoring further processors\n",
169 nr_cpu_ids);
170 unaccounted_cpus = true;
171 return -ENOSPC;
172 }
173
174 if (num_processors >= 8 && hotplug
175 && genapic.name == apic_default.name) {
176 printk_once(XENLOG_WARNING
177 "WARNING: CPUs limit of 8 reached - ignoring further processors\n");
178 unaccounted_cpus = true;
179 return -ENOSPC;
180 }
181
182 /* Boot cpu has been marked present in smp_prepare_boot_cpu */
183 if (!(m->mpc_cpuflag & CPU_BOOTPROCESSOR)) {
184 cpu = alloc_cpu_id();
185 if (cpu < 0) {
186 printk(KERN_WARNING "WARNING: Can't alloc cpu_id."
187 " Processor with apicid %i ignored\n", apicid);
188 return cpu;
189 }
190 x86_cpu_to_apicid[cpu] = apicid;
191 cpumask_set_cpu(cpu, &cpu_present_map);
192 }
193
194 if (++num_processors > 8) {
195 /*
196 * No need for processor or APIC checks: physical delivery
197 * (bigsmp) mode should always work.
198 */
199 def_to_bigsmp = true;
200 }
201
202 return cpu;
203 }
204
MP_processor_info(struct mpc_config_processor * m)205 static int MP_processor_info(struct mpc_config_processor *m)
206 {
207 return MP_processor_info_x(m, m->mpc_apicid, 0);
208 }
209
MP_bus_info(struct mpc_config_bus * m)210 static void __init MP_bus_info (struct mpc_config_bus *m)
211 {
212 char str[7];
213
214 memcpy(str, m->mpc_bustype, 6);
215 str[6] = 0;
216
217 #if 0 /* size of mpc_busid (8 bits) makes this check unnecessary */
218 if (m->mpc_busid >= MAX_MP_BUSSES) {
219 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
220 " is too large, max. supported is %d\n",
221 m->mpc_busid, str, MAX_MP_BUSSES - 1);
222 return;
223 }
224 #endif
225
226 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
227 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
228 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
229 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
230 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
231 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
232 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
233 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
234 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
235 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
236 } else {
237 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
238 }
239 }
240
MP_ioapic_info(struct mpc_config_ioapic * m)241 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
242 {
243 if (!(m->mpc_flags & MPC_APIC_USABLE))
244 return;
245
246 printk(KERN_INFO "I/O APIC #%d Version %d at %#x.\n",
247 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
248 if (nr_ioapics >= MAX_IO_APICS) {
249 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
250 MAX_IO_APICS, nr_ioapics);
251 panic("Recompile kernel with bigger MAX_IO_APICS\n");
252 }
253 if (!m->mpc_apicaddr) {
254 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
255 " found in MP table, skipping!\n");
256 return;
257 }
258 mp_ioapics[nr_ioapics] = *m;
259 nr_ioapics++;
260 }
261
MP_intsrc_info(struct mpc_config_intsrc * m)262 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
263 {
264 mp_irqs [mp_irq_entries] = *m;
265 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
266 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
267 m->mpc_irqtype, m->mpc_irqflag & 3,
268 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
269 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
270 if (++mp_irq_entries == MAX_IRQ_SOURCES)
271 panic("Max # of irq sources exceeded\n");
272 }
273
MP_lintsrc_info(struct mpc_config_lintsrc * m)274 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
275 {
276 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
277 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
278 m->mpc_irqtype, m->mpc_irqflag & 3,
279 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
280 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
281 /*
282 * Well it seems all SMP boards in existence
283 * use ExtINT/LVT1 == LINT0 and
284 * NMI/LVT2 == LINT1 - the following check
285 * will show us if this assumptions is false.
286 * Until then we do not have to add baggage.
287 */
288 if ((m->mpc_irqtype == mp_ExtINT) &&
289 (m->mpc_destapiclint != 0))
290 BUG();
291 if ((m->mpc_irqtype == mp_NMI) &&
292 (m->mpc_destapiclint != 1))
293 BUG();
294 }
295
296 /*
297 * Read/parse the MPC
298 */
299
smp_read_mpc(struct mp_config_table * mpc)300 static int __init smp_read_mpc(struct mp_config_table *mpc)
301 {
302 char str[16];
303 char oem[10];
304 int count=sizeof(*mpc);
305 unsigned char *mpt=((unsigned char *)mpc)+count;
306
307 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
308 printk(KERN_ERR "SMP mptable: bad signature [%#x]!\n",
309 *(u32 *)mpc->mpc_signature);
310 return 0;
311 }
312 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
313 printk(KERN_ERR "SMP mptable: checksum error!\n");
314 return 0;
315 }
316 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
317 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
318 mpc->mpc_spec);
319 return 0;
320 }
321 if (!mpc->mpc_lapic) {
322 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
323 return 0;
324 }
325 memcpy(oem,mpc->mpc_oem,8);
326 oem[8]=0;
327 printk(KERN_INFO "OEM ID: %s ",oem);
328
329 memcpy(str,mpc->mpc_productid,12);
330 str[12]=0;
331 printk("Product ID: %s ",str);
332
333 printk("APIC at: %#x\n", mpc->mpc_lapic);
334
335 /*
336 * Save the local APIC address (it might be non-default) -- but only
337 * if we're not using ACPI.
338 */
339 if (!acpi_lapic)
340 mp_lapic_addr = mpc->mpc_lapic;
341
342 /*
343 * Now process the configuration blocks.
344 */
345 while (count < mpc->mpc_length) {
346 switch(*mpt) {
347 case MP_PROCESSOR:
348 {
349 struct mpc_config_processor *m=
350 (struct mpc_config_processor *)mpt;
351
352 mpt += sizeof(*m);
353 count += sizeof(*m);
354
355 /* ACPI may have already provided this data. */
356 if (acpi_lapic)
357 break;
358
359 printk("Processor #%02x %u:%u APIC version %u%s\n",
360 m->mpc_apicid,
361 MASK_EXTR(m->mpc_cpufeature,
362 CPU_FAMILY_MASK),
363 MASK_EXTR(m->mpc_cpufeature,
364 CPU_MODEL_MASK),
365 m->mpc_apicver,
366 m->mpc_cpuflag & CPU_ENABLED
367 ? "" : " [disabled]");
368 MP_processor_info(m);
369 break;
370 }
371 case MP_BUS:
372 {
373 struct mpc_config_bus *m=
374 (struct mpc_config_bus *)mpt;
375 MP_bus_info(m);
376 mpt += sizeof(*m);
377 count += sizeof(*m);
378 break;
379 }
380 case MP_IOAPIC:
381 {
382 struct mpc_config_ioapic *m=
383 (struct mpc_config_ioapic *)mpt;
384 MP_ioapic_info(m);
385 mpt+=sizeof(*m);
386 count+=sizeof(*m);
387 break;
388 }
389 case MP_INTSRC:
390 {
391 struct mpc_config_intsrc *m=
392 (struct mpc_config_intsrc *)mpt;
393
394 MP_intsrc_info(m);
395 mpt+=sizeof(*m);
396 count+=sizeof(*m);
397 break;
398 }
399 case MP_LINTSRC:
400 {
401 struct mpc_config_lintsrc *m=
402 (struct mpc_config_lintsrc *)mpt;
403 MP_lintsrc_info(m);
404 mpt+=sizeof(*m);
405 count+=sizeof(*m);
406 break;
407 }
408 default:
409 {
410 count = mpc->mpc_length;
411 break;
412 }
413 }
414 }
415 if (!num_processors)
416 printk(KERN_ERR "SMP mptable: no processors registered!\n");
417 return num_processors;
418 }
419
ELCR_trigger(unsigned int irq)420 static int __init ELCR_trigger(unsigned int irq)
421 {
422 unsigned int port;
423
424 port = 0x4d0 + (irq >> 3);
425 return (inb(port) >> (irq & 7)) & 1;
426 }
427
construct_default_ioirq_mptable(int mpc_default_type)428 static void __init construct_default_ioirq_mptable(int mpc_default_type)
429 {
430 struct mpc_config_intsrc intsrc;
431 int i;
432 int ELCR_fallback = 0;
433
434 intsrc.mpc_type = MP_INTSRC;
435 intsrc.mpc_irqflag = 0; /* conforming */
436 intsrc.mpc_srcbus = 0;
437 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
438
439 intsrc.mpc_irqtype = mp_INT;
440
441 /*
442 * If true, we have an ISA/PCI system with no IRQ entries
443 * in the MP table. To prevent the PCI interrupts from being set up
444 * incorrectly, we try to use the ELCR. The sanity check to see if
445 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
446 * never be level sensitive, so we simply see if the ELCR agrees.
447 * If it does, we assume it's valid.
448 */
449 if (mpc_default_type == 5) {
450 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
451
452 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
453 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
454 else {
455 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
456 ELCR_fallback = 1;
457 }
458 }
459
460 for (i = 0; platform_legacy_irq(i); i++) {
461 switch (mpc_default_type) {
462 case 2:
463 if (i == 0 || i == 13)
464 continue; /* IRQ0 & IRQ13 not connected */
465 /* fall through */
466 default:
467 if (i == 2)
468 continue; /* IRQ2 is never connected */
469 }
470
471 if (ELCR_fallback) {
472 /*
473 * If the ELCR indicates a level-sensitive interrupt, we
474 * copy that information over to the MP table in the
475 * irqflag field (level sensitive, active high polarity).
476 */
477 if (ELCR_trigger(i))
478 intsrc.mpc_irqflag = 13;
479 else
480 intsrc.mpc_irqflag = 0;
481 }
482
483 intsrc.mpc_srcbusirq = i;
484 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
485 MP_intsrc_info(&intsrc);
486 }
487
488 intsrc.mpc_irqtype = mp_ExtINT;
489 intsrc.mpc_srcbusirq = 0;
490 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
491 MP_intsrc_info(&intsrc);
492 }
493
construct_default_ISA_mptable(int mpc_default_type)494 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
495 {
496 struct mpc_config_processor processor;
497 struct mpc_config_bus bus;
498 struct mpc_config_ioapic ioapic;
499 struct mpc_config_lintsrc lintsrc;
500 int linttypes[2] = { mp_ExtINT, mp_NMI };
501 int i;
502
503 /*
504 * local APIC has default address
505 */
506 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
507
508 /*
509 * 2 CPUs, numbered 0 & 1.
510 */
511 processor.mpc_type = MP_PROCESSOR;
512 /* Either an integrated APIC or a discrete 82489DX. */
513 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
514 processor.mpc_cpuflag = CPU_ENABLED;
515 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
516 (boot_cpu_data.x86_model << 4) |
517 boot_cpu_data.x86_mask;
518 processor.mpc_featureflag =
519 boot_cpu_data.x86_capability[FEATURESET_1d];
520 processor.mpc_reserved[0] = 0;
521 processor.mpc_reserved[1] = 0;
522 for (i = 0; i < 2; i++) {
523 processor.mpc_apicid = i;
524 MP_processor_info(&processor);
525 }
526
527 bus.mpc_type = MP_BUS;
528 bus.mpc_busid = 0;
529 switch (mpc_default_type) {
530 default:
531 printk("???\n");
532 printk(KERN_ERR "Unknown standard configuration %d\n",
533 mpc_default_type);
534 /* fall through */
535 case 1:
536 case 5:
537 memcpy(bus.mpc_bustype, "ISA ", 6);
538 break;
539 case 2:
540 case 6:
541 case 3:
542 memcpy(bus.mpc_bustype, "EISA ", 6);
543 break;
544 case 4:
545 case 7:
546 memcpy(bus.mpc_bustype, "MCA ", 6);
547 }
548 MP_bus_info(&bus);
549 if (mpc_default_type > 4) {
550 bus.mpc_busid = 1;
551 memcpy(bus.mpc_bustype, "PCI ", 6);
552 MP_bus_info(&bus);
553 }
554
555 ioapic.mpc_type = MP_IOAPIC;
556 ioapic.mpc_apicid = 2;
557 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
558 ioapic.mpc_flags = MPC_APIC_USABLE;
559 ioapic.mpc_apicaddr = 0xFEC00000;
560 MP_ioapic_info(&ioapic);
561
562 /*
563 * We set up most of the low 16 IO-APIC pins according to MPS rules.
564 */
565 construct_default_ioirq_mptable(mpc_default_type);
566
567 lintsrc.mpc_type = MP_LINTSRC;
568 lintsrc.mpc_irqflag = 0; /* conforming */
569 lintsrc.mpc_srcbusid = 0;
570 lintsrc.mpc_srcbusirq = 0;
571 lintsrc.mpc_destapic = MP_APIC_ALL;
572 for (i = 0; i < 2; i++) {
573 lintsrc.mpc_irqtype = linttypes[i];
574 lintsrc.mpc_destapiclint = i;
575 MP_lintsrc_info(&lintsrc);
576 }
577 }
578
efi_unmap_mpf(void)579 static __init void efi_unmap_mpf(void)
580 {
581 if (efi_enabled(EFI_BOOT))
582 clear_fixmap(FIX_EFI_MPF);
583 }
584
585 static struct intel_mp_floating *__initdata mpf_found;
586
587 /*
588 * Scan the memory blocks for an SMP configuration block.
589 */
get_smp_config(void)590 void __init get_smp_config (void)
591 {
592 struct intel_mp_floating *mpf = mpf_found;
593
594 /*
595 * ACPI supports both logical (e.g. Hyper-Threading) and physical
596 * processors, where MPS only supports physical.
597 */
598 if (acpi_lapic && acpi_ioapic) {
599 efi_unmap_mpf();
600 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
601 return;
602 }
603 else if (acpi_lapic)
604 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
605
606 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
607 if (mpf->mpf_feature2 & (1<<7)) {
608 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
609 pic_mode = true;
610 } else {
611 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
612 pic_mode = false;
613 }
614
615 /*
616 * Now see if we need to read further.
617 */
618 if (mpf->mpf_feature1 != 0) {
619
620 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
621 construct_default_ISA_mptable(mpf->mpf_feature1);
622
623 } else if (mpf->mpf_physptr) {
624
625 /*
626 * Read the physical hardware table. Anything here will
627 * override the defaults.
628 */
629 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
630 efi_unmap_mpf();
631 smp_found_config = false;
632 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
633 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
634 return;
635 }
636 /*
637 * If there are no explicit MP IRQ entries, then we are
638 * broken. We set up most of the low 16 IO-APIC pins to
639 * ISA defaults and hope it will work.
640 */
641 if (!mp_irq_entries) {
642 struct mpc_config_bus bus;
643
644 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
645
646 bus.mpc_type = MP_BUS;
647 bus.mpc_busid = 0;
648 memcpy(bus.mpc_bustype, "ISA ", 6);
649 MP_bus_info(&bus);
650
651 construct_default_ioirq_mptable(0);
652 }
653
654 } else
655 BUG();
656
657 efi_unmap_mpf();
658
659 printk(KERN_INFO "Processors: %d\n", num_processors);
660 /*
661 * Only use the first configuration found.
662 */
663 }
664
smp_scan_config(unsigned long base,unsigned long length)665 static int __init smp_scan_config (unsigned long base, unsigned long length)
666 {
667 unsigned int *bp = maddr_to_virt(base);
668 struct intel_mp_floating *mpf;
669
670 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
671 if (sizeof(*mpf) != 16)
672 printk("Error: MPF size\n");
673
674 while (length > 0) {
675 mpf = (struct intel_mp_floating *)bp;
676 if ((*bp == SMP_MAGIC_IDENT) &&
677 (mpf->mpf_length == 1) &&
678 !mpf_checksum((unsigned char *)bp, 16) &&
679 ((mpf->mpf_specification == 1)
680 || (mpf->mpf_specification == 4)) ) {
681
682 smp_found_config = true;
683 printk(KERN_INFO "found SMP MP-table at %08lx\n",
684 virt_to_maddr(mpf));
685 #if 0
686 reserve_bootmem(virt_to_maddr(mpf), PAGE_SIZE);
687 if (mpf->mpf_physptr) {
688 /*
689 * We cannot access to MPC table to compute
690 * table size yet, as only few megabytes from
691 * the bottom is mapped now.
692 * PC-9800's MPC table places on the very last
693 * of physical memory; so that simply reserving
694 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
695 * in reserve_bootmem.
696 */
697 unsigned long size = PAGE_SIZE;
698 unsigned long end = max_low_pfn * PAGE_SIZE;
699 if (mpf->mpf_physptr + size > end)
700 size = end - mpf->mpf_physptr;
701 reserve_bootmem(mpf->mpf_physptr, size);
702 }
703 #endif
704 mpf_found = mpf;
705 return 1;
706 }
707 bp += 4;
708 length -= 16;
709 }
710 return 0;
711 }
712
efi_check_config(void)713 static void __init efi_check_config(void)
714 {
715 struct intel_mp_floating *mpf;
716
717 if (efi.mps == EFI_INVALID_TABLE_ADDR)
718 return;
719
720 __set_fixmap(FIX_EFI_MPF, PFN_DOWN(efi.mps), __PAGE_HYPERVISOR);
721 mpf = fix_to_virt(FIX_EFI_MPF) + ((long)efi.mps & (PAGE_SIZE-1));
722
723 if (memcmp(mpf->mpf_signature, "_MP_", 4) == 0 &&
724 mpf->mpf_length == 1 &&
725 mpf_checksum((void *)mpf, 16) &&
726 (mpf->mpf_specification == 1 || mpf->mpf_specification == 4)) {
727 smp_found_config = true;
728 printk(KERN_INFO "SMP MP-table at %08lx\n", efi.mps);
729 mpf_found = mpf;
730 }
731 else
732 efi_unmap_mpf();
733 }
734
find_smp_config(void)735 void __init find_smp_config (void)
736 {
737 unsigned int address;
738
739 if (efi_enabled(EFI_BOOT)) {
740 efi_check_config();
741 return;
742 }
743
744 /*
745 * FIXME: Linux assumes you have 640K of base ram..
746 * this continues the error...
747 *
748 * 1) Scan the bottom 1K for a signature
749 * 2) Scan the top 1K of base RAM
750 * 3) Scan the 64K of bios
751 */
752 if (smp_scan_config(0x0,0x400) ||
753 smp_scan_config(639*0x400,0x400) ||
754 smp_scan_config(0xF0000,0x10000))
755 return;
756 /*
757 * If it is an SMP machine we should know now, unless the
758 * configuration is in an EISA/MCA bus machine with an
759 * extended bios data area.
760 *
761 * there is a real-mode segmented pointer pointing to the
762 * 4K EBDA area at 0x40E, calculate and scan it here.
763 *
764 * NOTE! There are Linux loaders that will corrupt the EBDA
765 * area, and as such this kind of SMP config may be less
766 * trustworthy, simply because the SMP table may have been
767 * stomped on during early boot. These loaders are buggy and
768 * should be fixed.
769 *
770 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
771 */
772
773 address = get_bios_ebda();
774 if (address)
775 smp_scan_config(address, 0x400);
776 }
777
778 /* --------------------------------------------------------------------------
779 ACPI-based MP Configuration
780 -------------------------------------------------------------------------- */
781
782 #ifdef CONFIG_ACPI
783
mp_register_lapic_address(u64 address)784 void __init mp_register_lapic_address (
785 u64 address)
786 {
787 if (!x2apic_enabled) {
788 mp_lapic_addr = (unsigned long) address;
789 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
790 }
791
792 if (boot_cpu_physical_apicid == -1U)
793 boot_cpu_physical_apicid = get_apic_id();
794
795 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
796 }
797
798
mp_register_lapic(u32 id,bool enabled,bool hotplug)799 int mp_register_lapic(u32 id, bool enabled, bool hotplug)
800 {
801 struct mpc_config_processor processor = {
802 .mpc_type = MP_PROCESSOR,
803 /* Note: We don't fill in fields not consumed anywhere. */
804 .mpc_apicid = id,
805 .mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR)),
806 .mpc_cpuflag = (enabled ? CPU_ENABLED : 0) |
807 (id == boot_cpu_physical_apicid ?
808 CPU_BOOTPROCESSOR : 0),
809 };
810
811 if (MAX_APICS <= id) {
812 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
813 id, MAX_APICS);
814 return -EINVAL;
815 }
816
817 return MP_processor_info_x(&processor, id, hotplug);
818 }
819
mp_unregister_lapic(uint32_t apic_id,uint32_t cpu)820 void mp_unregister_lapic(uint32_t apic_id, uint32_t cpu)
821 {
822 if (!cpu || (apic_id == boot_cpu_physical_apicid))
823 return;
824
825 if (x86_cpu_to_apicid[cpu] != apic_id)
826 return;
827
828 physid_clear(apic_id, phys_cpu_present_map);
829
830 x86_cpu_to_apicid[cpu] = BAD_APICID;
831 cpumask_clear_cpu(cpu, &cpu_present_map);
832 }
833
834 #define MP_ISA_BUS 0
835 #define MP_MAX_IOAPIC_PIN 127
836
837 static struct mp_ioapic_routing {
838 int gsi_base;
839 int gsi_end;
840 unsigned long pin_programmed[BITS_TO_LONGS(MP_MAX_IOAPIC_PIN + 1)];
841 } mp_ioapic_routing[MAX_IO_APICS];
842
843
mp_find_ioapic(int gsi)844 static int mp_find_ioapic (
845 int gsi)
846 {
847 unsigned int i;
848
849 /* Find the IOAPIC that manages this GSI. */
850 for (i = 0; i < nr_ioapics; i++) {
851 if ((gsi >= mp_ioapic_routing[i].gsi_base)
852 && (gsi <= mp_ioapic_routing[i].gsi_end))
853 return i;
854 }
855
856 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
857
858 return -1;
859 }
860
861
mp_register_ioapic(u8 id,u32 address,u32 gsi_base)862 void __init mp_register_ioapic (
863 u8 id,
864 u32 address,
865 u32 gsi_base)
866 {
867 int idx = 0;
868 int tmpid;
869
870 if (nr_ioapics >= MAX_IO_APICS) {
871 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
872 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
873 panic("Recompile kernel with bigger MAX_IO_APICS\n");
874 }
875 if (!address) {
876 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
877 " found in MADT table, skipping!\n");
878 return;
879 }
880
881 idx = nr_ioapics++;
882
883 mp_ioapics[idx].mpc_type = MP_IOAPIC;
884 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
885 mp_ioapics[idx].mpc_apicaddr = address;
886
887 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
888 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
889 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
890 tmpid = io_apic_get_unique_id(idx, id);
891 else
892 tmpid = id;
893 if (tmpid == -1) {
894 nr_ioapics--;
895 return;
896 }
897 mp_ioapics[idx].mpc_apicid = tmpid;
898 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
899
900 /*
901 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
902 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
903 */
904 mp_ioapic_routing[idx].gsi_base = gsi_base;
905 mp_ioapic_routing[idx].gsi_end = gsi_base +
906 io_apic_get_redir_entries(idx);
907
908 printk("IOAPIC[%d]: apic_id %d, version %d, address %#x, "
909 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
910 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
911 mp_ioapic_routing[idx].gsi_base,
912 mp_ioapic_routing[idx].gsi_end);
913
914 return;
915 }
916
highest_gsi(void)917 unsigned __init highest_gsi(void)
918 {
919 unsigned x, res = 0;
920 for (x = 0; x < nr_ioapics; x++)
921 if (res < mp_ioapic_routing[x].gsi_end)
922 res = mp_ioapic_routing[x].gsi_end;
923 return res;
924 }
925
io_apic_gsi_base(unsigned int apic)926 unsigned int io_apic_gsi_base(unsigned int apic)
927 {
928 return mp_ioapic_routing[apic].gsi_base;
929 }
930
mp_override_legacy_irq(u8 bus_irq,u8 polarity,u8 trigger,u32 gsi)931 void __init mp_override_legacy_irq (
932 u8 bus_irq,
933 u8 polarity,
934 u8 trigger,
935 u32 gsi)
936 {
937 struct mpc_config_intsrc intsrc;
938 int ioapic = -1;
939 int pin = -1;
940
941 /*
942 * Convert 'gsi' to 'ioapic.pin'.
943 */
944 ioapic = mp_find_ioapic(gsi);
945 if (ioapic < 0)
946 return;
947 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
948
949 /*
950 * TBD: This check is for faulty timer entries, where the override
951 * erroneously sets the trigger to level, resulting in a HUGE
952 * increase of timer interrupts!
953 */
954 if ((bus_irq == 0) && (trigger == 3))
955 trigger = 1;
956
957 intsrc.mpc_type = MP_INTSRC;
958 intsrc.mpc_irqtype = mp_INT;
959 intsrc.mpc_irqflag = (trigger << 2) | polarity;
960 intsrc.mpc_srcbus = MP_ISA_BUS;
961 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
962 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
963 intsrc.mpc_dstirq = pin; /* INTIN# */
964
965 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
966 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
967 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
968 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
969
970 mp_irqs[mp_irq_entries] = intsrc;
971 if (++mp_irq_entries == MAX_IRQ_SOURCES)
972 panic("Max # of irq sources exceeded\n");
973
974 return;
975 }
976
mp_config_acpi_legacy_irqs(void)977 void __init mp_config_acpi_legacy_irqs (void)
978 {
979 struct mpc_config_intsrc intsrc;
980 int i = 0;
981 int ioapic = -1;
982
983 /*
984 * Fabricate the legacy ISA bus (bus #31).
985 */
986 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
987 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
988
989 /*
990 * Locate the IOAPIC that manages the ISA IRQs (0-15).
991 */
992 ioapic = mp_find_ioapic(0);
993 if (ioapic < 0)
994 return;
995
996 intsrc.mpc_type = MP_INTSRC;
997 intsrc.mpc_irqflag = 0; /* Conforming */
998 intsrc.mpc_srcbus = MP_ISA_BUS;
999 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1000
1001 /*
1002 * Use the default configuration for the IRQs 0-15. Unless
1003 * overriden by (MADT) interrupt source override entries.
1004 */
1005 for (i = 0; platform_legacy_irq(i); i++) {
1006 int idx;
1007
1008 for (idx = 0; idx < mp_irq_entries; idx++) {
1009 struct mpc_config_intsrc *irq = mp_irqs + idx;
1010
1011 /* Do we already have a mapping for this ISA IRQ? */
1012 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1013 break;
1014
1015 /* Do we already have a mapping for this IOAPIC pin */
1016 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1017 (irq->mpc_dstirq == i))
1018 break;
1019 }
1020
1021 if (idx != mp_irq_entries) {
1022 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1023 continue; /* IRQ already used */
1024 }
1025
1026 intsrc.mpc_irqtype = mp_INT;
1027 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1028 intsrc.mpc_dstirq = i;
1029
1030 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1031 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1032 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1033 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1034 intsrc.mpc_dstirq);
1035
1036 mp_irqs[mp_irq_entries] = intsrc;
1037 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1038 panic("Max # of irq sources exceeded\n");
1039 }
1040 }
1041
mp_register_gsi(u32 gsi,int triggering,int polarity)1042 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1043 {
1044 int ioapic;
1045 int ioapic_pin;
1046 struct irq_desc * desc;
1047 unsigned long flags;
1048
1049 /*
1050 * Mapping between Global System Interrups, which
1051 * represent all possible interrupts, and IRQs
1052 * assigned to actual devices.
1053 */
1054
1055 #ifdef CONFIG_ACPI_BUS
1056 /* Don't set up the ACPI SCI because it's already set up */
1057 if (acpi_fadt.sci_int == gsi)
1058 return gsi;
1059 #endif
1060
1061 if (!nr_ioapics) {
1062 unsigned int port = 0x4d0 + (gsi >> 3);
1063 u8 val;
1064
1065 if (!platform_legacy_irq(gsi))
1066 return -EINVAL;
1067 val = inb(port);
1068 if (triggering)
1069 val |= 1 << (gsi & 7);
1070 else
1071 val &= ~(1 << (gsi & 7));
1072 outb(val, port);
1073 return 0;
1074 }
1075
1076 ioapic = mp_find_ioapic(gsi);
1077 if (ioapic < 0) {
1078 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1079 return -EINVAL;
1080 }
1081
1082 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1083
1084 desc = irq_to_desc(gsi);
1085 spin_lock_irqsave(&desc->lock, flags);
1086 if (!(desc->status & IRQ_DISABLED) && desc->handler != &no_irq_type) {
1087 spin_unlock_irqrestore(&desc->lock, flags);
1088 return -EEXIST;
1089 }
1090 spin_unlock_irqrestore(&desc->lock, flags);
1091
1092 /*
1093 * Avoid pin reprogramming. PRTs typically include entries
1094 * with redundant pin->gsi mappings (but unique PCI devices);
1095 * we only program the IOAPIC on the first.
1096 */
1097 if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
1098 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1099 "%d-%d\n", mp_ioapics[ioapic].mpc_apicid,
1100 ioapic_pin);
1101 return -EINVAL;
1102 }
1103 if (test_and_set_bit(ioapic_pin,
1104 mp_ioapic_routing[ioapic].pin_programmed)) {
1105 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1106 mp_ioapics[ioapic].mpc_apicid, ioapic_pin);
1107 return -EEXIST;
1108 }
1109
1110 return io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1111 triggering, polarity);
1112 }
1113
1114 #endif /* CONFIG_ACPI */
1115