1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * arch-x86/cpufeatureset.h 4 * 5 * CPU featureset definitions 6 * 7 * Copyright (c) 2015, 2016 Citrix Systems, Inc. 8 */ 9 10 /* 11 * There are two expected ways of including this header. 12 * 13 * 1) The "default" case (expected from tools etc). 14 * 15 * Simply #include <public/arch-x86/cpufeatureset.h> 16 * 17 * In this circumstance, normal header guards apply and the includer shall get 18 * an enumeration in the XEN_X86_FEATURE_xxx namespace. 19 * 20 * 2) The special case where the includer provides XEN_CPUFEATURE() in scope. 21 * 22 * In this case, no inclusion guards apply and the caller is responsible for 23 * their XEN_CPUFEATURE() being appropriate in the included context. 24 */ 25 26 #ifndef XEN_CPUFEATURE 27 28 /* 29 * Includer has not provided a custom XEN_CPUFEATURE(). Arrange for normal 30 * header guards, an enum and constants in the XEN_X86_FEATURE_xxx namespace. 31 */ 32 #ifndef __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ 33 #define __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ 34 35 #define XEN_CPUFEATURESET_DEFAULT_INCLUDE 36 37 #define XEN_CPUFEATURE(name, value) XEN_X86_FEATURE_##name = value, 38 enum { 39 40 #endif /* __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ */ 41 #endif /* !XEN_CPUFEATURE */ 42 43 44 #ifdef XEN_CPUFEATURE 45 /* 46 * A featureset is a bitmap of x86 features, represented as a collection of 47 * 32bit words. 48 * 49 * Words are as specified in vendors programming manuals, and shall not 50 * contain any synthesied values. New words may be added to the end of 51 * featureset. 52 * 53 * All featureset words currently originate from leaves specified for the 54 * CPUID instruction, but this is not preclude other sources of information. 55 */ 56 57 /* 58 * Attribute syntax: 59 * 60 * Attributes for a particular feature are provided as characters before the 61 * first space in the comment immediately following the feature value. Note - 62 * none of these attributes form part of the Xen public ABI. 63 * 64 * Special: '!' 65 * This bit has special properties and is not a straight indication of a 66 * piece of new functionality. Xen will handle these differently, 67 * and may override toolstack settings completely. 68 * 69 * Applicability to guests: 'A', 'S' or 'H' 70 * 'A' = All guests. 71 * 'S' = All HVM guests (not PV guests). 72 * 'H' = HVM HAP guests (not PV or HVM Shadow guests). 73 * Upper case => Available by default 74 * Lower case => Can be opted-in to, but not available by default. 75 * 76 * Migration: '|' 77 * This bit should be visible to a guest if any anywhere it might run has 78 * the bit set. i.e. it needs accumulating across the migration pool, 79 * rather than intersecting. 80 */ 81 82 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ 83 XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ 84 XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ 85 XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ 86 XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ 87 XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ 88 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ 89 XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ 90 XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ 91 XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ 92 XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ 93 XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ 94 XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ 95 XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ 96 XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ 97 XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ 98 XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ 99 XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */ 100 XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ 101 XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ 102 XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ 103 XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ 104 XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ 105 XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ 106 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ 107 XEN_CPUFEATURE(SS, 0*32+27) /*A CPU self snoop */ 108 XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ 109 XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ 110 XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ 111 112 /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ 113 XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ 114 XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */ 115 XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ 116 XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ 117 XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ 118 XEN_CPUFEATURE(VMX, 1*32+ 5) /*h Virtual Machine Extensions */ 119 XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ 120 XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ 121 XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ 122 XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ 123 XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ 124 XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ 125 XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ 126 XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ 127 XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ 128 XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ 129 XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ 130 XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ 131 XEN_CPUFEATURE(X2APIC, 1*32+21) /*!S Extended xAPIC */ 132 XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ 133 XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ 134 XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ 135 XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ 136 XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ 137 XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ 138 XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ 139 XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ 140 XEN_CPUFEATURE(RDRAND, 1*32+30) /*!A Digital Random Number Generator */ 141 XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */ 142 143 /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ 144 XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ 145 XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ 146 XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ 147 XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ 148 XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ 149 XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */ 150 XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ 151 XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ 152 XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ 153 154 /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ 155 XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ 156 XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ 157 XEN_CPUFEATURE(SVM, 3*32+ 2) /*h Secure virtual machine */ 158 XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ 159 XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ 160 XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ 161 XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ 162 XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ 163 XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ 164 XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ 165 XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ 166 XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ 167 XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ 168 XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ 169 XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ 170 XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ 171 XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ 172 XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ 173 XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ 174 XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ 175 XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ 176 XEN_CPUFEATURE(ADDR_MSK_EXT, 3*32+30) /*A Address Mask Extentions */ 177 178 /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ 179 XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ 180 XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ 181 XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ 182 XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ 183 184 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ 185 XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ 186 XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ 187 XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */ 188 XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ 189 XEN_CPUFEATURE(HLE, 5*32+ 4) /*!a Hardware Lock Elision */ 190 XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ 191 XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ 192 XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ 193 XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ 194 XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ 195 XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ 196 XEN_CPUFEATURE(RTM, 5*32+11) /*!A Restricted Transactional Memory */ 197 XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ 198 XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ 199 XEN_CPUFEATURE(MPX, 5*32+14) /*s Memory Protection Extensions */ 200 XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ 201 XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */ 202 XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */ 203 XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ 204 XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ 205 XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ 206 XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */ 207 XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ 208 XEN_CPUFEATURE(CLWB, 5*32+24) /*!A CLWB instruction */ 209 XEN_CPUFEATURE(PROC_TRACE, 5*32+25) /* Processor Trace */ 210 XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */ 211 XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */ 212 XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */ 213 XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ 214 XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */ 215 XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */ 216 217 /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ 218 XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ 219 XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */ 220 XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */ 221 XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ 222 XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ 223 XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */ 224 XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */ 225 XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */ 226 XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */ 227 XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */ 228 XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */ 229 XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 230 XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */ 231 XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */ 232 XEN_CPUFEATURE(BLD, 6*32+24) /* BusLock Detect (#DB trap) support */ 233 XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */ 234 XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */ 235 XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */ 236 XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */ 237 XEN_CPUFEATURE(PKS, 6*32+31) /*H Protection Key for Supervisor */ 238 239 /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ 240 XEN_CPUFEATURE(HW_PSTATE, 7*32+ 7) /* Hardware Pstates */ 241 XEN_CPUFEATURE(ITSC, 7*32+ 8) /*a Invariant TSC */ 242 XEN_CPUFEATURE(CPB, 7*32+ 9) /* Core Performance Boost (Turbo) */ 243 XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ 244 245 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ 246 XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ 247 XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ 248 XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ 249 XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ 250 XEN_CPUFEATURE(IBRS, 8*32+14) /*S MSR_SPEC_CTRL.IBRS */ 251 XEN_CPUFEATURE(AMD_STIBP, 8*32+15) /*S MSR_SPEC_CTRL.STIBP */ 252 XEN_CPUFEATURE(IBRS_ALWAYS, 8*32+16) /*S IBRS preferred always on */ 253 XEN_CPUFEATURE(STIBP_ALWAYS, 8*32+17) /*S STIBP preferred always on */ 254 XEN_CPUFEATURE(IBRS_FAST, 8*32+18) /*S IBRS preferred over software options */ 255 XEN_CPUFEATURE(IBRS_SAME_MODE, 8*32+19) /*S IBRS provides same-mode protection */ 256 XEN_CPUFEATURE(NO_LMSL, 8*32+20) /*S| EFER.LMSLE no longer supported. */ 257 XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ 258 XEN_CPUFEATURE(AMD_SSBD, 8*32+24) /*S MSR_SPEC_CTRL.SSBD available */ 259 XEN_CPUFEATURE(VIRT_SSBD, 8*32+25) /*! MSR_VIRT_SPEC_CTRL.SSBD */ 260 XEN_CPUFEATURE(SSB_NO, 8*32+26) /*A Hardware not vulnerable to SSB */ 261 XEN_CPUFEATURE(PSFD, 8*32+28) /*S MSR_SPEC_CTRL.PSFD */ 262 XEN_CPUFEATURE(BTC_NO, 8*32+29) /*A Hardware not vulnerable to Branch Type Confusion */ 263 XEN_CPUFEATURE(IBPB_RET, 8*32+30) /*A IBPB clears RSB/RAS too. */ 264 265 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ 266 XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ 267 XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ 268 XEN_CPUFEATURE(FSRM, 9*32+ 4) /*A Fast Short REP MOVS */ 269 XEN_CPUFEATURE(UINTR, 9*32+ 5) /* User-mode Interrupts */ 270 XEN_CPUFEATURE(AVX512_VP2INTERSECT, 9*32+8) /*a VP2INTERSECT{D,Q} insns */ 271 XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */ 272 XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*!A| VERW clears microarchitectural buffers */ 273 XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! RTM disabled (but XBEGIN wont fault) */ 274 XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ 275 XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ 276 XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ 277 XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */ 278 XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Record */ 279 XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ 280 XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ 281 XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ 282 XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ 283 XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ 284 XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ 285 XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /*!A IA32_ARCH_CAPABILITIES MSR */ 286 XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ 287 XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ 288 289 /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ 290 XEN_CPUFEATURE(SHA512, 10*32+ 0) /*A SHA512 Instructions */ 291 XEN_CPUFEATURE(SM3, 10*32+ 1) /*A SM3 Instructions */ 292 XEN_CPUFEATURE(SM4, 10*32+ 2) /*A SM4 Instructions */ 293 XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ 294 XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ 295 XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ 296 XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */ 297 XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ 298 XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */ 299 XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ 300 301 /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ 302 XEN_CPUFEATURE(NO_NEST_BP, 11*32+ 0) /*A No Nested Data Breakpoints */ 303 XEN_CPUFEATURE(FS_GS_NS, 11*32+ 1) /*S| FS/GS base MSRs non-serialising */ 304 XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ 305 XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */ 306 XEN_CPUFEATURE(AUTO_IBRS, 11*32+ 8) /*S Automatic IBRS */ 307 XEN_CPUFEATURE(AMD_FSRS, 11*32+10) /*A Fast Short REP STOSB */ 308 XEN_CPUFEATURE(AMD_FSRC, 11*32+11) /*A Fast Short REP CMPSB */ 309 XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for CPL > 0 software */ 310 XEN_CPUFEATURE(EPSF, 11*32+18) /*A Enhanced Predictive Store Forwarding */ 311 XEN_CPUFEATURE(FSRSC, 11*32+19) /*A Fast Short REP SCASB */ 312 XEN_CPUFEATURE(AMD_PREFETCHI, 11*32+20) /*A PREFETCHIT{0,1} Instructions */ 313 XEN_CPUFEATURE(SBPB, 11*32+27) /*A Selective Branch Predictor Barrier */ 314 XEN_CPUFEATURE(IBPB_BRTYPE, 11*32+28) /*A IBPB flushes Branch Type predictions too */ 315 XEN_CPUFEATURE(SRSO_NO, 11*32+29) /*A Hardware not vulenrable to Speculative Return Stack Overflow */ 316 317 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */ 318 XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory Number */ 319 320 /* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */ 321 XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */ 322 XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*S MSR_SPEC_CTRL.IPRED_DIS_* */ 323 XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*S MSR_SPEC_CTRL.RRSBA_DIS_* */ 324 XEN_CPUFEATURE(DDP_CTRL, 13*32+ 3) /* MSR_SPEC_CTRL.DDP_DIS_U */ 325 XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*S MSR_SPEC_CTRL.BHI_DIS_S */ 326 XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */ 327 328 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */ 329 330 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ 331 XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructions */ 332 XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32+ 5) /*A AVX-NE-CONVERT Instructions */ 333 XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructions */ 334 XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instructions */ 335 XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */ 336 337 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ 338 XEN_CPUFEATURE(RDCL_NO, 16*32+ 0) /*A No Rogue Data Cache Load (Meltdown) */ 339 XEN_CPUFEATURE(EIBRS, 16*32+ 1) /*A Enhanced IBRS */ 340 XEN_CPUFEATURE(RSBA, 16*32+ 2) /*! RSB Alternative (Retpoline not safe) */ 341 XEN_CPUFEATURE(SKIP_L1DFL, 16*32+ 3) /* Don't need to flush L1D on VMEntry */ 342 XEN_CPUFEATURE(INTEL_SSB_NO, 16*32+ 4) /*A No Speculative Store Bypass */ 343 XEN_CPUFEATURE(MDS_NO, 16*32+ 5) /*A No Microarchitectural Data Sampling */ 344 XEN_CPUFEATURE(IF_PSCHANGE_MC_NO, 16*32+ 6) /*A No Instruction fetch #MC */ 345 XEN_CPUFEATURE(TSX_CTRL, 16*32+ 7) /* MSR_TSX_CTRL */ 346 XEN_CPUFEATURE(TAA_NO, 16*32+ 8) /*A No TSX Async Abort */ 347 XEN_CPUFEATURE(MCU_CTRL, 16*32+ 9) /* MSR_MCU_CTRL */ 348 XEN_CPUFEATURE(MISC_PKG_CTRL, 16*32+10) /* MSR_MISC_PKG_CTRL */ 349 XEN_CPUFEATURE(ENERGY_FILTERING, 16*32+11) /* MSR_MISC_PKG_CTRL.ENERGY_FILTERING */ 350 XEN_CPUFEATURE(DOITM, 16*32+12) /* Data Operand Invariant Timing Mode */ 351 XEN_CPUFEATURE(SBDR_SSDP_NO, 16*32+13) /*A No Shared Buffer Data Read or Sideband Stale Data Propagation */ 352 XEN_CPUFEATURE(FBSDP_NO, 16*32+14) /*A No Fill Buffer Stale Data Propagation */ 353 XEN_CPUFEATURE(PSDP_NO, 16*32+15) /*A No Primary Stale Data Propagation */ 354 XEN_CPUFEATURE(FB_CLEAR, 16*32+17) /*!A| Fill Buffers cleared by VERW */ 355 XEN_CPUFEATURE(FB_CLEAR_CTRL, 16*32+18) /* MSR_OPT_CPU_CTRL.FB_CLEAR_DIS */ 356 XEN_CPUFEATURE(RRSBA, 16*32+19) /*! Restricted RSB Alternative */ 357 XEN_CPUFEATURE(BHI_NO, 16*32+20) /*A No Branch History Injection */ 358 XEN_CPUFEATURE(XAPIC_STATUS, 16*32+21) /* MSR_XAPIC_DISABLE_STATUS */ 359 XEN_CPUFEATURE(OVRCLK_STATUS, 16*32+23) /* MSR_OVERCLOCKING_STATUS */ 360 XEN_CPUFEATURE(PBRSB_NO, 16*32+24) /*A No Post-Barrier RSB predictions */ 361 XEN_CPUFEATURE(GDS_CTRL, 16*32+25) /* MCU_OPT_CTRL.GDS_MIT_{DIS,LOCK} */ 362 XEN_CPUFEATURE(GDS_NO, 16*32+26) /*A No Gather Data Sampling */ 363 XEN_CPUFEATURE(RFDS_NO, 16*32+27) /*A No Register File Data Sampling */ 364 XEN_CPUFEATURE(RFDS_CLEAR, 16*32+28) /*!A| Register File(s) cleared by VERW */ 365 366 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */ 367 368 #endif /* XEN_CPUFEATURE */ 369 370 /* Clean up from a default include. Close the enum (for C). */ 371 #ifdef XEN_CPUFEATURESET_DEFAULT_INCLUDE 372 #undef XEN_CPUFEATURESET_DEFAULT_INCLUDE 373 #undef XEN_CPUFEATURE 374 }; 375 376 #endif /* XEN_CPUFEATURESET_DEFAULT_INCLUDE */ 377 378 /* 379 * Local variables: 380 * mode: C 381 * c-file-style: "BSD" 382 * c-basic-offset: 4 383 * tab-width: 4 384 * indent-tabs-mode: nil 385 * End: 386 */ 387