Searched refs:APLL (Results 1 – 12 of 12) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| A D | apll.txt | 1 Binding for Texas Instruments APLL clock.
4 register-mapped APLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) APLL mostly behaves like
18 - reg : address and length of the register set for controlling the APLL.
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| /linux/include/dt-bindings/clock/ |
| A D | xlnx-versal-clk.h | 27 #define APLL 18 macro
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| A D | xlnx-zynqmp-clk.h | 14 #define APLL 2 macro
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| A D | nuvoton,ma35d1-clk.h | 22 #define APLL 11 macro
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
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| /linux/arch/arm64/boot/dts/nuvoton/ |
| A D | ma35d1-iot-512m.dts | 43 <&clk APLL>,
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| A D | ma35d1-som-256m.dts | 43 <&clk APLL>,
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| /linux/drivers/clk/nuvoton/ |
| A D | clk-ma35d1-pll.c | 236 case APLL: in ma35d1_clk_pll_recalc_rate()
268 case APLL: in ma35d1_clk_pll_round_rate()
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| A D | clk-ma35d1.c | 506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
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| /linux/drivers/clk/ingenic/ |
| A D | jz4780-cgu.c | 295 .pll = DEF_PLL(APLL),
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| /linux/Documentation/devicetree/bindings/arm/marvell/ |
| A D | cp110-system-controller.txt | 35 - 0 0 APLL
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| /linux/arch/arm/boot/dts/rockchip/ |
| A D | rk3036.dtsi | 238 * Fix the emac parent clock is DPLL instead of APLL.
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