| /linux/drivers/staging/rtl8723bs/include/ |
| A D | hal_pwr_seq.h | 48 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x…
56 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin…
57 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 …
60 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR …
71 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 …
94 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
114 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
157 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] =…
181 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA…
195 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] =…
[all …]
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| A D | rtw_ht.h | 65 #define LDPC_HT_ENABLE_TX BIT1
69 #define STBC_HT_ENABLE_TX BIT1
73 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
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| A D | hal_com_reg.h | 221 #define RRSR_2M BIT1
293 #define RCR_APM BIT1 /* Accept physical match packet */
548 #define SDIO_HIMR_AVAL_MSK BIT1
552 #define SDIO_HISR_AVAL BIT1
597 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */
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| A D | hal_phy.h | 14 #define ANT_DETECT_BY_RSSI BIT1
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| A D | rtl8723b_spec.h | 213 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
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| A D | osdep_service.h | 18 #define BIT1 0x00000002 macro
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| A D | pwrseq.h | 29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
392 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
435 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
459 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
505 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
546 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
[all …]
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| /linux/drivers/scsi/ |
| A D | dc395x.h | 75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
593 #define GREATER_1G BIT1
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| /linux/drivers/video/fbdev/via/ |
| A D | dvi.c | 45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
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| A D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
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| A D | via_utility.c | 170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
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| A D | share.h | 15 #define BIT1 0x02 macro
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| /linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| A D | halbt_precomp.h | 32 #define BIT1 0x00000002 macro
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| A D | halbtc8192e2ant.h | 13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
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| A D | halbtc8821a1ant.h | 14 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
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| A D | halbtc8821a2ant.h | 14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
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| A D | halbtc8723b2ant.h | 16 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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| A D | halbtc8723b1ant.h | 13 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
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| /linux/drivers/tty/ |
| A D | synclink_gt.c | 351 #define MASK_PARITY BIT1
1784 if (status & BIT1) in rx_async()
1791 if (status & BIT1) in rx_async()
1969 if (status & BIT1) { in dcd_change()
3775 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3788 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
4309 val |= BIT1 + BIT0; in sync_mode()
4419 if (status & BIT1) in get_gtsignals()
4461 val |= BIT1; in msc_set_vcr()
4577 status &= ~BIT1; in rx_get_frame()
[all …]
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| /linux/drivers/staging/rtl8723bs/hal/ |
| A D | odm_DIG.h | 82 ODM_RESUME_DIG = BIT1
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| A D | HalHWImg8723B_MAC.c | 58 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
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| A D | HalBtc8723b2Ant.h | 14 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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| A D | HalBtc8723b1Ant.h | 14 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
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| A D | HalHWImg8723B_RF.c | 64 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
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| /linux/include/uapi/linux/ |
| A D | synclink.h | 20 #define BIT1 0x0002 macro
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